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Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Aaron Durbin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#12).
Change subject: soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
......................................................................
soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake
Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To
be able to override the GPE0_STS mask as well, also pass that one. To
accomplish that, pointers to the variables are passed now.
Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
2 files changed, 10 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58071/12
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58198 )
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58198/comment/7052235a_684f97a0
PS1, Line 16: Cq-Depend: chrome-internal:4157948
Nit: Move this line right above Change-Id line.
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/58198/comment/4530ca61_8a1c907e
PS1, Line 54: NVME
> Do we need to specify the NVMe pin as well now?
SSD_AUX_RST_L/AGPIO40 is in S5 domain. So I dont think FSP passes that GPIO to SMU. It passes GPIOs in S0 domain only.
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Change subject: vc/amd/fsp/cezanne: Update Cezanne FSP-M UPD definition
......................................................................
Patch Set 2: Code-Review+2
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Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
......................................................................
Patch Set 5:
(14 comments)
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/f8ff249f_88db1f26
PS5, Line 15: [CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/c502b941_9493a558
PS5, Line 16: [CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/ecb52729_d92ac7d5
PS5, Line 17: [CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/09d527ed_80114ee8
PS5, Line 18: [CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/1ebbca4e_1e63ff51
PS5, Line 20: [CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/20aec8af_cefeb3ab
PS5, Line 21: [CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/6cde550e_9948c649
PS5, Line 22: [CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/0455c36d_c06eabd2
PS5, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/81860434_047e5900
PS5, Line 26: [CPPC_REF_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/a478ddd8_ee521a60
PS5, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/859644e0_19095b47
PS5, Line 27: [CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG( ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/c04daedf_382e5fb4
PS5, Line 28: [CPPC_PERF_LIMITED] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/33a677c3_d4591a29
PS5, Line 29: [CPPC_ENABLE] = CPPC_REG( ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1),
space prohibited after that open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130063):
https://review.coreboot.org/c/coreboot/+/58118/comment/9042a181_d6fe1b3b
PS5, Line 34: [CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8),
line over 96 characters
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Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
......................................................................
Patch Set 8:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/c63929c7_6ed600bd
PS8, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/1a2ab5d9_0e59a0ae
PS8, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/180a50f3_90fb1d39
PS8, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/323f162d_bf3daec3
PS8, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/1abb7cc3_f91bf6d9
PS8, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/21272585_68b7081b
PS8, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/90153ddb_4cb4a794
PS8, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/02d178fc_21968fd4
PS8, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/9b6af4cb_cc93428d
PS8, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/bcda7aeb_e485e46b
PS8, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/2b1dd3ad_095424e4
PS8, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/7c875dce_0e44a241
PS8, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/dbd34080_01168e28
PS8, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/9a1bc360_9df7cba0
PS8, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062):
https://review.coreboot.org/c/coreboot/+/57886/comment/72d7bff0_dd86b114
PS8, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
line over 96 characters
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Change subject: mb/google/caroline: Update _HID for digitizer
......................................................................
Patch Set 1: Code-Review+2
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Change subject: payloads/tianocore/Kconfig: Extend help for bootsplash file
......................................................................
Patch Set 3: Code-Review+2
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Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58181
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Change subject: soc/intel/common/cse: Support RW update when stitching CSE binary
......................................................................
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config. Also, $(CSE_LITE_ME_RW)-file is
updated to be evaluated every time it is used so that there is no
dependency on the order of definitions in Makefile.inc.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
2 files changed, 11 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/58181/4
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Hello build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58126
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Change subject: mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd
......................................................................
mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: I4da677da2e24b0398d04786e71490611db635ead
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/brya/chromeos.fmd
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/58126/12
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