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Furquan Shaikh has uploaded a new patch set (#15) to the change originally created by Bernardo Perez Priego. ( https://review.coreboot.org/c/coreboot/+/57353 )
Change subject: soc/intel/common/cse: Add support for stitching CSE components
......................................................................
soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
BUG=b:189177580
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
A src/soc/intel/Makefile.inc
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
3 files changed, 170 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/57353/15
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I'd like you to reexamine a change. Please visit
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Change subject: Makefile: Add src/soc/* to subdirs
......................................................................
Makefile: Add src/soc/* to subdirs
This change adds src/soc/* to subdirs before src/soc/*/* to allow
Makefile in src/soc/* to provide any common helpers that will be
useful for any src/soc/*/*. This is done to primarily ensure that the
helpers are defined before being invoked by the SoC Makefile.inc. This
is utilized by Intel CSE stitching mechanism in following changes.
BUG=b:189177580
Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58124/10
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Change subject: southbridge/intel/common: Add an option to allow stitching of CSE binary
......................................................................
southbridge/intel/common: Add an option to allow stitching of CSE binary
In the following changes, CSE binary for some platforms will be
stitched at build time instead of adding a pre-built binary. This
change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to
select if it wants to stitch CSE binary instead of adding a pre-built
one. In this case, ME_BIN_PATH is not visible to user and instead
mainboard and/or SoC code is expected to provide the recipe for
stitching the CSE image.
BUG=b:189177580
Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/southbridge/intel/common/firmware/Kconfig
M src/southbridge/intel/common/firmware/Makefile.inc
2 files changed, 25 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58083/11
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I'd like you to reexamine a change. Please visit
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Change subject: util/cse_serger: Add a new tool for stitching CSE components
......................................................................
util/cse_serger: Add a new tool for stitching CSE components
This change adds a new tool `cse_serger` which can be used to print,
dump and stitch together different components for the CSE region.
BUG=b:189177186
Change-Id: I90dd809b47fd16afdc80e66431312721082496aa
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M Makefile.inc
M util/cbfstool/Makefile
M util/cbfstool/Makefile.inc
A util/cbfstool/bpdt_formats/Makefile.inc
A util/cbfstool/bpdt_formats/bpdt_1_6.c
A util/cbfstool/bpdt_formats/bpdt_1_7.c
A util/cbfstool/bpdt_formats/subpart_entry_1.c
A util/cbfstool/bpdt_formats/subpart_hdr_1.c
A util/cbfstool/bpdt_formats/subpart_hdr_2.c
A util/cbfstool/cse_serger.c
A util/cbfstool/cse_serger.h
11 files changed, 1,960 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55503/21
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Change subject: util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries
......................................................................
util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries
This change adds a new tool `cse_fpt` which can be used to print and
dump CSE partitions in Flash Partition Table (FPT) format.
BUG=b:189167923
Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M Makefile.inc
M util/cbfstool/Makefile
M util/cbfstool/Makefile.inc
A util/cbfstool/cse_fpt.c
A util/cbfstool/cse_fpt.h
A util/cbfstool/fpt_formats/Makefile.inc
A util/cbfstool/fpt_formats/fpt_hdr_20.c
A util/cbfstool/fpt_formats/fpt_hdr_21.c
8 files changed, 721 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/55259/19
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Change subject: soc/intel/common/cse: Split CSE metadata into two CBFS files
......................................................................
soc/intel/common/cse: Split CSE metadata into two CBFS files
This change splits CSE metadata structure (added to CBFS) into two
separate CBFS files (me_rw.hash and me_rw.version). Since `struct
cse_rw_metadata` is now used, it is dropped completely.
This change is being made in order to prepare for the upcoming changes
to stitch CSE binary at build time. Since the binary might not be
available pre-built, it complicates the order of operations for the
addition of CSE metadata structure and declaring hash and version as
CPPFLAGS_common. Instead rules can be enabled for individual CBFS file
targets for hash and version that ensure proper ordering as well.
BUG=b:184892226
TEST=Ensured that update works correctly on brya by forcing version
mismatch. In case of version match, no update is triggered.
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Change-Id: I7c9bb165e6a64415affcd0b3331628092195fa0d
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 87 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/58158/9
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Change subject: soc/intel/common/cse: Reorganize firmware update checks for CSE Lite
......................................................................
soc/intel/common/cse: Reorganize firmware update checks for CSE Lite
`cse_fw_update()` is currently checking whether an update is required
by comparing versions once and then again comparing versions later in
`cse_is_downgrade_instance()` to determine if the update is an upgrade
or downgrade. Additionally, if CSE RW partition is corrupt (determined
based on `cse_is_rw_bp_sign_valid()`), `cse_is_downgrade_instance()`
ends up using the corrupted version information to determine if it is
a downgrade instance.
This change reorganizes the firmware update checks to return different
status values:
1. CSE_UPDATE_NOT_REQUIRED: No update required. Versions match.
2. CSE_UPDATE_UPGRADE: Update required and it is an upgrade.
3. CSE_UPDATE_DOWNGRADE: Update required and it is a
downgrade (requires data clear).
4. CSE_UPDATE_CORRUPTED: `cse_is_rw_bp_sign_valid()` failed and hence
requires data clear.
5. CSE_UPDATE_METADATA_ERROR: Unable to read CSE metadata from CBFS.
This change also prepares the file for follow up changes which
completely drop cse_rw_metadata structure.
BUG=b:184892226
Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 60 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/58157/5
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58099 )
Change subject: mb/adlrvp: Add hook function to return EC in RW status
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/intel/adlrvp/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/58099/comment/43d68b7d_b3a47cc1
PS6, Line 9: early_gpio_table
> We found out that we made a bug at the introducing get_ec_is_trusted() CL... […]
Ack
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