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Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
nb/intel/sandybridge: Populate meminfo when using MRC
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info needed,
so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
2 files changed, 77 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
nb/intel/sandybridge: Populate meminfo when using MRC
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info needed,
so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
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---
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
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I'd like you to reexamine a change. Please visit
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Change subject: nb/intel/sandybridge: Populate meminfo when using MRC
......................................................................
nb/intel/sandybridge: Populate meminfo when using MRC
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info needed,
so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8
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---
M src/northbridge/intel/sandybridge/raminit.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
2 files changed, 77 insertions(+), 0 deletions(-)
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58180 )
Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2:
Do we need to handle shutdown in depthcharge as well? If so, we may need SMI...sad
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )
Change subject: soc/tigerlake: Make IO decode / enable register configurable
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
> Tbh I wouldn't do that for each platform but keep using common code, since it handles mirroring alre […]
I just wanted to show that it can be much simpler. For instance, we could
call lpc_set_fixed_io_ranges() and lpc_enable_fixed_io_ranges() with static
values from platform code. It's all the `if` and `else` and (likely unneces-
sary) mainboard overrides that concern me.
If we ever can confirm that a single set (e.g. enable everything) works for
all boards, we could even move the calls to common code.
`gen_io_dec` is a separate topic.
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Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/wwan_power.asl:
https://review.coreboot.org/c/coreboot/+/58180/comment/72aec2ca_e87997bf
PS2, Line 5: Method (WWPD, 0)
> Sorry about my ACPI ignorance, but why does the method need to be renamed? So you can override it?
be called from mainboard MPTS
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Hello build bot (Jenkins), Weimin Wu,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
......................................................................
mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
---
M src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
M src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58196/2
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Zhi7 Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58196 )
Change subject: mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
......................................................................
mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
---
M src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
M src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58196/1
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
index 490e591..05ff304 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc
@@ -4,4 +4,4 @@
# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/sasukette/memory src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
index b02dcd7..cb4801e 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt
@@ -5,3 +5,4 @@
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
+K4U6E3S4AB-MGCL 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
index be1daed..476f0f5 100644
--- a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt
@@ -10,3 +10,4 @@
# Part Name
K4U6E3S4AA-MGCR
+K4U6E3S4AB-MGCL
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58170 )
Change subject: mb/siemens/mc_ehl2: Enable LPC ComB
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58170/comment/5d866e45_56e5bfd7
PS1, Line 10:
> Tested how?
Done
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58166 )
Change subject: mb/siemens/mc_ehl2: Enable SD-Card
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58166/comment/17610b37_a78d3b34
PS1, Line 9: must
> should
Done
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