coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload: Add mock architecture
by Jakub Czapiga (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Paul Menzel, Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57708 ) Change subject: libpayload: Add mock architecture ...................................................................... Patch Set 10: (2 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/57708/comment/bcf8ddc6_19fd57ff PS8, Line 125: MOCK > Sorry, I think you misunderstood me. […] Oh, yes. I misunderstood you. Sorry. Fixed :) File payloads/libpayload/arch/host/coreboot.c: https://review.coreboot.org/c/coreboot/+/57708/comment/7453e6dd_7332497e PS7, Line 7: int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) > Do we need to provide all these stubs when this is only meant to be linked into unit tests anyway? I […] I forgot to answer to this comment before. The only stubs left are: - (weak) libpayload_init_default_cbfs_media() - getpagesize() - Default value is the same for all architectures, so I think, it can be kept as is. -- To view, visit https://review.coreboot.org/c/coreboot/+/57708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Gerrit-Change-Number: 57708 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 10:14:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add mock architecture
by Jakub Czapiga (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Jakub Czapiga, Paul Menzel, Jan Dabros. Hello build bot (Jenkins), Julius Werner, Jan Dabros, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57708 to look at the new patch set (#10). Change subject: libpayload: Add mock architecture ...................................................................... libpayload: Add mock architecture Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/mock/Kconfig A payloads/libpayload/arch/mock/Makefile.inc A payloads/libpayload/arch/mock/head.c A payloads/libpayload/arch/mock/libpayload.ldscript A payloads/libpayload/arch/mock/mock_media.c A payloads/libpayload/arch/mock/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/include/mock/arch/barrier.h A payloads/libpayload/include/mock/arch/cache.h A payloads/libpayload/include/mock/arch/io.h A payloads/libpayload/include/mock/arch/types.h A payloads/libpayload/include/mock/arch/virtual.h M payloads/libpayload/sample/Makefile A payloads/libpayload/sample/arch_mock/Makefile A payloads/libpayload/sample/arch_mock/hello.c A payloads/libpayload/sample/arch_mock/hello_mocks.c 19 files changed, 329 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/57708/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/57708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Gerrit-Change-Number: 57708 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58180 ) Change subject: mb/google/brya: Clear SLP_S0_GATE_L on ACPI sleep entry ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/wwan_power.asl: https://review.coreboot.org/c/coreboot/+/58180/comment/103fff3b_b95fc979 PS2, Line 5: Method (WWPD, 0) Sorry about my ACPI ignorance, but why does the method need to be renamed? So you can override it? -- To view, visit https://review.coreboot.org/c/coreboot/+/58180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8 Gerrit-Change-Number: 58180 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:35:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58183 ) Change subject: mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58183/comment/437075ea_89b89c12 PS2, Line 9: commit 6260bf71 Please add the summary in brackets after it. -- To view, visit https://review.coreboot.org/c/coreboot/+/58183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Gerrit-Change-Number: 58183 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:33:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Update SPD for DDR4 devices
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Mario Scheithauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58111 ) Change subject: mb/siemens/mc_ehl2: Update SPD for DDR4 devices ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58111/comment/d1e3f8e4_f3b14040 PS3, Line 9: devices > I have added it. Thank you. Please do not forget to mark the comment as resolved. https://review.coreboot.org/c/coreboot/+/58111/comment/7eccf454_8fb805dd PS3, Line 11: > Following values were adjusted according to this board characteristic and with help of Serial Presen […] Could you please add that to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/58111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Gerrit-Change-Number: 58111 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:31:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58172 ) Change subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices ...................................................................... Patch Set 2: (1 comment) File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c: https://review.coreboot.org/c/coreboot/+/58172/comment/f5fb69ba_d8270b10 PS1, Line 14: SOC2 > SOC2 is a Siemens ASIC Thanks, could you please add that name to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/58172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Gerrit-Change-Number: 58172 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Matt DeVillier, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58188 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58188/comment/3db3587f_f38f4d0f PS1, Line 14: SandyBridge Nit: Sandy Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/58188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Gerrit-Change-Number: 58188 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:28:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Matt DeVillier, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58188 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58188/comment/6d9dd484_1e1ef545 PS1, Line 9: Populate a memory_info struct with PEI and SPD data, : in order to inject the CBMEM_INFO table necessary to : populate a type17 SMBIOS table. It’d be great, if you reflowed this for 72/75 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/58188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Gerrit-Change-Number: 58188 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:27:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Build chromeos.c in verstage
by Paul Menzel (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Hsuan-ting Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58193 ) Change subject: mb/google/guybrush: Build chromeos.c in verstage ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58193/comment/6432465a_ec157201 PS2, Line 9: build builds https://review.coreboot.org/c/coreboot/+/58193/comment/14def157_83885fd3 PS2, Line 9: Before attempting another commit 6260bf71, ensure that guybrush build Please add the summary in brackets: > commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main) -- To view, visit https://review.coreboot.org/c/coreboot/+/58193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Gerrit-Change-Number: 58193 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Fri, 08 Oct 2021 09:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Angel Pons (Code Review) 08 Oct '21

08 Oct '21

Attention is currently required from: Matt DeVillier, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58188 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: (11 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58188/comment/f5221363_e9df9dad PS1, Line 7: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM How about: nb/intel/sandybridge: Populate meminfo when using MRC https://review.coreboot.org/c/coreboot/+/58188/comment/b310668a_ce6ad86a PS1, Line 17: remove one space File src/northbridge/intel/sandybridge/raminit_mrc.c: https://review.coreboot.org/c/coreboot/+/58188/comment/700291aa_d2c32b52 PS1, Line 392: struct memory_info* mem_info; > "foo* bar" should be "foo *bar" Please fix. https://review.coreboot.org/c/coreboot/+/58188/comment/69c453c1_6dbf50f4 PS1, Line 406: / please add spaces around `/`. Or even better, use `DIV_ROUND_CLOSEST`. https://review.coreboot.org/c/coreboot/+/58188/comment/4673db9b_8008f4dd PS1, Line 406: ddr_frequency See raminit_shared.c on how to calculate this, the reference clock can be 133 MHz or 100 MHz. https://review.coreboot.org/c/coreboot/+/58188/comment/3970aadb_f87577e2 PS1, Line 411: // DIMM-A I'd much prefer C-style comments, for consistency with the rest of the file. https://review.coreboot.org/c/coreboot/+/58188/comment/22d503ce_19aa9415 PS1, Line 422: memcpy(dimm->serial, // bytes 122-125 in SPD > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/58188/comment/8cf843b5_4138dbf1 PS1, Line 428: dimm->mod_id = // bytes 117/118 (LSB/MSB) > line over 96 characters Please fix. https://review.coreboot.org/c/coreboot/+/58188/comment/001bfefa_82c4be01 PS1, Line 446: memcpy(dimm->serial, // bytes 122-125 in SPD > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/58188/comment/200b4332_5302c874 PS1, Line 452: dimm->mod_id = // bytes 117/118 (LSB/MSB) > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/58188/comment/1e9ec44a_3be28908 PS1, Line 452: dimm->mod_id = // bytes 117/118 (LSB/MSB) > line over 96 characters Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/58188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Gerrit-Change-Number: 58188 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 08 Oct 2021 08:56:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2021