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Change subject: soc/qualcomm: Commonize AOP firmware support
......................................................................
Removed Code-Review+2 by Shelley Chen <shchen(a)google.com>
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
......................................................................
mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus
as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC
only supports the standard speed.
TEST:
- Console Log shows no errors for RX6110SA during I2C2 init
- Finalize device for I2C 00:32 shows correct date and time
Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 23 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/58112/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/qualcomm/sc7280: Enable compression of SHRM
......................................................................
soc/qualcomm/sc7280: Enable compression of SHRM
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/shrm_load_reset.c
2 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58191/3
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Rajesh Patil has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50581 )
Change subject: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 76:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50581/comment/d1b65417_97ec43f7
PS71, Line 10: Load QUP FW in respective Serial Engines.
> Hi Paul, […]
Ack
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Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58191 )
Change subject: soc/qualcomm/sc7280: Enable compression of SHRM
......................................................................
soc/qualcomm/sc7280: Enable compression of SHRM
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on previous comments.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/shrm_load_reset.c
2 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58191/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58191 )
Change subject: soc/qualcomm/sc7280: Enable compression of SHRM
......................................................................
Patch Set 1:
(3 comments)
File src/soc/qualcomm/sc7280/shrm_load_reset.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130024):
https://review.coreboot.org/c/coreboot/+/58191/comment/765a4663_28d778a9
PS1, Line 18: /* map to cached region to force address to be 4 byte aligned */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130024):
https://review.coreboot.org/c/coreboot/+/58191/comment/6dcd4626_85383a09
PS1, Line 24: /* flush cached region */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130024):
https://review.coreboot.org/c/coreboot/+/58191/comment/2d29c74e_91dfa05b
PS1, Line 26: /* remap back to device memory */
code indent should use tabs where possible
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Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58191 )
Change subject: soc/qualcomm/sc7280: Enable compression of SHRM
......................................................................
soc/qualcomm/sc7280: Enable compression of SHRM
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/shrm_load_reset.c
2 files changed, 15 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/58191/1
diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc
index 364c987..442b2a3 100644
--- a/src/soc/qualcomm/sc7280/Makefile.inc
+++ b/src/soc/qualcomm/sc7280/Makefile.inc
@@ -107,7 +107,7 @@
SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
$(SHRM_CBFS)-file := $(SHRM_FILE)
$(SHRM_CBFS)-type := payload
-$(SHRM_CBFS)-compression := none
+$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(SHRM_CBFS)
endif
diff --git a/src/soc/qualcomm/sc7280/shrm_load_reset.c b/src/soc/qualcomm/sc7280/shrm_load_reset.c
index 78830a2..a853c73 100644
--- a/src/soc/qualcomm/sc7280/shrm_load_reset.c
+++ b/src/soc/qualcomm/sc7280/shrm_load_reset.c
@@ -1,22 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/cache.h>
+#include <arch/mmu.h>
#include <cbfs.h>
#include <console/console.h>
#include <soc/mmu.h>
+#include <soc/mmu_common.h>
#include <soc/shrm.h>
#include <soc/clock.h>
+#include <soc/symbols_common.h>
void shrm_fw_load_reset(void)
{
- bool shrm_fw_entry;
struct prog shrm_fw_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/shrm");
- shrm_fw_entry = selfload(&shrm_fw_prog);
- if (!shrm_fw_entry)
+ /* map to cached region to force address to be 4 byte aligned */
+ mmu_config_range((void *)_shrm, REGION_SIZE(shrm), CACHED_RAM);
+
+ if (!selfload(&shrm_fw_prog))
die("SOC image: SHRM load failed");
+ /* flush cached region */
+ dcache_clean_by_mva(_shrm, REGION_SIZE(shrm));
+ /* remap back to device memory */
+ mmu_config_range((void *)_shrm, REGION_SIZE(shrm), DEV_MEM);
+
clock_reset_shrm();
- printk(BIOS_DEBUG, "\nSOC:SHRM brought out of reset.\n");
+ printk(BIOS_DEBUG, "SOC:SHRM brought out of reset.\n");
}
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Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58183 )
Change subject: mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables
......................................................................
Patch Set 2: Code-Review+1
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58162 )
Change subject: mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58162/comment/be3b5397_50df582a
PS1, Line 11: Define SSFC bit 9-11 in coreboot for codec within ec.
> Please update this as "Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. […]
Done
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Hello build bot (Jenkins), Henry Sun, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VS
......................................................................
mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:198713670
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: Iaba136a836b89f42411474ae733380e345cce687
---
M src/mainboard/google/dedede/variants/galtic/overridetree.cb
1 file changed, 25 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/58162/2
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