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Change subject: soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig
......................................................................
Patch Set 16: Code-Review+2
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Change subject: mb/acer/aspire_vn7_572g: Add vboot support
......................................................................
Patch Set 2:
(1 comment)
This change is ready for review.
Patchset:
PS2:
Does vboot generally work for Intel PTT boards? Perhaps PTT is still unavailable in verstage, until it's initialised in romstage (FSP allocating the UMA for CSME).
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58017 )
Change subject: soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`
......................................................................
Patch Set 18: Code-Review+1
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57933 )
Change subject: soc/intel: transition full control over PM Timer from FSP to coreboot
......................................................................
Patch Set 33: Code-Review+1
(1 comment)
Patchset:
PS33:
The following is from FSP header
When FALSE, it disables PCH ACPI timer, and stops TCO timer.
@note: This will have significant power impact when it's enabled.
But we do have code that will stop tco timer in coreboot, only concern I have will be tco_configure() we have in common will cover tco counter 2 or not in newer silicon.
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Hello build bot (Jenkins), Patrick Georgi, Julius Werner, Arthur Heymans, Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51671
to look at the new patch set (#12).
Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
---
M src/arch/x86/bootblock.ld
M src/ec/hp/kbc1126/Kconfig
M src/ec/hp/kbc1126/Makefile.inc
A src/ec/hp/kbc1126/ecfw_ptr.c
A src/ec/hp/kbc1126/ecfw_ptr.h
5 files changed, 64 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/12
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Change subject: soc/intel/common/tcss: Optimize USB-C DP flow and code structure
......................................................................
soc/intel/common/tcss: Optimize USB-C DP flow and code structure
HPD event may not be ready when configuring TCSS mux for DP,
check if any DP device is connected and wait for HPD ready before
TCSS configuration. Remove unnecessary dependency on mainboard
functions, use generic interface which provides USB-C mux
operations.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for
Brya. Build coreboot and update your Brya. Boot Brya with USB-C
display connected, you should find `HPD ready after %lu ms` and
`Port C%zd is configured to DP mode!` in coreboot log. Display
should show screen in developer mode or recovery mode.
Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com>
Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50
---
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/tcss.c
2 files changed, 44 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/57139/25
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49767 )
Change subject: soc/qualcomm: Commonize AOP firmware support
......................................................................
Patch Set 77:
(2 comments)
File src/soc/qualcomm/common/aop_load_reset.c:
https://review.coreboot.org/c/coreboot/+/49767/comment/fc852143_9114362f
PS77, Line 16: aop_fw_entry = selfload(&aop_fw_prog);
: if (!aop_fw_entry)
Can you fix this per feedback in CB:49392? Basically just have "if (!selfload(&aop_fw_prog))" ?
https://review.coreboot.org/c/coreboot/+/49767/comment/9e95093c_7c045e43
PS77, Line 22: \n
Please remove this newline.
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