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Change subject: util/cse_serger: Add a new tool for stitching CSE components
......................................................................
util/cse_serger: Add a new tool for stitching CSE components
This change adds a new tool `cse_serger` which can be used to print,
dump and stitch together different components for the CSE region.
BUG=b:189177186
Change-Id: I90dd809b47fd16afdc80e66431312721082496aa
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M Makefile.inc
M util/cbfstool/Makefile
M util/cbfstool/Makefile.inc
A util/cbfstool/bpdt_formats/Makefile.inc
A util/cbfstool/bpdt_formats/bpdt_1_6.c
A util/cbfstool/bpdt_formats/bpdt_1_7.c
A util/cbfstool/bpdt_formats/subpart_entry_1.c
A util/cbfstool/bpdt_formats/subpart_hdr_1.c
A util/cbfstool/bpdt_formats/subpart_hdr_2.c
A util/cbfstool/cse_serger.c
A util/cbfstool/cse_serger.h
11 files changed, 1,963 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55503/25
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Change subject: util/cse_serger: Add command `create-cse-region`
......................................................................
Patch Set 3:
(2 comments)
File util/cbfstool/cse_serger.c:
https://review.coreboot.org/c/coreboot/+/58215/comment/1d84d2b2_ec3a6fe6
PS3, Line 720: if (i == 0) {
> > braces {} are not necessary for any arm of this statement […]
It is a little weird. If I remove the braces {}, then I also have to drop the ';' at the end because of the way ERROR is defined. I have done that in latest patchset. Let me know what you think.
https://review.coreboot.org/c/coreboot/+/58215/comment/827d0646_71a7bbda
PS3, Line 733: memcpy(buffer_get(&wbuff), buffer_get(&rbuff), buffer_size(&rbuff));
> should the size of wbuff be verified?
Done
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Change subject: soc/intel: transition full control over PM Timer from FSP to coreboot
......................................................................
Patch Set 33:
(1 comment)
Patchset:
PS33:
> The following is from FSP header
>
> When FALSE, it disables PCH ACPI timer, and stops TCO timer.
> @note: This will have significant power impact when it's enabled.
Stopping the TCO timer is not done via the TCO registers but a result of stopping the PM timer. This is done in coreboot now (see CB:57932).
>
> But we do have code that will stop tco timer in coreboot, only concern I have will be tco_configure() we have in common will cover tco counter 2 or not in newer silicon.
You probably mean `tco_timer_disable`? Since the timer is already stopped by disabling the PM timer, this only sets that specific disable bit for the TCO but won't have any real impact.
Regarding TCO ctr 2, I would expect it to stop, too, when the PM timer is disabled.
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Change subject: soc/intel/alderlake: Enable support for CSE stitching
......................................................................
Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58125/comment/b8f02005_b2a1541a
PS17, Line 8:
> Can you add some context here about the required components in each BP?
Done
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Hello build bot (Jenkins), Henry Sun, Aseda Aboagye, Shou-Chieh Hsu, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/corori: Configure I2C times for Touchpad
......................................................................
mb/google/dedede/var/corori: Configure I2C times for Touchpad
Configure I2C high / low time in the device tree to ensure Touchpad
I2C CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
Touch Pad CLK: 389.2 KHz
BUG=b:202787528
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Change-Id: I0f9d062fc611de0062a39849aee1174268391682
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/corori/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58238/2
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Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58238 )
Change subject: mb/google/dedede/var/corori: Configure I2C times for Touchpad
......................................................................
mb/google/dedede/var/corori: Configure I2C times for Touchpad
Configure I2C high / low time in the device tree to ensure Touchpad
I2C CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
Touch Pad CLK: 389.2 KHz
BUG=b:202787528
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Change-Id: I0f9d062fc611de0062a39849aee1174268391682
---
M src/mainboard/google/dedede/variants/corori/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58238/1
diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb
index d322000..f7899a6 100644
--- a/src/mainboard/google/dedede/variants/corori/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb
@@ -39,6 +39,8 @@
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 255,
+ .fall_time_ns = 14,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
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Change subject: cbfstool: Add helper function `buffer_from_file_aligned_size`
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
> not sure if i'm misinterpreting what this is supposed to do or what it does, but shouldn't this be g […]
The change is ensuring that the buffer size that is allocated for reading the file is aligned to a multiple of the align attribute. I see your point about the usage of terms "alignment" and "granularity". Does this change make it somewhat clear:
```
int buffer_from_file_roundup_size(struct buffer *buffer, const char *filename, size_t size_granularity)
```
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Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 27:
(2 comments)
Patchset:
PS27:
> But the flag set to 1 have no consequence even in case of mismatch right?
Did I miss a case? Where do you see that mismatch?
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/57934/comment/020e5273_f84f5e48
PS26, Line 155: if (CONFIG(USE_PM_ACPI_TIMER) || !CONFIG(PM_ACPI_TIMER_OPTIONAL))
> yup, right. […]
Done
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Change subject: soc/intel/common/cse: Reorganize firmware update checks for CSE Lite
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/58157/comment/0b47e4bf_7805a43e
PS5, Line 651: (status == CSE_UPDATE_CORRUPTED
> If the last update is downgrade case, then coreboot first clears the runtime data and triggers downg […]
I was thinking of this case:
1. CSE region getting corrupted for some reason (it could be an update being applied or some other reason)
2. Suppose user recovers their device with an OS image which has an older firmware i.e. firmware older than what was being flashed and what was present on the device before. This would be a case of downgrade via recovery. In that case, we might not have erased data already.
Given that erasing data doesn't have any other side effects and it should be an extremely rare case, I will keep this check as is.
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