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Hello build bot (Jenkins), Patrick Georgi, Julius Werner, Arthur Heymans, Iru Cai,
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
......................................................................
arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build time
According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
---
M src/arch/x86/bootblock.ld
M src/ec/hp/kbc1126/Kconfig
M src/ec/hp/kbc1126/Makefile.inc
A src/ec/hp/kbc1126/ecfw_ptr.c
A src/ec/hp/kbc1126/ecfw_ptr.h
5 files changed, 60 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/11
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Bhanu Prakash Maiya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58161 )
Change subject: mb/google/guybrush/var/nipperkin: update fw_config field
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Assignment matches this https://docs.google.com/spreadsheets/d/11cu76Z_rd1sXFubT-fb73olB-aexrLgACv5…
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Change subject: mb/google/guybrush/var/nipperkin: update fw_config field
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
hi reviwers,
could you please review this one? thank you!
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Change subject: mb/google/brya/variants/brask: Init overridetree
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58165/comment/c555985a_36451561
PS2, Line 11: bray0
> brya0
Ack
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Change subject: mb/google/brya/variants/brask: Init overridetree
......................................................................
mb/google/brya/variants/brask: Init overridetree
Init overridetree based on the schematics.
Refer to brya0/overridetree.cb to update the settings of the devices
including DPTF, WIFI, NAU8825 and etc.
Refer to kano/overridetree.cb to update the SSD settings (pcie4_0).
TODO: DPTF and USB positions will be further updated later.
BUG=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 286 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/58165/3
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Change subject: soc/amd/common/block/include/psp_efs: use unsigned type for bitfield
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/psp_efs.h:
https://review.coreboot.org/c/coreboot/+/58224/comment/363ecc9e_ee6cb1ca
PS1, Line 29: uint32_t
> Why not use the generic type `unsigned int`?
mostly for consistency with the rest of the file, but also to clarify that the bits will be packed into a 32 bit memory location. since this isn't an 8 or 16 bit architecture where an unsigned int might end up being only 16 bits, unsigned int would also work and i'd expect it to result in an identical binary in this case, but i still prefer using an uint32_t here
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Change subject: soc/amd/common/block/lpc: Refactor ESPI Setup
......................................................................
Patch Set 2: -Code-Review
(1 comment)
File src/soc/amd/common/block/lpc/lpc_util.c:
https://review.coreboot.org/c/coreboot/+/58114/comment/6f3186db_0bc191b3
PS2, Line 365: configure_espi
> I think I would rather keep eSPI code out of lpc_util.c. […]
yes, moving this function to espi_util.c and calling it from fch_pre_init would be a good idea
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Change subject: soc/intel/alderlake: fix NULL pointer dereference
......................................................................
soc/intel/alderlake: fix NULL pointer dereference
microcode_file could be NULL and passed to get_microcode_size,
this was detected by klocwork scan.
Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com>
Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 7 insertions(+), 5 deletions(-)
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Change subject: soc/intel/alderlake: fix NULL pointer dereference
......................................................................
soc/intel/alderlake: fix NULL pointer dereference
microcode_file could be NULL and passed to get_microcode_size,
this was detcted by klocwork scan.
Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com>
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