coreboot-gerrit October 2021

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Change in coreboot[master]: soc/intel/alderlake: fix NULL pointer derefrence
by Selma Bensaid (Code Review) 12 Oct '21

12 Oct '21

Selma Bensaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58233 ) Change subject: soc/intel/alderlake: fix NULL pointer derefrence ...................................................................... soc/intel/alderlake: fix NULL pointer derefrence microcode_file could be NULL and passed to get_microcode_size, this was detcted by klocwork scan. Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/58233/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 333957f..f9569f9 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -346,12 +346,14 @@ /* Locate microcode and pass to FSP-S for 2nd microcode loading */ microcode_file = intel_microcode_find(); - microcode_len = get_microcode_size(microcode_file); - if ((microcode_file != NULL) && (microcode_len != 0)) { - /* Update CPU Microcode patch base address/size */ - s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; - s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + if (microcode_file != NULL) { + microcode_len = get_microcode_size(microcode_file); + if (microcode_len != 0) { + /* Update CPU Microcode patch base address/size */ + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; + s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + } } /* Use coreboot MP PPI services if Kconfig is enabled */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736 Gerrit-Change-Number: 58233 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Paul Menzel, Sridhar Siricilla, Bernardo Perez Priego. Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Sridhar Siricilla, Bernardo Perez Priego, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58101 to look at the new patch set (#7). Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... lib/spd_bin: Fix for LDDR5 1. Add LDDR5 for the param 2. Fix SPD name for LDDR5 This addresses the warning message: Defaulting to using DDR4 params. Please add dram_type check for 19 to use_ddr4_params Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M src/lib/spd_bin.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd_bin: Fix for LDDR5
by Cliff Huang (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Paul Menzel, Sridhar Siricilla, Bernardo Perez Priego. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58101 ) Change subject: lib/spd_bin: Fix for LDDR5 ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58101/comment/3d52b705_ed7d4b9f PS5, Line 9: Added LDDR5 for the param : Fixed SPD name for LDDR5 > List would be: […] got it now. done. https://review.coreboot.org/c/coreboot/+/58101/comment/6710acfa_59bb8ded PS5, Line 11: with this change, we won't get this warning message: > I do not see a blank line. I missed this one. Thanks. done. -- To view, visit https://review.coreboot.org/c/coreboot/+/58101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 Gerrit-Change-Number: 58101 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Mon, 11 Oct 2021 22:31:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errors
by Raul Rangel (Code Review) 12 Oct '21

12 Oct '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58232 ) Change subject: arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errors ...................................................................... arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errors There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc --- M src/arch/x86/c_start.S M src/cpu/x86/cpu_info.S.inc 2 files changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/58232/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9e718fc..c3fdfd9 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -90,7 +90,8 @@ */ set_segment_descriptor_base $per_cpu_segment_descriptors, %esp - mov per_cpu_segment_selector, %eax + mov $per_cpu_segment_selector, %eax + movl (%eax), %eax mov %eax, %gs #endif diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index 9ffdd84..6dca920 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -1,14 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Pushes a 32-bit register onto the stack. + * + * There are two possible code sections where this code can be included: + * .code32 and .code64 + * + * Doing a `push %eax` while in a .code64 section will result in a compiler + * error. This macro manually pushes the 32-bit register onto the stack so we + * can share the code between 32 and 64 bit builds. + */ +.macro pushr reg:req +#if ENV_X86_64 + movl $0, -4(%esp) + movl \reg, -8(%esp) + sub $8, %esp +#else + push \reg +#endif +.endm + /* Push struct cpu_info */ .macro push_cpu_info index=$0 - push \index /* index */ - push $0 /* *cpu */ + pushr \index /* index (size_t) */ + pushr $0 /* *cpu */ .endm /* Push struct per_cpu_segment_data */ .macro push_per_cpu_segment_data cpu_info_pointer=%esp - push \cpu_info_pointer /* *cpu_info */ + pushr \cpu_info_pointer /* *cpu_info */ .endm /* -- To view, visit https://review.coreboot.org/c/coreboot/+/58232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Gerrit-Change-Number: 58232 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP
by Raul Rangel (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58146 to look at the new patch set (#2). Change subject: cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP ...................................................................... cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb --- M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 3 files changed, 7 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/58146/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Gerrit-Change-Number: 58146 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/wyvern: use SaGv_FixedHigh
by Matt DeVillier (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58230 ) Change subject: mb/google/wyvern: use SaGv_FixedHigh ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58230/comment/c96d4953_3bfee805 PS1, Line 10: always > remove Done https://review.coreboot.org/c/coreboot/+/58230/comment/5c6ed168_10420454 PS1, Line 10: used > always use Done File src/mainboard/google/hatch/variants/wyvern/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58230/comment/26c64fb4_796ff8a0 PS1, Line 23: # Enable System Agent fixed frequency > Just use the commit message body as-is? (well, with my suggestions applied) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Gerrit-Change-Number: 58230 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Oct 2021 22:20:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/fizz: use SaGv_FixedHigh
by Matt DeVillier (Code Review) 12 Oct '21

12 Oct '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58231 ) Change subject: mb/google/fizz: use SaGv_FixedHigh ...................................................................... mb/google/fizz: use SaGv_FixedHigh No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/fizz/variants/fizz/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58231/1 diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb index 3394bdf..b4eea38 100644 --- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -3,6 +3,10 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7" + # No need for dynamic config (and the additional RAM training time) + # on a Chromebox; always use high power/high performance mode + register "SaGv" = "SaGv_FixedHigh" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/58231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e Gerrit-Change-Number: 58231 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/wyvern: use SaGv_FixedHigh
by Matt DeVillier (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak. Hello Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58230 to look at the new patch set (#2). Change subject: mb/google/wyvern: use SaGv_FixedHigh ...................................................................... mb/google/wyvern: use SaGv_FixedHigh No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/58230/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Gerrit-Change-Number: 58230 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Tim Wawrzynczak (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Evgeny Zinoviev, Patrick Rudolph, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 77: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 77 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Oct 2021 22:05:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Angel Pons (Code Review) 12 Oct '21

12 Oct '21

Attention is currently required from: Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Evgeny Zinoviev, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 77: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/2f07b04e_3d2adf69 PS77, Line 1009: do_global_reset(); > me_reset_with_count only gets called when some sort of option table is used and the me_state option […] I think both options are required to be present to properly handle this, not sure though. -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 77 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Oct 2021 21:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit October 2021