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Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 27:
(1 comment)
Patchset:
PS27:
But the flag set to 1 have no consequence even in case of mismatch right?
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Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57951 )
Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57951/comment/15d5e328_e585b203
PS2, Line 11: We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using intel SoC
> Please add a dot/period to the end of sentences.
Done
https://review.coreboot.org/c/coreboot/+/57951/comment/adb30a89_c4fd3a27
PS2, Line 11: intel
> Intel
Done
https://review.coreboot.org/c/coreboot/+/57951/comment/1a2514b6_abe4f6ce
PS2, Line 11: intel
> Intel
Done
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Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57951
to look at the new patch set (#3).
Change subject: Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC.
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
---
M src/include/bootmode.h
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/mistral/chromeos.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/zork/chromeos.c
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/skylake/Makefile.inc
51 files changed, 0 insertions(+), 323 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57951/3
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Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> In our systems we disable speed step in coreboot all the time. […]
This is just our view. In general I agree that it makes sense to enable such features per default and I think that the vast majority of the use cases with coreboot will benefit from this.
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Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57932 )
Change subject: soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
......................................................................
Patch Set 33: Code-Review+1
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Change subject: [RFC] soc/intel/{adl,ehl,icl,jsl,tgl}: Invert `eist_enabled`
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
> Werner, do you have an OS that would do something unwanted? The OS always has […]
In our systems we disable speed step in coreboot all the time. This is done in order to avoid CPU frequency switching in a realtime environment. And since modern kernels are able to handle all this "fancy" features and most likely enable things like this per default we chose the strategy do define the feature set in this regard in firmware. So regardless of the logic here (either enable or disable per default): in the end we will make sure for the Siemens mainboards that EIST is disabled. And since this is an option in devicetree we can do that easily.
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