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Change subject: mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd
......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/google/brya/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/58126/comment/d8705b68_6059c3f7
PS19, Line 6: 1588
> did this change?
Nm you just carved a few K out from here.
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Change subject: soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Ethan, +Cliff Huang told me that the 2nd argument was not required for this command, see https://review.coreboot.org/c/coreboot/+/56005/1..9/src/soc/intel/common/bl…
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58307
to look at the new patch set (#3).
Change subject: soc/amd/common/block/i2c: implement proper read_resource
......................................................................
soc/amd/common/block/i2c: implement proper read_resource
Before this patch the reservation of the MMIO region of the I2C
controllers was done in the LPC controller PCI device despite the I2C
controllers already being devices in the devicetree. This patch
implements this functionality as read_resources function of the I2C
device instead. This will only reserve the memory when the I2C devices
are enabled in devicetree which is a change from the previous behavior.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0
---
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/common/block/i2c/i2c.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
5 files changed, 6 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/58307/3
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58306
to look at the new patch set (#3).
Change subject: soc/amd/cezanne,picasso/uart: implement read_resource
......................................................................
soc/amd/cezanne,picasso/uart: implement read_resource
Implement the read_resources function for the UART devices so that the
resource allocator knows about their fixed MMIO resources when enabled.
TEST=UART still works on Mandolin.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae
---
M src/soc/amd/cezanne/uart.c
M src/soc/amd/picasso/uart.c
2 files changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/58306/3
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Change subject: util/cse_serger: Add a new tool for stitching CSE components
......................................................................
Patch Set 26:
(2 comments)
File util/cbfstool/cse_serger.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130426):
https://review.coreboot.org/c/coreboot/+/55503/comment/c5b70c40_71c3e0a7
PS26, Line 272: ERROR("Part(%d) exceeds file size. Part offset=0x%x, Part size = 0x%x, File size = 0x%zx\n",
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130426):
https://review.coreboot.org/c/coreboot/+/55503/comment/552e592e_1e8894dc
PS26, Line 920: if (c < LONGOPT_START) {
braces {} are not necessary for any arm of this statement
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Change subject: arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58199/comment/df3288f8_c3949b25
PS2, Line 12: romstage
I think romstage currently can support COOP_MULTITASKING.
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Hello Shelley Chen, Furquan Shaikh, Kyösti Mälkki,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/58331
to review the following change.
Change subject: [RFC] pci_mmio_cfg: Move guard around pci_s_* functions to x86
......................................................................
[RFC] pci_mmio_cfg: Move guard around pci_s_* functions to x86
There is no platform in our tree that requires the PCI MMIO ops but
doesn't want the pci_s_* definitions. The only case where we include
the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to
use MMIO is on older x86 platforms, so move the guard there.
Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/arch/x86/include/arch/pci_ops.h
M src/include/device/pci_mmio_cfg.h
2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58331/1
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index 317e597..abbd35c 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -4,6 +4,8 @@
#define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h>
+#if CONFIG(MMCONF_SUPPORT)
#include <device/pci_mmio_cfg.h>
+#endif
#endif /* ARCH_I386_PCI_OPS_H */
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h
index 8798405..e873abc 100644
--- a/src/include/device/pci_mmio_cfg.h
+++ b/src/include/device/pci_mmio_cfg.h
@@ -105,6 +105,8 @@
#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!"
#endif
+#endif
+
/* Avoid name collisions as different stages have different signature
* for these functions. The _s_ stands for simple, fundamental IO or
* MMIO variant.
@@ -146,6 +148,4 @@
pci_mmio_write_config32(dev, reg, value);
}
-#endif
-
#endif /* _PCI_MMIO_CFG_H */
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