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Change subject: [trivial]amdfwtool: Fix some blanks
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58320/comment/0bca60a2_4032d69e
PS1, Line 7: [trivial]
Nit: We are not using these tags. Please remove.
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Change subject: amdfwtool: Add more detailed description and note in comment.
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55602/comment/bd947e2e_09ebdec0
PS7, Line 7: amdfwtool: Add more detailed description and note in comment.
Nit: Please remove the dot/period at the end of the commit message summary.
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Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
There was a big issue with per-test config. It was missing include guards, so including it twice could make gcc report errors e.g. macro redefined. Fixed. (Also should be fixed in the coreboot/tests/Makefile.inc TODO)
+ small fixes & prefix in libpayload junit files to easily differentiate them.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58327 )
Change subject: libpayload/tests: Add libcbfs/cbfs_core-test test case
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/tests/libcbfs/cbfs_core-test.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130421):
https://review.coreboot.org/c/coreboot/+/58327/comment/25f66322_1a3d68ea
PS1, Line 210: lib_sysinfo.cbfs_size = 1 * KiB - 64; /* Does not matter. Has to be positive por this test */
line over 96 characters
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Hello build bot (Jenkins), Nico Huber, Paul Fagerburg, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58242
to look at the new patch set (#6).
Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.
Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/configs/config.unit-tests
A payloads/libpayload/tests/Makefile.inc
A payloads/libpayload/tests/drivers/Makefile.inc
A payloads/libpayload/tests/drivers/speaker-test.c
A payloads/libpayload/tests/include/mocks/x86_io.h
A payloads/libpayload/tests/include/tests/test.h
M util/testing/Makefile.inc
9 files changed, 549 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/58242/6
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Change subject: [WIP] soc/amd/common/block/i2c: implement proper read_resource
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
adding Karthik, since he was mentioned in the comment in lpc.c in amd/common
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58275 )
Change subject: mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry
......................................................................
mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/guybrush/mainboard.c
1 file changed, 28 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 3626157..39ef2a0 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -13,11 +13,13 @@
#include <vendorcode/google/chromeos/chromeos.h>
#define BACKLIGHT_GPIO GPIO_129
+#define WWAN_AUX_RST_GPIO GPIO_18
#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS"
#define METHOD_MAINBOARD_INI "\\_SB.MINI"
#define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
#define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
+#define METHOD_MAINBOARD_S0X "\\_SB.MS0X"
/*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -151,6 +153,31 @@
acpigen_pop_len();
}
+static void mainboard_assert_wwan_aux_reset(void)
+{
+ if (variant_has_pcie_wwan())
+ acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO);
+}
+
+static void mainboard_deassert_wwan_aux_reset(void)
+{
+ if (variant_has_pcie_wwan())
+ acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO);
+}
+
+static void mainboard_write_ms0x(void)
+{
+ acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1);
+ /* S0ix Entry */
+ acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+ mainboard_assert_wwan_aux_reset();
+ /* S0ix Exit */
+ acpigen_write_else();
+ mainboard_deassert_wwan_aux_reset();
+ acpigen_pop_len();
+ acpigen_pop_len();
+}
+
static void mainboard_fill_ssdt(const struct device *dev)
{
mainboard_write_blken();
@@ -158,6 +185,7 @@
mainboard_write_mini();
mainboard_write_mpts();
mainboard_write_mwak();
+ mainboard_write_ms0x();
}
static void mainboard_enable(struct device *dev)
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