coreboot-gerrit October 2021

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Change in coreboot[master]: soc/amd: make configure_espi_with_mb_hook call conditional
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58339 ) Change subject: soc/amd: make configure_espi_with_mb_hook call conditional ...................................................................... soc/amd: make configure_espi_with_mb_hook call conditional If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/picasso/early_fch.c 3 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58339/1 diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index f97f57c..f06d576 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -40,8 +40,12 @@ enable_acpimmio_decode_pm04(); /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); - /* Setup eSPI to enable port80 routing. */ - configure_espi_with_mb_hook(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); + fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 0f8066b..e12b1b8 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -134,12 +134,8 @@ /* Setup eSPI with any mainboard specific initialization. */ static inline void configure_espi_with_mb_hook(void) { - /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform - port80h routing as early as possible. */ - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - mb_set_up_early_espi(); - espi_setup(); - } + mb_set_up_early_espi(); + espi_setup(); } #endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 83b4ae4..2a1b5c9 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -47,8 +47,11 @@ enable_acpimmio_decode_pm04(); /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); - /* Setup eSPI to enable port80 routing. */ - configure_espi_with_mb_hook(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Gerrit-Change-Number: 58339 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/include/espi: rename configure_espi
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58338 ) Change subject: soc/amd/common/include/espi: rename configure_espi ...................................................................... soc/amd/common/include/espi: rename configure_espi Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/picasso/early_fch.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58338/1 diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 69458b6..f97f57c 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -41,7 +41,7 @@ /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); /* Setup eSPI to enable port80 routing. */ - configure_espi(); + configure_espi_with_mb_hook(); fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 7e49ea0..0f8066b 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -132,7 +132,7 @@ void mb_set_up_early_espi(void); /* Setup eSPI with any mainboard specific initialization. */ -static inline void configure_espi(void) +static inline void configure_espi_with_mb_hook(void) { /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform port80h routing as early as possible. */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 8771e38..83b4ae4 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -48,7 +48,7 @@ /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); /* Setup eSPI to enable port80 routing. */ - configure_espi(); + configure_espi_with_mb_hook(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); -- To view, visit https://review.coreboot.org/c/coreboot/+/58338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Gerrit-Change-Number: 58338 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google: Add OEM product names for various boards
by Matt DeVillier (Code Review) 15 Oct '21

15 Oct '21

Attention is currently required from: Martin Roth, Tim Wawrzynczak, Nick Vaccaro. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57392 ) Change subject: mb/google: Add OEM product names for various boards ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/dedede/Kconfig.name: https://review.coreboot.org/c/coreboot/+/57392/comment/c1159213_16eed367 PS5, Line 16: Drawcia (HP Chromebook x360 11 G4 EE)" > drawcia also covers drawlat and drawman, so this is also […] Done https://review.coreboot.org/c/coreboot/+/57392/comment/903fd8e8_3c612982 PS5, Line 99: bool "-> Storo" > ASUS Chromebook CR1100 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Gerrit-Change-Number: 57392 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Oct 2021 19:54:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Add HAVE_CBFS_CACHE Kconfig
by Raul Rangel (Code Review) 15 Oct '21

15 Oct '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56577 ) Change subject: lib/cbfs: Add HAVE_CBFS_CACHE Kconfig ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > So the problem is that the availability of the cache may be stage-dependent, and you can't easily mo […] I think this makes sense. I'm running into an issue where REGION_SIZE doesn't work correctly for optional regions in ramstage. romstage works as expected. ``` coreboot-4.14-2248-ga3f9b16e0549-dirty Thu Oct 14 16:53:49 UTC 2021 romstage starting (log level: 8)... GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000 Boot Count incremented to 639 FMAP: area FW_MAIN_A found @ 12000 (3137280 bytes) CBFS: Found 'fspm.bin' @0x1906c0 size 0x16328 in mcache @0x02016a38 RX: _cbfs_alloc: cbfs_cache->size: 0 ``` Once we hit ramstage though, we get garbage. I'm not sure if this is caused by the rmodule loader. ``` coreboot-4.14-2248-ga3f9b16e0549-dirty Thu Oct 14 16:53:49 UTC 2021 ramstage starting (log level: 8)... RX: main: cbfs_cache->size: 3111460864 ``` Loading the ramstage ELF in gdb shows the correct values: ``` (gdb) print cbfs_cache $1 = {buf = 0x0, size = 0, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} ``` So I'm not quite sure why we are getting garbage. -- To view, visit https://review.coreboot.org/c/coreboot/+/56577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74434ef9250ff059e7587147b1456aeabbee33aa Gerrit-Change-Number: 56577 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 14 Oct 2021 19:54:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/scout: set correct i2c configuration
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58236 ) Change subject: mb/google/hatch/var/scout: set correct i2c configuration ...................................................................... mb/google/hatch/var/scout: set correct i2c configuration Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous I2C configuration copied from Puff. BUG=b:202195805 TEST=Boot scout, verify no more errors due to missing I2C devices Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1 Signed-off-by: Matt Ziegelbaum <ziegs(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/hatch/variants/scout/gpio.c M src/mainboard/google/hatch/variants/scout/overridetree.cb 2 files changed, 29 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index c916d55..5491efe 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -51,16 +51,14 @@ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* - * TODO(b/187094460): Re-enable touch screen I2C after resolving USB - * conflict - */ - + /* C16 : PCH_I2C_RFU_SDA (NC) */ + PAD_NC(GPP_C16, NONE), + /* C17 : PCH_I2C_RFU_SCL (NC) */ + PAD_NC(GPP_C17, NONE), /* C18 : PCH_I2C_USI_SDA */ - PAD_NC(GPP_C18, NONE), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : PCH_I2C_USI_SDL */ - PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* D13 : SMBUS_ISP_SCALAR */ PAD_CFG_GPO(GPP_D13, 0, DEEP), @@ -112,14 +110,22 @@ /* F22 : EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* H4: PCH_I2C_PCON_SDA */ + /* H4: PCH_I2C_SCALER_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ + /* H5: PCH_I2C_SCALER_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* H6 : PCH_I2C_TPU_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : PCH_I2C_TPU_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : NC */ + PAD_NC(GPP_H11, NONE), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index 8b7d558..9b33621 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -4,11 +4,11 @@ register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, @@ -150,20 +150,19 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | + #| I2C1 | USI (Touch screen) | + #| I2C2 | SCALER | + #| I2C3 | TPU | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { + .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, + .rise_time_ns = 60, + .fall_time_ns = 60, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -175,11 +174,6 @@ .rise_time_ns = 60, .fall_time_ns = 60, }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, }" # PCIe root port 7 for LAN @@ -380,24 +374,11 @@ device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2, PCON PS175. - device pci 15.3 off end # I2C #3, Realtek RTD2142. + device pci 15.1 on end # I2C #1, USI (Touch screen) + device pci 15.2 on end # I2C #2, SCALER + device pci 15.3 on end # I2C #3, TPU device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 + device pci 19.0 off end # I2C #4 device pci 1a.0 on end # eMMC device pci 1c.6 on # PCI Root Port 7 (LAN) chip drivers/net # RTL8111H Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/58236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1 Gerrit-Change-Number: 58236 Gerrit-PatchSet: 4 Gerrit-Owner: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joe Tessler <jrt(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58282 ) Change subject: mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3 ...................................................................... mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3 S3 is not currently functional on Guybrush. Remove support from ACPI. BUG=b:202401767 b:181766974 TEST=Boot Guybrush Confirm 'deep' is not in /sys/power/mem_sleep Confirm S0ix suspend/resume still works BRANCH=None Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 489c045..c97c06d 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -29,7 +29,6 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION - select HAVE_ACPI_RESUME select HAVE_EM100_SUPPORT select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Gerrit-Change-Number: 58282 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/cpu_info.S: Remove ebx save/restore
by Karthik Ramasubramanian (Code Review) 15 Oct '21

15 Oct '21

Attention is currently required from: Raul Rangel, Julius Werner. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58205 ) Change subject: cpu/x86/cpu_info.S: Remove ebx save/restore ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 Gerrit-Change-Number: 58205 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Oct 2021 19:40:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_fch: use I2C[ABCD]_BASE_ADDRESS defines
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Attention is currently required from: Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58337 ) Change subject: soc/amd/stoneyridge/acpi/sb_fch: use I2C[ABCD]_BASE_ADDRESS defines ...................................................................... soc/amd/stoneyridge/acpi/sb_fch: use I2C[ABCD]_BASE_ADDRESS defines Now that the I2C[ABCD]_BASE_ADDRESS defines aren't macros that calculate the MMIO addresses any more, those defines can also be used in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7de2f83dc2f8061d8f1735caf10314bcddb2d3fa --- M src/soc/amd/stoneyridge/acpi/sb_fch.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/58337/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index bbb5235..b389c66 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -74,7 +74,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) + Memory32Fixed (ReadWrite, I2CA_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -90,7 +90,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) + Memory32Fixed (ReadWrite, I2CB_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -104,7 +104,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + Memory32Fixed (ReadWrite, I2CC_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -119,7 +119,7 @@ Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + Memory32Fixed(ReadWrite, I2CD_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/58337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7de2f83dc2f8061d8f1735caf10314bcddb2d3fa Gerrit-Change-Number: 58337 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/include/iomap: drop I2C_BUS_ADDRESS(x) macro
by Felix Held (Code Review) 15 Oct '21

15 Oct '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58336 ) Change subject: soc/amd/stoneyridge/include/iomap: drop I2C_BUS_ADDRESS(x) macro ...................................................................... soc/amd/stoneyridge/include/iomap: drop I2C_BUS_ADDRESS(x) macro The I2C_BUS_ADDRESS(x) macro isn't used to iterate over the I2C controller base addresses, so drop this and use the fixed MMIO address for the I2C[ABCD]_BASE_ADDRESS defines instead which also allows using those defines in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idd7484a0322dc5167cbb7fdcd9a2583f0dbed50e --- M src/soc/amd/stoneyridge/include/soc/iomap.h 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/58336/1 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index c8cee23..3d01938 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -11,13 +11,10 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) +#define I2CA_BASE_ADDRESS 0xfedc2000 +#define I2CB_BASE_ADDRESS 0xfedc3000 +#define I2CC_BASE_ADDRESS 0xfedc4000 +#define I2CD_BASE_ADDRESS 0xfedc5000 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/58336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd7484a0322dc5167cbb7fdcd9a2583f0dbed50e Gerrit-Change-Number: 58336 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by Julien Viard de Galbert (Code Review) 15 Oct '21

15 Oct '21

Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25429 ) Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... Patch Set 10: (2 comments) Patchset: PS10: > Applying this change to soc/intel/skylake makes one duplicate vanish but four other entries get repl […] Yes this version _really_ respect PSS_MAX_ENTRIES which is 8. So there should not be 10 values in there ;) PS10: I hope this answers your question. -- To view, visit https://review.coreboot.org/c/coreboot/+/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 14 Oct 2021 19:13:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit October 2021