Sean Rhodes has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58343 )
Change subject: ec/starlabs: Add standardised ITE EC support
......................................................................
ec/starlabs: Add standardised ITE EC support
Add EC support that supports different Q Events and EC memory.
Tested with:
* IT5570E
* IT8987E
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
---
A src/ec/starlabs/merlin/Kconfig
A src/ec/starlabs/merlin/Makefile.inc
A src/ec/starlabs/merlin/acpi/ac.asl
A src/ec/starlabs/merlin/acpi/battery.asl
A src/ec/starlabs/merlin/acpi/cmos.asl
A src/ec/starlabs/merlin/acpi/ec.asl
A src/ec/starlabs/merlin/acpi/hid.asl
A src/ec/starlabs/merlin/acpi/keyboard.asl
A src/ec/starlabs/merlin/acpi/lid.asl
A src/ec/starlabs/merlin/acpi/suspend.asl
A src/ec/starlabs/merlin/acpi/thermal.asl
A src/ec/starlabs/merlin/acpi/typec.asl
A src/ec/starlabs/merlin/acpi/ubtc.asl
A src/ec/starlabs/merlin/chip.h
A src/ec/starlabs/merlin/ec.c
A src/ec/starlabs/merlin/ec.h
A src/ec/starlabs/merlin/variants/cml/ecdefs.h
A src/ec/starlabs/merlin/variants/cml/emem.asl
A src/ec/starlabs/merlin/variants/cml/events.asl
A src/ec/starlabs/merlin/variants/kbl/ecdefs.h
A src/ec/starlabs/merlin/variants/kbl/emem.asl
A src/ec/starlabs/merlin/variants/kbl/events.asl
A src/ec/starlabs/merlin/variants/merlin/ecdefs.h
A src/ec/starlabs/merlin/variants/merlin/emem.asl
A src/ec/starlabs/merlin/variants/merlin/events.asl
A src/ec/starlabs/merlin/variants/tgl/ecdefs.h
A src/ec/starlabs/merlin/variants/tgl/emem.asl
A src/ec/starlabs/merlin/variants/tgl/events.asl
28 files changed, 3,063 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58343/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
Gerrit-Change-Number: 58343
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems>
Gerrit-MessageType: newpatchset
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58345 )
Change subject: mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_EN
......................................................................
mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_EN
The definition of those bits changed between Picasso and Renoir/Cezanne
so add a comment where those bit definitions are used as well.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272
---
M src/mainboard/google/guybrush/bootblock.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/58345/1
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c
index 4a0d384..83ac43a 100644
--- a/src/mainboard/google/guybrush/bootblock.c
+++ b/src/mainboard/google/guybrush/bootblock.c
@@ -34,6 +34,8 @@
size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios;
+ /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped
+ on Picasso and older compared to Renoir/Cezanne and newer */
dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN);
dword |= LPC_LDRQ0_PD_EN;
--
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Gerrit-Branch: master
Gerrit-Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272
Gerrit-Change-Number: 58345
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Sean Rhodes has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/58344 )
Change subject: ec/starlabs: Add standardised ITE EC support
......................................................................
ec/starlabs: Add standardised ITE EC support
Add EC support that supports different Q Events and EC memory.
Tested with:
* IT5570E
* IT8987E
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Iaf8f37a08c232b8754e57f022782f21284fa07dd
---
M src/ec/starlabs/merlin/variants/merlin/emem.asl
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/58344/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaf8f37a08c232b8754e57f022782f21284fa07dd
Gerrit-Change-Number: 58344
Gerrit-PatchSet: 2
Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems>
Gerrit-MessageType: newpatchset
Attention is currently required from: Sridhar Siricilla, Paul Menzel, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55363 )
Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/55363/comment/05c69296_6f5cad36
PS8, Line 116: heci_reset();
are you observing any increase in boot time while executing this additional reset flow?
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
Gerrit-Change-Number: 55363
Gerrit-PatchSet: 8
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Gerrit-Comment-Date: Thu, 14 Oct 2021 19:59:16 +0000
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58341 )
Change subject: mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes
......................................................................
mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes
The writes were originally added due to being part of the initialization
sequence in the reference code, but coreboot already has those registers
cleared by the time we reach this part of the code, so we can drop these
redundant writes.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I43344460e5355664841d77daf1df3fd386e047e9
---
M src/mainboard/google/guybrush/bootblock.c
1 file changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58341/1
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c
index 040bc52..4a0d384 100644
--- a/src/mainboard/google/guybrush/bootblock.c
+++ b/src/mainboard/google/guybrush/bootblock.c
@@ -39,8 +39,11 @@
dword |= LPC_LDRQ0_PD_EN;
pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
- pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0);
- pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
+ /*
+ * All LPC decodes need to be cleared before we can configure the LPC pads as secondary
+ * eSPI interface that gets used for the EC communication. This is already done by
+ * lpc_disable_decodes that gets called before this function.
+ */
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return;
--
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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