Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58335 )
Change subject: mb/google/kahlee/treeya/audio: use proper I2C base address define
......................................................................
mb/google/kahlee/treeya/audio: use proper I2C base address define
I2C_BASE_ADDRESS is the beginning of the MMIO space that contains the
I2C controllers MMIO. I2C[ABCD]_BASE_ADDRESS are the base addresses of
the 4 I2C controllers, so use I2CA_BASE_ADDRESS instead here.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ie8d6a438f76cd33929f5070f9ec6b2f280f471a0
---
M src/mainboard/google/kahlee/variants/treeya/audio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/58335/1
diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c
index 8265298..1c7a4c4 100644
--- a/src/mainboard/google/kahlee/variants/treeya/audio.c
+++ b/src/mainboard/google/kahlee/variants/treeya/audio.c
@@ -23,7 +23,7 @@
printk(BIOS_INFO, "Checking audio codec\n");
return;
}
- } while (mmio_dev->path.mmio.addr != I2C_BASE_ADDRESS);
+ } while (mmio_dev->path.mmio.addr != I2CA_BASE_ADDRESS);
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
if (child->path.type != DEVICE_PATH_I2C)
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58307 )
Change subject: soc/amd/common/block/i2c: implement proper read_resource
......................................................................
Patch Set 4: Code-Review+2
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58307
to look at the new patch set (#4).
Change subject: soc/amd/common/block/i2c: implement proper read_resource
......................................................................
soc/amd/common/block/i2c: implement proper read_resource
Before this patch the reservation of the MMIO region of the I2C
controllers was done in the LPC controller PCI device despite the I2C
controllers already being devices in the devicetree. This patch
implements this functionality as read_resources function of the I2C
device instead. This will only reserve the memory when the I2C devices
are enabled in devicetree which is a change from the previous behavior.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0
---
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/common/block/i2c/i2c.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
5 files changed, 6 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/58307/4
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57392 )
Change subject: mb/google: Add OEM product names for various boards
......................................................................
Patch Set 5: Code-Review+2
(2 comments)
File src/mainboard/google/dedede/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/57392/comment/db3f6597_8f17dd7c
PS5, Line 16: Drawcia (HP Chromebook x360 11 G4 EE)"
drawcia also covers drawlat and drawman, so this is also
HP Chromebook 11 G9 EE
HP Chromebook 14 G7
https://review.coreboot.org/c/coreboot/+/57392/comment/635a3937_12598fcd
PS5, Line 99: bool "-> Storo"
ASUS Chromebook CR1100
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Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58317 )
Change subject: soc/intel/common/acpi: Correct IPC sub command for reading LPM requirement
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hi Ethan, +Cliff Huang told me that the 2nd argument was not required for this command, see https:// […]
Hi Tim, I checked our latest PMC document. This has been changed to use subcommand=2 for command 0xa0. I don't have our external NDA document. Can you request for the latest one from you end? Currently, I don't see issue when using subcmd=0 for adl yet, but this could be potential issue in the future. Thanks.
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 )
Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 6:
(1 comment)
File payloads/libpayload/tests/Makefile.inc:
PS4:
> How likely is this?
I am working on a CBFS_VERIFICATION support in the libpayload. It requires vboot for hash functions. And that's why I want this framework to be present in the libpayload. (It's easier to test it with unit-tests than on a actual device)
> Copying makefiles adds technical debt, and if we're not going to need the separate functionality later, then the tradeoff isn't worth it.
> ---
> Agreed, and *then* you make the copy and have the files diverge.
Libpayload still has a separate and independent Makefiles (or it seems to be that way), which are partially identical to ones from main coreboot tree.
On the other hand libpayload is somehow unique in a way it handles its config (kconfig negatives, and custom CONFIG_LP_ prefix), has different implementation of stdlib, and it contains (and installs) lpgcc wrapper for building payloads with it. There are many small but important differences between the two.
So, we have two ways: Leave it as it is now, or integrate it with main coreboot tree. I think that partial integration (unit-tests only) will be harder to manage due to reasons mentioned above. I also do not *think* that full integration is currently possible.
I understand your concerns about duplicated build systems. I will do my best to maintain both of them. (I already found few issues requiring fixing, while rewriting it for libpayload).
> As I make these comments, please understand that I'm not *demanding* that we have a single makefile that builds the unit tests for coreboot and libpayload. I just want us to consider whether the choice we're making is the right one.
Oh..., I am sorry. I didn't think that you are demanding it. I really appreciate your involvement. Maybe my writing style is too defensive (or aggressive?) sometimes.
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Change subject: mb/google/brya/var/taeko: Include driver for GL9763E for eMMC boot disk
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/block: move FCH IOAPIC resource from LPC to SMBus
......................................................................
Patch Set 1: Code-Review-2
(1 comment)
Patchset:
PS1:
turns out that the FCH IOAPIC base is configured in BAR0 of the LPC PCI dev, so this likely isn't the way to go
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58191 )
Change subject: soc/qualcomm/sc7280: Enable compression of SHRM
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58191/comment/147a558f_a562c4ef
PS3, Line 15: Also, did some cleanup in this file based on comments in CB:49392.
> In the future, it would be great to have this in a separate commit.
Noted. I bunched these changes together because they seemed so small to me that I didn't think that it merited a separate CL.
https://review.coreboot.org/c/coreboot/+/58191/comment/8cddf2ca_13148b95
PS3, Line 19: TEST=Make sure we can still boot to kernel on herobrine
> What timing differences are there?
I see no boot time differences, actually.
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