coreboot-gerrit September 2020

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Change in coreboot[master]: configs: add ASUS A88XM-E sample configuration
by Mike Banon (Code Review) 02 Jun '22

02 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39900 ) Change subject: configs: add ASUS A88XM-E sample configuration ...................................................................... configs: add ASUS A88XM-E sample configuration You can use this .config as the base configuration for your A88XM-E by saving it to ./coreboot/.config - however, you may want to change some of its' configs! If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ief7475faaac3e96546436a13d808eac3728575e9 --- A configs/config.asus_a88xm-e 1 file changed, 762 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39900/1 diff --git a/configs/config.asus_a88xm-e b/configs/config.asus_a88xm-e new file mode 100644 index 0000000..a4469e0 --- /dev/null +++ b/configs/config.asus_a88xm-e @@ -0,0 +1,762 @@ +######### +### +### ./coreboot/.config for ASUS A88XM-E - 27 Mar 2020 +### +######### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_TIMESTAMPS_ON_CONSOLE=y +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_CBMEM_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="A88XM-E" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="asus/a88xm-e" +CONFIG_MAX_CPUS=4 +CONFIG_VGA_BIOS_ID="1002,990c" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_IRQ_SLOT_COUNT=11 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_VGA_BIOS=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_VGA_BIOS_FILE="pci1002,990c.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x8000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_BOARD_ASUS_A88XM_E=y +# CONFIG_BOARD_ASUS_AM1I_A is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_H61M_CS is not set +# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +# CONFIG_BOARD_ASUS_P5QC is not set +# CONFIG_BOARD_ASUS_P5Q_PRO is not set +# CONFIG_BOARD_ASUS_P5QL_PRO is not set +# CONFIG_BOARD_ASUS_P5Q is not set +# CONFIG_BOARD_ASUS_P5QL_EM is not set +# CONFIG_BOARD_ASUS_P5QPL_AM is not set +# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set +# CONFIG_BOARD_ASUS_P8Z77_M_PRO is not set +# CONFIG_BOARD_ASUS_P8Z77_V_LX2 is not set +# CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_135 is not set +CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_150=y +# CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_165 is not set +CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL=0x0 +# CONFIG_HUDSON_XHCI_FWM is not set +# CONFIG_HUDSON_IMC_FWM is not set +# CONFIG_CONFIG_HUDSON_XHCI_ENABLE is not set +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +# CONFIG_POST_IO is not set +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_UART_FOR_CONSOLE=0 +# CONFIG_VBOOT is not set +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="A88XM-E" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0xc0000 +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x00800000 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_CPU_ADDR_BITS=48 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d" +CONFIG_BOTTOMIO_POSITION=0x80000000 +# CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW is not set +CONFIG_SOC_AMD_COMMON=y +# CONFIG_SOC_AMD_PI is not set +CONFIG_SOC_AMD_COMMON_BLOCK=y + +# +# AMD SoC Common IP Code +# +# CONFIG_SOC_AMD_COMMON_BLOCK_ACPI is not set +CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO=y +# CONFIG_SOC_AMD_COMMON_BLOCK_ALINK is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_CAR is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_HDA is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_IOMMU is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_LPC is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_PCI is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_PI is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_PSP is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_SATA is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_SPI is not set +# CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG is not set +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QUALCOMM_COMMON is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SC7180 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +CONFIG_CPU_AMD_AGESA=y +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=8192 +CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +CONFIG_UNKNOWN_TSC_RATE=y +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_HAVE_SMI_HANDLER is not set +# CONFIG_NO_SMM is not set +CONFIG_SMM_ASEG=y +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_X86_AMD_INIT_SIPI is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_SMP=y +CONFIG_SSE=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_ASPEED_AST2400 is not set +# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set +# CONFIG_SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND is not set +# CONFIG_SUPERIO_FINTEK_FAN_CONTROL is not set +CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y +CONFIG_SUPERIO_ITE_ENV_CTRL=y +CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y +CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y +CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y +CONFIG_SUPERIO_ITE_IT8728F=y + +# +# Embedded Controllers +# +# CONFIG_EC_51NB_NPCE985LA0DX is not set +# CONFIG_EC_GOOGLE_CHROMEEC_SKUID is not set +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARM_LPAE is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_X86_RESET_VECTOR=0xfffffff0 +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CBMEM_TOP_BACKUP=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y +# CONFIG_PIRQ_ROUTE is not set + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +CONFIG_BOOTSPLASH=y +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_HT_CHAIN_UNITID_BASE=0 +CONFIG_HT_CHAIN_END_UNITID_BASE=0 +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_PCIEXP_HOTPLUG is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_VGA_BIOS_SECOND is not set +# CONFIG_CHECK_REV_IN_OPROM_NAME is not set +CONFIG_VGA_BIOS_DGPU=y +CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6758.rom" +CONFIG_VGA_BIOS_DGPU_ID="1002,6758" +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_MAINBOARD_HAS_CRB_TPM is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SUPPORT_LEGACY_VPD_MAC is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +# CONFIG_SPI_SDCARD is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_WIFI is not set +CONFIG_DRIVERS_AMD_PI=y +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GFX_GENERIC is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_PTN3460 is not set +# CONFIG_DRIVERS_I2C_RT1011 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_ISH is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_HAVE_INTEL_PTT is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +# CONFIG_DEFAULT_POST_ON_LPC is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_DISABLE_ACPI_HIBERNATE is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_NO_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +# CONFIG_COMPRESSED_PAYLOAD_NONE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +CONFIG_MAX_REBOOT_CNT=3 +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/39900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7475faaac3e96546436a13d808eac3728575e9 Gerrit-Change-Number: 39900 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 26

Change in ...coreboot[master]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review) 02 Jun '22

02 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33800 Change subject: configs: add ASUS AM1I-A sample configuration ...................................................................... configs: add ASUS AM1I-A sample configuration You can use this .config as the base configuration for your AM1I-A by saving it to ./coreboot/.config - however, you may want to change some of its' configs! If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 --- A configs/config.asus_am1i-a 1 file changed, 789 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33800/1 diff --git a/configs/config.asus_am1i-a b/configs/config.asus_am1i-a new file mode 100644 index 0000000..0660c44 --- /dev/null +++ b/configs/config.asus_am1i-a @@ -0,0 +1,789 @@ +######### +### +### ./coreboot/.config for ASUS AM1I-A - 26 Jun 2019 +### +######### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/am1i-a" +CONFIG_MAINBOARD_PART_NUMBER="AM1I-A" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_IRQ_SLOT_COUNT=9 +CONFIG_VGA_BIOS_ID="1002,9830" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_AZ_PIN=0xaa +CONFIG_VGA_BIOS_FILE="pci1002,9830.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_BOARD_ASUS_AM1I_A=y +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_H61M_CS is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +# CONFIG_BOARD_ASUS_P5QC is not set +# CONFIG_BOARD_ASUS_P5Q_PRO is not set +# CONFIG_BOARD_ASUS_P5QL_PRO is not set +# CONFIG_BOARD_ASUS_P5QPL_AM is not set +# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set +# CONFIG_HUDSON_IMC_FWM is not set +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=4 +CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="AM1I-A" +CONFIG_CPU_ADDR_BITS=40 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QUALCOMM_COMMON is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY16_KB=y +CONFIG_FORCE_AM1_SOCKET_SUPPORT=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_ASPEED_AST2400 is not set +# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set +CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y +CONFIG_SUPERIO_ITE_ENV_CTRL=y +CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y +CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y +CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y +CONFIG_SUPERIO_ITE_IT8623E=y + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_RISCV_M is not set +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_USER_TPM1 is not set +# CONFIG_USER_TPM2 is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO=y +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_POSTCAR=y +CONFIG_HAVE_RAMSTAGE=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/33800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 Gerrit-Change-Number: 33800 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 38

Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review) 02 Jun '22

02 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509 Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches Conveniently and securely gets, checks SHA256 and installs some of my patches from this page - https://review.coreboot.org/q/status:open+banon - and also gets a collection of useful floppy-based operating systems. Sometimes it takes quite a long time to get a patch merged, while the people might need it today! - and this script could be really helpful. It asks a [Y/N] question for every addition, and since there are some "universal" patches as well as great floppies, you may still want to run this script - even if your board is not Lenovo G505S or not AMD. Please share your feedback/suggestions and tell about other useful patches, preferably the "universal" ones - i.e. SeaBIOS. Currently included: 1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs 2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb ; tint build system ; and also a floppies collection : KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird. Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 --- A csb_patcher.sh 1 file changed, 876 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1 diff --git a/csb_patcher.sh b/csb_patcher.sh new file mode 100755 index 0000000..b325f71 --- /dev/null +++ b/csb_patcher.sh @@ -0,0 +1,876 @@ +#!/bin/sh +# +# csb_patcher.sh: coreboot and SeaBIOS patcher script. +# +# Conveniently and securely gets, checks SHA256 and installs some of my +# patches from this page - https://review.coreboot.org/q/status:open+banon +# and also gets a collection of useful floppy-based operating systems. +# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com> +# + +# Keys +enter=$( printf '\015' ) +ctrl_c=$( printf '\003' ) +ctrl_x=$( printf '\030' ) +ctrl_z=$( printf '\032' ) + +# Formatting +bold="\e[1m" +bred="\e[1;31m" +bgreen="\e[1;32m" +byellow="\e[1;33m" +bend="\e[0m" + +# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y. +yesno () { + printf "$1 [Y/N] " + yesno_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + yesno_answer=$( head -c 1 ) + case "$yesno_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$yesno_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"y"*|"Y"*) + stty "$yesno_old_stty_cfg" + printf "${bgreen}YES${bend}$2\n" + return 0 + ;; + *"n"*|"N"*) + stty "$yesno_old_stty_cfg" + printf "${byellow}NO${bend}\n" + return 1 + ;; + esac + done +} + +# Waits until a user presses Enter. +encontinue () { + printf "\npress [ENTER] to continue... " + encontinue_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + encontinue_answer=$( head -c 1 ) + case "$encontinue_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$encontinue_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"$enter"*) + stty "$encontinue_old_stty_cfg" + printf "\n" + return 0 + ;; + esac + done +} + +# Checks if a command '$1' exists. +command_exists() { + if [ ! -x "$( command -v $1 )" ] ; then + printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Checks if a file '$1' exists. +file_exists () { + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Force removes a file '$2' and then copies a file '$1' to '$2'. +copier () { + if file_exists "$1" ; then + rm -f "$2" + cp "$1" "$2" + return 0 + else + return 1 + fi +} + +# Force removes a file '$2' and then moves a file '$1' to '$2'. +mover () { + if file_exists "$1" ; then + rm -f "$2" + mv "$1" "$2" + return 0 + else + return 1 + fi +} + +# Checks if line '$1' contains the text '$2'. +checker () { + case "$1" in + *"$2"*) + return 0 + ;; + *) + return 1 + ;; + esac +} + +# Prints the lines of a file '$2' which contain the text '$1'. +grepper () { + if file_exists "$2" ; then + while IFS= read -r grepper_line + do + case "$grepper_line" in + *"$1"*) + printf '%s\n' "$grepper_line" + ;; + esac + done < "$2" + return 0 + else + return 1 + fi +} + +# Checks if a file '$2' contains the text '$1'. +grepcheck () { + if file_exists "$2" ; then + while IFS= read -r grepcheck_line + do + case "$grepcheck_line" in + *"$1"*) + return 0 + ;; + esac + done < "$2" + return 1 + else + return 1 + fi +} + +# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'. +sedder () { + if file_exists "$1" ; then + csb_sedder_tmp="./.csb_sedder" + rm -f "$csb_sedder_tmp" + while IFS= read -r sedder_line + do + case "$sedder_line" in + *"$2"*) + if [ ! -z "$3" ] ; then + printf '%s\n' "$3" >> "$csb_sedder_tmp" + fi + ;; + *) + printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp" + ;; + esac + done < "$1" + mover "$csb_sedder_tmp" "$1" + return 0 + else + return 1 + fi +} + +# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful. +wgetter () { + rm -f "$1" + if [ -z "$3" ] ; then + wget "$2" + else + wget "$3" "$2" + fi + if [ -f "$1" ] ; then + wgetter_file_size=$(($( wc -c < "$1" ))) + if [ "$wgetter_file_size" -eq "0" ] ; then + rm -f "$1" + fi + fi + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !" + printf "\n Please check your Internet connection and try again.\n" + encontinue + return 1 + else + return 0 + fi +} + +# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it. +unzipper () { + if file_exists "$1" ; then + if [ -z "$2" ] ; then + unzip "$1" + else + unzip -j "$1" "$2" + fi + rm -f "$1" + return 0 + else + return 1 + fi +} + +# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560. +expander () { + if file_exists "$1" && [ ! -z "$2" ] ; then + expander_file_size=$(($( wc -c < "$1" ))) + if [ "$expander_file_size" -lt "$2" ] ; then + dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache + fi + return 0 + else + return 1 + fi +} + +# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches. +floppy_verifier () { + rm -f "./.$1" + cd ".." + if [ ! -z "$2" ] ; then + if file_exists "./floppies/$1.img" ; then + floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img" + floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" ) + printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n" + if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then + printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n" + cd "./floppies/" + touch "./.$1" + return 0 + else + printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n" + encontinue + cd "./floppies/" + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum" + printf "\n is changing constantly and not provided by $1 project, so not checked.\n" + encontinue + cd "./floppies/" + touch "./.$1" + return 0 + fi +} + +# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image. +floppy_mass_downloader () { + printf "\n" + if [ ! -d "./floppies/" ]; then + mkdir "./floppies/" + fi + cd "./floppies/" + # KOLIBRI + if command_exists "7za" ; then + if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then + rm -f "./kolibri.img" + 7za x "./latest-img.7z" + rm -f "./latest-img.7z" + floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + else + printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n" + encontinue + fi + # FREEDOS + if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then + unzipper "./FD12FLOPPY.zip" "FLOPPY.img" + mover "./FLOPPY.img" "./freedos.img" + floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537" + fi + # MICHALOS + printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n" + if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then + unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img" + floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c" + fi + # SNOWDROP + if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then + floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + # FIWIX + if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then + floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd" + fi + # MEMTEST + if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then + unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin" + expander "./memtestp.bin" "1474560" + mover "./memtestp.bin" "./memtest.img" + floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1" + fi + # TATOS + if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then + expander "./tatos.img" "1474560" + floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1" + fi + # PLOP + if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then + unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img" + mover "./plpbt.img" "./plop.img" + floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27" + fi + # FLOPPYBIRD + if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then + floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f" + fi + # Some floppies have the weird permissions after their extraction + floppy_mass_downloader_floppies=$( find . -name "*.img" ) + if [ ! -z "$floppy_mass_downloader_floppies" ] ; then + chmod 755 "./"*".img" + fi + # Return back to ./coreboot/ + cd ".." + return 0 +} + +# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info. +atombios_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./pci1002,$1.rom" ] ; then + atombios_adder_cbfs=$( "$2" "$3" print ) + if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then + printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n" + else + if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ," + printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info. +floppy_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./floppies/$1.img" ] ; then + if [ -f "./floppies/.$1" ] ; then + floppy_adder_cbfs=$( "$2" "$3" print ) + if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then + printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n" + else + if checker "$1" "plop" ; then + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !" + printf "\n Add it only if you really need it and trust the author of $1 project.\n" + encontinue + fi + if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -" + printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool. +cbfs_mass_adder () { + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if file_exists "$2" && file_exists "$3" ; then + if checker "$1" "atom" || checker "$1" "flop" ; then + copier "$3" "$4" + printf "\n${bold}=== $4 - initial memory map${bend}\n\n" + "$2" "$4" print + printf "\n" + if checker "$1" "atom" ; then +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " + atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G" + atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M" + atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230" + atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series" + atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D" + fi + if checker "$1" "flop" ; then + if [ ! -d "./floppies/" ] ; then + printf "\n" + floppy_mass_downloader + fi + # Default boot order: the last floppy added - is the first floppy to boot! + floppy_adder "floppybird" "$2" "$4" "2K" + floppy_adder "plop" "$2" "$4" "74K" + floppy_adder "tatos" "$2" "$4" "60K" + floppy_adder "memtest" "$2" "$4" "44K" + floppy_adder "fiwix" "$2" "$4" "458K" + floppy_adder "snowdrop" "$2" "$4" "126K" + floppy_adder "michalos" "$2" "$4" "256K" + floppy_adder "freedos" "$2" "$4" "698K" + floppy_adder "kolibri" "$2" "$4" "1264K" + fi + printf "\n${bold}=== $4 - final memory map${bend}\n\n" + "$2" "$4" print + printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n" + return 0 + else + return 1 + fi + else + return 1 + fi +} + +# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'. +csb_finder () { + csb_finder_files=$( find . -name "*.$1" ) + if [ ! -z "$csb_finder_files" ] ; then + printf "%25s\n" "*.$1 - YES" >> "$2" + printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n" + printf "$csb_finder_files" + printf "\n That means - Some patches $3\n" + encontinue + return 0 + else + printf "%24s\n" "*.$1 - NO" >> "$2" + return 1 + fi +} + +# Prints a csb_patcher_log '$1' with a custom highlighting. +csb_printer () { + if ! file_exists "$1" ; then + return 1 + fi + while IFS= read -r csb_printer_line + do + case "$csb_printer_line" in + *"orig - YES"*) + printf "${csb_printer_line%???}${byellow}YES" # YELLOW + ;; + *"rej - YES"*) + printf "${csb_printer_line%???}${bred}YES" # RED + ;; + *"YES"*) + printf "${csb_printer_line%???}${bgreen}YES" # GREEN + ;; + *"orig - NO"*|*"rej - NO"*) + printf "${csb_printer_line%??}${bgreen}NO" # GREEN + ;; + *"NO"*) + printf "${csb_printer_line%??}${byellow}NO" # YELLOW + ;; + *"FAILURE_1"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED + ;; + *"FAILURE_2"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED + ;; + *"FAILURE_3"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED + ;; + *"\\\\"*) + printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR + ;; + *) + printf "${bold}$csb_printer_line" + ;; + esac + printf "${bend}\n" + done < "$1" + return 0 +} + +# Configure some popular options of a config file '$1'. +csb_configurer () { + if file_exists "$1" ; then + csb_configurer_tmp="./.csb_configurer" + rm -f "$csb_configurer_tmp" + grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp" + if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then + printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n" + sedder "$1" "### CSB_CONFIGURER OPTIONS" "" + printf "### CSB_CONFIGURER OPTIONS\n" >> "$1" + sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" "" + if ! yesno "Do you have an Intel WiFi adapter?" "" ; then + printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1" + fi + sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" "" + if yesno "Do you have a Discrete GPU?" "" ; then + printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1" + if yesno "No for HD-8570M, Yes for R5-M230" "" ; then + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1" + else + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1" + fi + fi + + sedder "$1" "# NATIVE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" "" + + sedder "$1" "# RAID" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" "" + sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" "" + sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" "" + + sedder "$1" "# AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + sedder "$1" "# LEGACY IDE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" "" + + sedder "$1" "# IDE to AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" "" + + sedder "$1" "# AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" "" + + sedder "$1" "# IDE to AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then + printf "# AHCI\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1" + printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1" + printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1" + else + printf "# NATIVE\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1" + fi + rm -f "$csb_configurer_tmp" + return 0 + else + printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and installs a patch. +# Arguments are the patch properties: +# $1 - new diff name, could be also a part of extracted scripts' filename +# $2 - change ID number, part of download link to review.coreboot.org +# $3 - change revision number, part of download link to review.coreboot.org +# $4 - diff filename inside the downloaded archive, will be renamed to $1 +# $5 - diff known good SHA256 checksum, will be used for SHA256 verification +# $6 - filepath where to save a csb_patcher_log which will be printed later +# $7 - info about the target of a patch, if not specified ("") it is common +# +csb_patcher () { + if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then + printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_1" >> "$6" + csb_printer "$6" + exit 1 + fi + unzipper "./patch?zip" + mover "./$4.diff" "./$1.diff" + csb_patcher_sha256sum_correct="$5 ./$1.diff" + csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" ) + printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n" + if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then + printf "^^^ this is correct, " + csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" ) + csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????} + if [ "$1" = "dgpu" ] ; then + printf "will extract a ${bold}$7$1${bend} patch now...\n" + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_patches.sh" + patch -p1 < "./$1.diff" + chmod +x "./"*"_$1_patches.sh" + "./get_$1_patches.sh" + if ! "./check_$1_patches.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + else + printf "${bold}$7$1${bend} patch could be applied now...\n" + fi + if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \ + [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if [ -f "./.$1" ] ; then + printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory," + printf "\n maybe you have applied this patch already.\n\n" + fi + if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then + if [ "$1" = "dgpu" ] ; then + "./apply_$1_patches.sh" + else + if [ "$1" = "atombios" ] ; then + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_roms.sh" + rm -f "./pci1002\,"*".rom" + rm -f "./pci1002\,"*".rom.txt" + fi + if [ "$1" = "tint" ] ; then + rm -f "./payloads/external/tint/tint.sh" + rm -f "./payloads/external/tint/"*"_core.sh" + rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch" + fi + if [ "$1" = "seabios" ] ; then + rm -f "./payloads/external/SeaBIOS/"*".patch" + fi + patch -p1 < "./$1.diff" + if [ "$1" = "atombios" ] ; then + chmod +x "./"*"_$1_roms.sh" + "./extract_$1_roms.sh" + printf "\n" + if ! "./check_$1_roms.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + fi + if [ "$1" = "tint" ] ; then + chmod +x "./payloads/external/tint/"*"_core.sh" + fi + fi + touch ".$1" + printf "%25s\n" "$7$1 - YES" >> "$6" + if [ "$1" = "atombios" ] ; then + encontinue + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can apply it later by running:${bend}" + if [ "$1" = "dgpu" ] ; then + printf "\n${bold} ./apply_$1_patches.sh${bend}\n" + else + printf "\n${bold} patch -p1 < ./$1.diff${bend}\n" + fi + encontinue + fi + fi + if checker "$1" "config" ; then + rm -f "./configs/$1_"* + patch -p1 < "./$1.diff" + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + ls "./configs" > "./.csb_configs" + csb_patcher_config_name=$( grepper "$1" "./.csb_configs" ) + rm -f "./.csb_configs" + printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}" + printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n" + if [ -f "./.config" ] ; then + printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n" + fi + if yesno "Copy it to ./.config now?" "" ; then + copier "./configs/$csb_patcher_config_name" "./.config" + printf "\n" + printf "%25s\n" "$7$1 - YES" >> "$6" + if yesno "Configure this ./.config now?" "" ; then + csb_configurer "./.config" + else + printf "\n${bold}You can configure it later by running:${bend}" + printf "\n${bold} ./csb_patcher.sh config${bend}\n\n" + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can copy it later by running:${bend}" + printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n" + fi + printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n" + encontinue + fi + printf "\n\n" + return 0 + else + printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_2" >> "$6" + csb_printer "$6" + exit 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches. +# $1 - filepath where to save a csb_patcher_log which will be printed later +# +csb_mass_patcher () { +### +### https://review.coreboot.org/c/coreboot/+/31929 +### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches +### + csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S " +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " +### +### https://review.coreboot.org/c/coreboot/+/23856 +### tint: introduce the new tint build system with checksum verification +### + csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32351 +### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb +### + csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32352 +### configs: add Lenovo G505S sample configuration (use with dGPU patches) +### +csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" "" + + return 0 +} + +# Prints a usage info for this ./csb_patcher.sh script. +csb_usage () { + printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n" + printf "${bold}./csb_patcher.sh${bend}\n" + printf " patch your coreboot source code\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n" + printf " print this usage info\n\n" + printf "${bold}==================== Before building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n" + printf " configure some popular options\n\n" + printf "${bold}==================== After building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n" + printf " add the AtomBIOS to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n" + printf " add the floppies to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n" + printf " both AtomBIOS VGA ROMs and floppies\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n" + printf " print a ./.csb_patcher log\n\n" + return 0 +} + +# +# MAIN PART OF A CSB_PATCHER SCRIPT +# + +if [ -z "$1" ] ; then + csb_patcher_log="./.csb_patcher" + rm -f "$csb_patcher_log" + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" || \ + ! command_exists "patch" ; then + exit 1 + fi + printf '\n\n' >> "$csb_patcher_log" + printf ' \\\\!//\n' >> "$csb_patcher_log" + printf ' (o o)\n' >> "$csb_patcher_log" + printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log" + printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log" + printf 'Please send your feedback to\n' >> "$csb_patcher_log" + printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + encontinue + printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log" + + csb_mass_patcher "$csb_patcher_log" + + if yesno "Download a ${bold}floppies${bend} collection?" "" ; then + floppy_mass_downloader + printf "%25s\n" "floppies - YES" >> "$csb_patcher_log" + else + printf "\n" + printf "%24s\n" "floppies - NO" >> "$csb_patcher_log" + fi + + printf '==================== Bad files found?\n' >> "$csb_patcher_log" + csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it." + csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}" + + printf '\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + csb_usage +else + case "$1" in + *"print"*) + csb_patcher_log="./.csb_patcher" + csb_printer "$csb_patcher_log" + ;; + *"config"*) + csb_configurer "./.config" + ;; + *"atom"*|*"flop"*) + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" ; then + exit 1 + fi + cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom" + ;; + *"help"*|*"usage"*) + printf "\n" + csb_usage + ;; + *) + printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n" + csb_usage + exit 1 + ;; + esac +fi + +exit 0 + -- To view, visit https://review.coreboot.org/c/coreboot/+/33509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 Gerrit-Change-Number: 33509 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 100

Change in coreboot[master]: [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash
by Arthur Heymans (Code Review) 23 May '22

23 May '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44294 ) Change subject: [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash ...................................................................... [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash Save the regular boot MTRR's that are restored on the S3 path during the CPU init with cbmem instead of storing them to the SPI flash. Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/s3_mtrr.c M src/northbridge/amd/agesa/agesa_helper.h 4 files changed, 21 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44294/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a0..058a9d4 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -8,6 +8,7 @@ #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 +#define CBMEM_ID_AGESA_MTRR 0xf08b4b9d #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 @@ -74,6 +75,7 @@ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ + { CBMEM_ID_AGESA_MTRR, "AGESA MTRR " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index e47daf3..0b37d3e 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -9,45 +9,24 @@ #include <AGESA.h> #include <northbridge/amd/agesa/agesa_helper.h> -typedef enum { - S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - /* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_MTRR_SIZE 0x1000 #define S3_DATA_NONVOLATILE_SIZE 0x1000 -#if CONFIG(HAVE_ACPI_RESUME) && \ - (S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE #error "Please increase the value of S3_DATA_SIZE" #endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len) +static void get_s3nv_data(uintptr_t *pos, uintptr_t *len) { /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeMTRR: - *pos = s3_data; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } + *pos = CONFIG_S3_DATA_POS; + *len= S3_DATA_NONVOLATILE_SIZE; } AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock) { uintptr_t pos, size; - get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + get_s3nv_data(&pos, &size); u32 len = *(u32*)pos; @@ -101,15 +80,12 @@ #endif } -static u8 MTRRStorage[S3_DATA_MTRR_SIZE]; - AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) { - u32 MTRRStorageSize = 0; uintptr_t pos, size; /* To be consumed in AmdInitResume. */ - get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + get_s3nv_data(&pos, &size); if (size && dataBlock->NvStorageSize) spi_SaveS3info(pos, size, dataBlock->NvStorage, dataBlock->NvStorageSize); @@ -127,24 +103,9 @@ } /* Collect MTRR setup. */ - backup_mtrr(MTRRStorage, &MTRRStorageSize); - - /* To be consumed in restore_mtrr, CPU enumeration in ramstage. */ - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - if (size && MTRRStorageSize) - spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize); + backup_mtrr(); return AGESA_SUCCESS; } #endif /* ENV_RAMSTAGE */ - -const void *OemS3Saved_MTRR_Storage(void) -{ - uintptr_t pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - if (!size) - return NULL; - - return (void *)(pos + sizeof(UINT32)); -} diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 672eb20..be38327 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> +#include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -20,12 +21,16 @@ msr_t top_mem2; }; -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) +void backup_mtrr(void) { msr_t syscfg_msr; - struct mtrr_backup *mtrr_save = (struct mtrr_backup *)mtrr_store; + struct mtrr_backup *mtrr_save; uint32_t i; + mtrr_save = cbmem_add(CBMEM_ID_AGESA_MTRR, sizeof(struct mtrr_backup)); + if (!mtrr_save) + return; + /* Enable access to AMD RdDram and WrDram extension bits */ syscfg_msr = rdmsr(SYSCFG_MSR); syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -51,16 +56,17 @@ mtrr_save->syscfg = rdmsr(SYSCFG_MSR); mtrr_save->top_mem = rdmsr(TOP_MEM); mtrr_save->top_mem2 = rdmsr(TOP_MEM2); - - *mtrr_store_size = sizeof(struct mtrr_backup); } void restore_mtrr(void) { msr_t syscfg_msr; - struct mtrr_backup *mtrr_save = (struct mtrr_backup *)OemS3Saved_MTRR_Storage(); + struct mtrr_backup *mtrr_save = cbmem_find(CBMEM_ID_AGESA_MTRR); uint32_t i; + if (!mtrr_save) + return; + /* Enable access to AMD RdDram and WrDram extension bits */ syscfg_msr = rdmsr(SYSCFG_MSR); syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 120e74a..ef6085f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -39,7 +39,7 @@ void recover_postcar_frame(struct postcar_frame *pcf, int s3resume); void restore_mtrr(void); -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); +void backup_mtrr(void); const void *OemS3Saved_MTRR_Storage(void); #endif /* _AGESA_HELPER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Gerrit-Change-Number: 44294 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data
by Arthur Heymans (Code Review) 23 May '22

23 May '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44295 ) Change subject: [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data ...................................................................... [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data Most of the code is copied from soc/amd/common/block/s3/s3_resume.c The current default MRC_CACHE FMAP region is 64K instead of 8K. One could make this configurable in the future. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/Makefile.inc M src/drivers/amd/agesa/oem_s3.c 3 files changed, 38 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44295/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..f407139 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select CACHE_MRC_SETTINGS if CPU_AMD_AGESA @@ -53,14 +54,6 @@ Try to restore memory training results from non-volatile memory. -config S3_DATA_POS - hex - default 0xFFFF0000 - -config S3_DATA_SIZE - int - default 8192 - endif # CPU_AMD_AGESA source "src/cpu/amd/agesa/family14/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 14067e1..1f9cca5 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -3,18 +3,3 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 0b37d3e..8d32bae 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -1,41 +1,53 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <spi-generic.h> -#include <spi_flash.h> #include <string.h> +#include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <mrc_cache.h> +#include <reset.h> #include <northbridge/amd/agesa/state_machine.h> #include <AGESA.h> #include <northbridge/amd/agesa/agesa_helper.h> -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_NONVOLATILE_SIZE 0x1000 +/* Training data versioning is not supported or tracked. */ +#define DEFAULT_MRC_VERSION 0 -#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(uintptr_t *pos, uintptr_t *len) +static void __noreturn reboot_from_resume(const char *message) { - /* FIXME: Find file from CBFS. */ - *pos = CONFIG_S3_DATA_POS; - *len= S3_DATA_NONVOLATILE_SIZE; + printk(BIOS_ERR, "%s", message); +// set_pm1cnt_s5(); TODO?? + board_reset(); } AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - get_s3nv_data(&pos, &size); + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; + struct region_device rdev; - u32 len = *(u32*)pos; + if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + &rdev)) + reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - /* Test for uninitialized s3nv data in SPI. */ - if (len == 0 || len == (u32)-1ULL) - return AGESA_FATAL; + base = rdev_mmap_full(&rdev); + size = region_device_sz(&rdev); + if (!base || !size) + reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); - dataBlock->NvStorageSize = len; - dataBlock->NvStorage = (void *) (pos + sizeof(u32)); + /* Read 16 bytes to infer if the NV has been erased from flash. */ + for (i = 0; i < 4; i++) + erased &= read32((uint32_t *)base + i); + if (erased == 0xffffffff) + reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); + + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + return AGESA_SUCCESS; } @@ -56,44 +68,13 @@ return AGESA_SUCCESS; } -#if ENV_RAMSTAGE - -static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) -{ -#if CONFIG(SPI_FLASH) - struct spi_flash flash; - - spi_init(); - if (spi_flash_probe(0, 0, &flash)) - return -1; - - spi_flash_volatile_group_begin(&flash); - - spi_flash_erase(&flash, pos, size); - spi_flash_write(&flash, pos, sizeof(len), &len); - spi_flash_write(&flash, pos + sizeof(len), len, buf); - - spi_flash_volatile_group_end(&flash); - return 0; -#else - return -1; -#endif -} - AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - - /* To be consumed in AmdInitResume. */ - get_s3nv_data(&pos, &size); - if (size && dataBlock->NvStorageSize) - spi_SaveS3info(pos, size, dataBlock->NvStorage, - dataBlock->NvStorageSize); - else - printk(BIOS_EMERG, - "Error: Cannot store memory training results in SPI.\n" - "Error: S3 resume will not be possible.\n" - ); + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } /* To be consumed in AmdS3LateRestore. */ char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); @@ -107,5 +88,3 @@ return AGESA_SUCCESS; } - -#endif /* ENV_RAMSTAGE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Gerrit-Change-Number: 44295 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer arit...
by Arthur Heymans (Code Review) 23 May '22

23 May '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44293 ) Change subject: [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer aritmetic ...................................................................... [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer aritmetic The size of the data used is fixed in this function so there is no need for this aritmetic. The function signature will be changed in a followup commit. Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/s3_mtrr.c 1 file changed, 53 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44293/1 diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 6c7ba5f..672eb20 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -8,114 +8,82 @@ #include <string.h> #include <northbridge/amd/agesa/agesa_helper.h> -static void write_mtrr(u8 **p_nvram_pos, unsigned int idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} +struct mtrr_backup { + msr_t mtrr_fix_64k_00000; + msr_t mtrr_fix_16k_80000; + msr_t mtrr_fix_16k_a0000; + msr_t mtrr_fix_4k_xx000[8]; /* 4K_C0000 -- 4K_F8000 */ + msr_t mtrr_phys_base[8]; + msr_t mtrr_phys_mask[8]; + msr_t syscfg; + msr_t top_mem; + msr_t top_mem2; +}; void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) { - u8 *nvram_pos = mtrr_store; - msr_t msr_data; - u32 i; + msr_t syscfg_msr; + struct mtrr_backup *mtrr_save = (struct mtrr_backup *)mtrr_store; + uint32_t i; /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, MTRR_FIX_64K_00000); - write_mtrr(&nvram_pos, MTRR_FIX_16K_80000); - write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000); + mtrr_save->mtrr_fix_64k_00000 = rdmsr(MTRR_FIX_64K_00000); + mtrr_save->mtrr_fix_16k_80000 = rdmsr(MTRR_FIX_16K_80000); + mtrr_save->mtrr_fix_16k_a0000 = rdmsr(MTRR_FIX_16K_A0000); - for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++) - write_mtrr(&nvram_pos, i); + for (i = 0; i < 8; i++) + mtrr_save->mtrr_fix_4k_xx000[i] = rdmsr(MTRR_FIX_4K_C0000 + i); /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Variable MTRRs */ - for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++) - write_mtrr(&nvram_pos, i); + for (i = 0; i < 8; i++) { + mtrr_save->mtrr_phys_mask[i] = rdmsr(MTRR_PHYS_BASE(i)); + mtrr_save->mtrr_phys_base[i] = rdmsr(MTRR_PHYS_BASE(i)); + } - /* SYSCFG_MSR */ - write_mtrr(&nvram_pos, SYSCFG_MSR); - /* TOM */ - write_mtrr(&nvram_pos, TOP_MEM); - /* TOM2 */ - write_mtrr(&nvram_pos, TOP_MEM2); + mtrr_save->syscfg = rdmsr(SYSCFG_MSR); + mtrr_save->top_mem = rdmsr(TOP_MEM); + mtrr_save->top_mem2 = rdmsr(TOP_MEM2); - *mtrr_store_size = nvram_pos - (u8*) mtrr_store; + *mtrr_store_size = sizeof(struct mtrr_backup); } void restore_mtrr(void) { - volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); - u32 msr; - msr_t msr_data; - - if (!msrPtr) - return; - - disable_cache(); + msr_t syscfg_msr; + struct mtrr_backup *mtrr_save = (struct mtrr_backup *)OemS3Saved_MTRR_Storage(); + uint32_t i; /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_64K_00000, msr_data); + wrmsr(MTRR_FIX_64K_00000, mtrr_save->mtrr_fix_64k_00000); + wrmsr(MTRR_FIX_16K_80000, mtrr_save->mtrr_fix_16k_80000); + wrmsr(MTRR_FIX_16K_A0000, mtrr_save->mtrr_fix_16k_a0000); - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_16K_80000, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_16K_A0000, msr_data); - - for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } + for (i = 0; i < 8; i++) + wrmsr(MTRR_FIX_4K_C0000 + i, mtrr_save->mtrr_fix_4k_xx000[i]); /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Restore the Variable MTRRs */ - for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); + for (i = 0; i < 8; i++) { + wrmsr(MTRR_PHYS_BASE(i), mtrr_save->mtrr_phys_mask[i]); + wrmsr(MTRR_PHYS_BASE(i), mtrr_save->mtrr_phys_base[i]); } - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYSCFG_MSR, msr_data); + wrmsr(SYSCFG_MSR, mtrr_save->syscfg); + wrmsr(TOP_MEM, mtrr_save->top_mem); + wrmsr(TOP_MEM2, mtrr_save->top_mem2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a Gerrit-Change-Number: 44293 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: mb/lenovo/t60: Add support for ThinkLight
by Stefan Ott (Code Review) 17 May '22

17 May '22

Stefan Ott has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40678 ) Change subject: mb/lenovo/t60: Add support for ThinkLight ...................................................................... mb/lenovo/t60: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T60 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T60 to test this. Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Signed-off-by: Stefan Ott <stefan(a)ott.net> --- M src/mainboard/lenovo/t60/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/40678/1 diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 51ff336..cab3ddb 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -48,4 +48,6 @@ // Dock support code #include "acpi/dock.asl" + + #include <ec/lenovo/h8/acpi/thinklight.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/40678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Gerrit-Change-Number: 40678 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Ott <coreboot(a)desire.ch> Gerrit-MessageType: newchange

9 33

Change in coreboot[master]: nb/intel/haswell: Add RMRR for USB devices
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 ) Change subject: nb/intel/haswell: Add RMRR for USB devices ...................................................................... nb/intel/haswell: Add RMRR for USB devices FIXME: Figure out which address the RMRR corresponds to. VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry. Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes. Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - return current; + return acpi_create_usb_rmrr(current); } unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Gerrit-Change-Number: 43807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/lenovo/{t420,t420s}: Convert to variant board
by Peter Lemenkov (Code Review) 03 May '22

03 May '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40381 ) Change subject: mb/lenovo/{t420,t420s}: Convert to variant board ...................................................................... mb/lenovo/{t420,t420s}: Convert to variant board Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/Kconfig.name M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420/board_info.txt M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420/gma-mainboard.ads M src/mainboard/lenovo/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/board_info.txt R src/mainboard/lenovo/t420/variants/t420/data.vbt A src/mainboard/lenovo/t420/variants/t420/early_init.c R src/mainboard/lenovo/t420/variants/t420/gpio.c A src/mainboard/lenovo/t420/variants/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/overridetree.cb R src/mainboard/lenovo/t420/variants/t420s/board_info.txt R src/mainboard/lenovo/t420/variants/t420s/data.vbt A src/mainboard/lenovo/t420/variants/t420s/early_init.c R src/mainboard/lenovo/t420/variants/t420s/gpio.c R src/mainboard/lenovo/t420/variants/t420s/hda_verb.c A src/mainboard/lenovo/t420/variants/t420s/overridetree.cb D src/mainboard/lenovo/t420s/Kconfig D src/mainboard/lenovo/t420s/Kconfig.name D src/mainboard/lenovo/t420s/Makefile.inc D src/mainboard/lenovo/t420s/acpi/ec.asl D src/mainboard/lenovo/t420s/acpi/platform.asl D src/mainboard/lenovo/t420s/acpi/superio.asl D src/mainboard/lenovo/t420s/acpi_tables.c D src/mainboard/lenovo/t420s/cmos.default D src/mainboard/lenovo/t420s/cmos.layout D src/mainboard/lenovo/t420s/devicetree.cb D src/mainboard/lenovo/t420s/dsdt.asl D src/mainboard/lenovo/t420s/early_init.c D src/mainboard/lenovo/t420s/gma-mainboard.ads D src/mainboard/lenovo/t420s/mainboard.c D src/mainboard/lenovo/t420s/smihandler.c D src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd D src/mainboard/lenovo/t420s/vboot-ro.fmd D src/mainboard/lenovo/t420s/vboot-rwa.fmd 38 files changed, 150 insertions(+), 853 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40381/1 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index dfc8ed1..b0523f6 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T420 +if BOARD_LENOVO_T420 || BOARD_LENOVO_T420S config BOARD_SPECIFIC_OPTIONS def_bool y @@ -16,7 +16,7 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select DRIVERS_RICOH_RCE822 + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T420 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT @@ -51,9 +51,19 @@ string default "lenovo/t420" +config VARIANT_DIR + string + default "t420" if BOARD_LENOVO_T420 + default "t420s" if BOARD_LENOVO_T420S + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T420" + default "ThinkPad T420" if BOARD_LENOVO_T420 + default "ThinkPad T420s" if BOARD_LENOVO_T420S config MAX_CPUS int @@ -81,4 +91,4 @@ config PS2M_EISAID default "LEN0015" -endif # BOARD_LENOVO_T420 +endif # BOARD_LENOVO_T420 || BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420/Kconfig.name b/src/mainboard/lenovo/t420/Kconfig.name index 75570ad..c43ec9d 100644 --- a/src/mainboard/lenovo/t420/Kconfig.name +++ b/src/mainboard/lenovo/t420/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T420 bool "ThinkPad T420" + +config BOARD_LENOVO_T420S + bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 05befdd..df5ca02 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -15,7 +15,9 @@ smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c - +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/board_info.txt b/src/mainboard/lenovo/t420/board_info.txt index c0f04ca..05146ff 100644 --- a/src/mainboard/lenovo/t420/board_info.txt +++ b/src/mainboard/lenovo/t420/board_info.txt @@ -1,3 +1,5 @@ +Vendor name: Lenovo +Board name: ThinkPad T420 baseboard Category: laptop ROM package: SOIC-8 / WSON-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..ec4a57a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -82,13 +82,7 @@ device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on - chip drivers/ricoh/rce822 - register "sdwppol" = "1" - register "disable_mask" = "0x87" - device pci 00.0 on end - end - end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 6c189f4..7a06bf0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -34,24 +34,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index a26b993..fae3544 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. with HW.GFX.GMA; diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 690c936..2997587 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,45 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ - 0x17aa21ce, /* Subsystem ID */ - 13, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21d2), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x00b707C0, /* Enable PortB as Output with HP amp */ - 0x00d70740, /* Enable PortD as Output */ - 0x0017a200, /* Disable ClkEn of PortSenseTst */ - 0x0017c621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017a208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/t420/variants/t420/board_info.txt b/src/mainboard/lenovo/t420/variants/t420/board_info.txt new file mode 100644 index 0000000..c0f04ca --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/t420/data.vbt b/src/mainboard/lenovo/t420/variants/t420/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420/data.vbt rename to src/mainboard/lenovo/t420/variants/t420/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420/early_init.c b/src/mainboard/lenovo/t420/variants/t420/early_init.c new file mode 100644 index 0000000..4b71060 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/early_init.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0: system port 4, OC0 */ + { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 0, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 1, 1, 4 }, /* P8: system port 3, OC4*/ + { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/variants/t420/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420/gpio.c rename to src/mainboard/lenovo/t420/variants/t420/gpio.c diff --git a/src/mainboard/lenovo/t420/variants/t420/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c new file mode 100644 index 0000000..690c936 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21d2), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t420/variants/t420/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb new file mode 100644 index 0000000..c0b503c --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.4 on + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on end + end + end # PCIe Port #5 (Ricoh SD & FW) + end + end +end diff --git a/src/mainboard/lenovo/t420s/board_info.txt b/src/mainboard/lenovo/t420/variants/t420s/board_info.txt similarity index 100% rename from src/mainboard/lenovo/t420s/board_info.txt rename to src/mainboard/lenovo/t420/variants/t420s/board_info.txt diff --git a/src/mainboard/lenovo/t420s/data.vbt b/src/mainboard/lenovo/t420/variants/t420s/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420s/data.vbt rename to src/mainboard/lenovo/t420/variants/t420s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420s/early_init.c b/src/mainboard/lenovo/t420/variants/t420s/early_init.c new file mode 100644 index 0000000..3066da5 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/early_init.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 0, 1, -1 }, /* P0: empty */ + { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 0, 1, -1 }, /* P8: empty (touch panel) */ + { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420/variants/t420s/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420s/gpio.c rename to src/mainboard/lenovo/t420/variants/t420s/gpio.c diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420s/hda_verb.c similarity index 100% rename from src/mainboard/lenovo/t420s/hda_verb.c rename to src/mainboard/lenovo/t420/variants/t420s/hda_verb.c diff --git a/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb new file mode 100644 index 0000000..e12d7ea --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x17aa 0x21d2 inherit + + device pci 02.0 on + subsystemid 0x17aa 0x21d3 + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + end + end +end diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig deleted file mode 100644 index e2fd824..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if BOARD_LENOVO_T420S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_BD82X6X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS - select DRIVERS_LENOVO_HYBRID_GRAPHICS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default "lenovo/t420s" - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad T420s" - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - -config VGA_BIOS_ID - string - default "8086,0126" - -config PS2K_EISAID - default "PNP0303" - -config PS2M_EISAID - default "LEN0015" - -endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420s/Kconfig.name b/src/mainboard/lenovo/t420s/Kconfig.name deleted file mode 100644 index 648688b..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_T420S - bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc deleted file mode 100644 index 05befdd..0000000 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -smm-y += smihandler.c -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl deleted file mode 100644 index 2dda5ec..0000000 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl deleted file mode 100644 index dc46182..0000000 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c deleted file mode 100644 index 65c6019..0000000 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <southbridge/intel/bd82x6x/nvs.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default deleted file mode 100644 index 467f965..0000000 --- a/src/mainboard/lenovo/t420s/cmos.default +++ /dev/null @@ -1,16 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -sata_mode=AHCI -fn_ctrl_swap=Disable -sticky_fn=Disable -trackpoint=Enable -hybrid_graphics_mode=Integrated Only -usb_always_on=Disable diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout deleted file mode 100644 index 26e6300..0000000 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ /dev/null @@ -1,141 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused - -440 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb deleted file mode 100644 index b3399c3..0000000 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ /dev/null @@ -1,175 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(1)" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "1" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21d2 inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d3 - end # Integrated Graphics Controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) - register "sata_port_map" = "0x17" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - # device specific SPI configuration - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "0" - - register "beepmask0" = "0x02" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf0" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x00" - register "event7_enable" = "0xa1" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x00" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl deleted file mode 100644 index a03b252..0000000 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c deleted file mode 100644 index 4f5f69d..0000000 --- a/src/mainboard/lenovo/t420s/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads deleted file mode 100644 index fae3544..0000000 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ /dev/null @@ -1,23 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later --- This file is part of the coreboot project. - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - LVDS, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c deleted file mode 100644 index 0890151..0000000 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c deleted file mode 100644 index 4432995..0000000 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmutil.h> - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd deleted file mode 100644 index d1cbff7..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x20000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME - } - SI_BIOS 0x7e0000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd deleted file mode 100644 index 51df8a5..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x500000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME 0x4ed000 - } - SI_BIOS 0x300000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd deleted file mode 100644 index 8a4cd3b..0000000 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ /dev/null @@ -1,29 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 - } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 - - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/40381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Gerrit-Change-Number: 40381 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/intel/soc: Remove save state handler code
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45477 ) Change subject: soc/intel/soc: Remove save state handler code ...................................................................... soc/intel/soc: Remove save state handler code Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 15 files changed, 54 insertions(+), 461 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45477/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index bcbc819..ddde65d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <intelblocks/smihandler.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -15,12 +14,7 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t100_smm_ops; -} - -const smi_handler_t southbridge_smi[32] = { +const void (*southbridge_smi[32])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 9348ae0..0372e81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <halt.h> @@ -152,41 +152,6 @@ } /* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -/* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are * in ACPI mode to PCI mode so that non-ACPI drivers may work. @@ -278,11 +243,10 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6f8cd62..b9ba4d8 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <soc/nvs.h> @@ -185,41 +185,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -258,11 +223,10 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index a223bf5..0ccdc5b 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -9,7 +9,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -231,46 +231,9 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -296,11 +259,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 266c258..4ba142e 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 7cea1dd..7ebd31c 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -10,41 +10,11 @@ struct global_nvs; /* - * The register value is used with get_reg and set_reg - */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, -}; - -struct smm_save_state_ops { - /* return io_misc_info from SMM Save State Area */ - uint32_t (*get_io_misc_info)(void *state); - - /* return value of the requested register from - * SMM Save State Area - */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); - - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); -}; - -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); - -/* - * SOC SMI Handler has to provide this structure which has methods to access - * the SOC specific SMM Save State Area - */ -const struct smm_save_state_ops *get_smm_save_state_ops(void); - -/* * southbridge_smi should be defined inside SOC specific code and should have * handlers for any SMI events that need to be handled. Default handlers * for some SMI events are provided in soc/intel/common/block/smm/smihandler.c */ -extern const smi_handler_t southbridge_smi[32]; +extern const void (*southbridge_smi[32])(void); #define SMI_HANDLER_SCI_EN(__bit) (1 << (__bit)) @@ -53,79 +23,69 @@ * the SMI event on SLP_EN. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_sleep(void); /* * This function should be implemented in SOC specific code to handle * SMI_APM event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_apmc(void); /* * This function should be implemented in SOC specific code to handle * SMI_PM1 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_pm1(void); /* * This function should be implemented in SOC specific code to handle * SMI_GPE0 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpe0(void); /* * This function should be implemented in SOC specific code to handle * MC event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_mc(void); /* * This function should be implemented in SOC specific code to handle * minitor event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_monitor(void); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_tco(void); /* * This function should be implemented in SOC specific code to handle * SMI PERIODIC_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_periodic(void); /* * This function should be implemented in SOC specific code to handle * SMI GPIO_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpi(void); /* * This function should be implemented in SOC specific code to handle * SMI ESPI_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_espi(void); /* SoC overrides. */ @@ -145,8 +105,4 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); - -extern const struct smm_save_state_ops em64t100_smm_ops; - -extern const struct smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index b629ef2..d1b9093 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -6,8 +6,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <delay.h> #include <device/pci_def.h> #include <elog.h> @@ -26,13 +25,6 @@ #include <spi-generic.h> #include <stdint.h> -/* SoC overrides. */ - -__weak const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - /* Specific SOC SMI handler during ramstage finalize phase */ __weak void smihandler_soc_at_finalize(void) { @@ -84,38 +76,6 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, - int cmd) -{ - int node; - void *state = NULL; - uint32_t io_misc_info; - uint8_t reg_al; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - io_misc_info = save_state_ops->get_io_misc_info(state); - - /* Check for Synchronous IO (bit0==1) */ - if (!(io_misc_info & (1 << 0))) - continue; - /* Make sure it was a write (bit4==0) */ - if (io_misc_info & (1 << 4)) - continue; - /* Check for APMC IO port */ - if (((io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); - if (reg_al != cmd) - continue; - break; - } - return state; -} - /* Inherited from cpu/x86/smm.h resulting in a different signature */ void southbridge_smi_set_eos(void) { @@ -170,8 +130,7 @@ } -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_sleep(void) { uint32_t reg32; uint8_t slp_typ; @@ -284,11 +243,9 @@ smihandler_soc_at_finalize(); } -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_apmc(void) { uint8_t reg8; - void *state = NULL; static int smm_initialized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -325,12 +282,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; @@ -350,8 +305,7 @@ mainboard_smi_apmc(reg8); } -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_pm1(void) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -368,14 +322,12 @@ } } -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpe0(void) { pmc_clear_all_gpe_status(); } -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_tco(void) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -399,8 +351,7 @@ } } -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_periodic(void) { uint32_t reg32; @@ -412,8 +363,7 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpi(void) { struct gpi_status smi_sts; @@ -424,8 +374,7 @@ gpi_clear_get_smi_status(&smi_sts); } -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_espi(void) { mainboard_smi_espi_handler(); } @@ -444,7 +393,6 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -463,15 +411,13 @@ if (!smi_sts) return; - save_state_ops = get_smm_save_state_ops(); - /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { if (!(smi_sts & (1 << i))) continue; if (southbridge_smi[i] != NULL) { - southbridge_smi[i](save_state_ops); + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " @@ -479,119 +425,3 @@ } } } - -static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state) -{ - em64t100_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t100_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t100_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state) -{ - em64t101_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t101_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t101_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -const struct smm_save_state_ops em64t100_smm_ops = { - .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, - .get_reg = em64t100_smm_save_state_get_reg, - .set_reg = em64t100_smm_save_state_set_reg, -}; - -const struct smm_save_state_ops em64t101_smm_ops = { - .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, - .get_reg = em64t101_smm_save_state_get_reg, - .set_reg = em64t101_smm_save_state_set_reg, -}; diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 99825f1..6900061 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -40,8 +40,7 @@ return 0; } -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -52,8 +51,7 @@ printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..397a6ec 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -146,42 +146,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void finalize(void) { static int finalize_done; @@ -237,14 +201,12 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } - break; } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index fbbbbdb..8ff0e6e 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 6d31adf..4246b27 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 177010c..5df890c 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -3,7 +3,7 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 40ed25e..a757cca 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index cb42832..bc4896a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -269,7 +269,6 @@ return; } int node = get_apmc_node(reg8); - if (node >= 0) { if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) smm_initialized = 1; diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 007b383..14f45da 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -7,7 +7,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <elog.h> #include <halt.h> #include <option.h> @@ -182,42 +182,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { u8 reg8; -- To view, visit https://review.coreboot.org/c/coreboot/+/45477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b Gerrit-Change-Number: 45477 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020