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Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only
by Patrick Rudolph (Code Review) 05 Nov '22

05 Nov '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40830 ) Change subject: [WIP]security/intel: Add option to eanble SMM flash access only ...................................................................... [WIP]security/intel: Add option to eanble SMM flash access only On platforms where the boot media can be updated externally, for e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps the SMMSTORE working for the use in payloads. UNTESTED. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 8 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40830/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index d24c5e5..dbe6840 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -99,3 +99,13 @@ possible. This option prevents using write protecting facilities in ramstage, like the MRC cache for example. Use this option if you don't trust code running after verstage. + +config BOOTMEDIA_SMM_BWP + bool "Boot media only writable in SMM" + depends on ARCH_X86 + depends on HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE if SOC_INTEL_COMMON_BLOCK + help + Enable flash writes in SMM only. Select this if you want to secure + the SMM_STORE and don't need to update coreboot using the + internal controller. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index a00e5c0..768c4cd 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -62,6 +62,12 @@ /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + /* BIOS Lock */ fast_spi_set_lock_enable(); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 278e90a..78bfb39 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -416,16 +416,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -579,8 +569,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 5e967af..253d33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,6 +35,10 @@ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) +#define BIOS_CNTL 0xdc +#define LPC_BC_WE (1 << 0) /* WE */ +#define LPC_BC_LE (1 << 1) /* LE */ +#define LPC_BC_EISS (1 << 5) /* EISS */ static int spi_is_multichip(void); @@ -293,7 +297,6 @@ void spi_init(void) { - uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; uint16_t hsfs; @@ -345,10 +348,7 @@ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + spi_smm_only_flashing(0); } } @@ -1108,12 +1108,35 @@ writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } writew_(optype, cntlr.optype); + + spi_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { } +void spi_smm_only_flashing(bool enable) +{ + pci_devfn_t dev = PCI_DEV(0, 31, 0); + u8 reg8 = pci_read_config8(dev, BIOS_CNTL); + + if (reg8 & LPC_BC_LE) + return; + + if (enable) { + reg8 |= LPC_BC_EISS; + reg8 &= ~LPC_BC_WE; + } else { + reg8 &= ~LPC_BC_EISS; + reg8 |= LPC_BC_WE; + } + pci_write_config8(dev, BIOS_CNTL, reg8); + + printk(BIOS_SPEW, "BIOS updates outside of SMM %s\n", + enable ? "enabled" : "disabled"); +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..ad1cb27 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,7 @@ struct intel_spi_op ops[8]; }; +void spi_smm_only_flashing(bool enable); void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 395919e..67c03fa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -420,16 +420,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { /* @@ -482,8 +472,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d9ef5cc..dafb901 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -481,16 +481,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -549,8 +539,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..82e96f3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -40,6 +40,8 @@ void smm_southbridge_enable_smi(void) { + u32 mask; + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ enable_pm1(PWRBTN_EN | GBL_EN); @@ -49,11 +51,14 @@ * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on TCO events * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + mask = APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS; + if (CONFIG(BOOTMEDIA_SMM_BWP)) + mask |= TCO_EN; + enable_smi(mask); } static void __unused southbridge_trigger_smi(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Gerrit-Change-Number: 40830 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 48

Change in coreboot[master]: mb/{lenovo,packardbell}: Enable MEI device
by Evgeny Zinoviev (Code Review) 02 Nov '22

02 Nov '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42412 ) Change subject: mb/{lenovo,packardbell}: Enable MEI device ...................................................................... mb/{lenovo,packardbell}: Enable MEI device Enable the MEI in device trees of some Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42412/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e608..9107f7c 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -51,7 +51,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d..fa63971 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -56,7 +56,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..795c372 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -69,7 +69,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c3..7a2f669 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706e..694f258 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea..b1a1131 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -68,7 +68,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da3..0c8fe79 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,7 +68,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f..b614e83 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -48,7 +48,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT -- To view, visit https://review.coreboot.org/c/coreboot/+/42412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Gerrit-Change-Number: 42412 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
by Arthur Heymans (Code Review) 27 Oct '22

27 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37321 ) Change subject: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB ...................................................................... cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37321/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index efb5fa9..335463d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -139,9 +139,9 @@ config SMM_LAPIC_REMAP_MITIGATION bool - default y if NORTHBRIDGE_INTEL_I945 - default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ + || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ + || NORTHBRIDGE_INTEL_E7505 default n config SERIALIZED_SMM_INITIALIZATION -- To view, visit https://review.coreboot.org/c/coreboot/+/37321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Gerrit-Change-Number: 37321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45278 ) Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps ...................................................................... WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps Use GPIOs mapping defined in APCB GET_SPD_FROM_GPIO to fetch correct SPD block from PSP BIOS table entry type 0x69 (BIOS_SPD_DATA). There is only one APCB now with no SPD data in it. No need for board ID getting method. This will save ROM space consumed by multiple APCB copies in the past. This is a working example of an implementation tested on Dalboz. It does not require patching with APCB_EDIT_TOOL. All SPDs are assembled in one type 0x69 blob and inserted into PSP BIOS directory. BUG=b:127505025 TEST=Dalboz with CABLRV20090300 and test CB and boot loader code BRANCH=Zork Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45278/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index eb2be50..e83e08d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ # # type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) +PSP_SPD_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/SPD_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -262,6 +262,12 @@ # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 +# SPD data array blob (with SPDs for all possible memory IDs for this platform) +SPD_BLOB:=$(obj)/SPD_array.bin + +# APCB binary without SPD data +APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ @@ -304,9 +310,8 @@ OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) -OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) +OPT_PSP_APCB_FILE=$(call add_opt_prefix, $(APCB_NO_SPD_BLOB), --instance 0 --apcb) +OPT_SPD_BLOB=$(call add_opt_prefix, $(SPD_BLOB), --spd-data-blob) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) @@ -341,7 +346,8 @@ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILE) \ + $(OPT_SPD_BLOB) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ @@ -383,6 +389,16 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +$(obj)/SPD_%.bin: $$(SPD_SOURCES_DIR)/%.hex + xxd -r -p $< > $@ + +$(SPD_BLOB): $$(PSP_SPD_FILES) + cat $+ > $@ + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -418,12 +434,22 @@ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ + $(PSP_APCB_FILE) \ + $(SPD_BLOB) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@ $(AMDFWTOOL) \ $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f385068..2192a04 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,6 +215,7 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("--spd-data-blob Add SPD array\n"); printf("-C | --soc-name <socname> Specify SOC name. Supported names are\n"); printf(" Stoneyridge, Raven, Picasso, Renoir or Lucienne"); printf("-h | --help show this help\n"); @@ -251,6 +252,7 @@ AMD_BIOS_PMUD = 0x65, AMD_BIOS_UCODE = 0x66, AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_SPD_DATA = 0x69, AMD_BIOS_MP2_CFG = 0x6a, AMD_BIOS_PSP_SHARED_MEM = 0x6b, AMD_BIOS_L2_PTR = 0x70, @@ -409,6 +411,7 @@ { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, + { .type = AMD_BIOS_SPD_DATA, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, @@ -1085,6 +1088,7 @@ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, LONGOPT_SPI_MICRON_FLAG = 258, + LONGOPT_SPD_DATA = 259, }; // Unused values: D @@ -1136,6 +1140,7 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + {"spd-data-blob", required_argument, 0, LONGOPT_SPD_DATA }, /* Embedded Firmware Structure items*/ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, @@ -1450,6 +1455,11 @@ instance, optarg); sub = instance = 0; break; + case LONGOPT_SPD_DATA: + /* optional SPD data array outside of APCB */ + register_bdt_data(AMD_BIOS_SPD_DATA, sub, instance, optarg); + sub = instance = 0; + break; case 'Q': /* APOB destination */ register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Gerrit-Change-Number: 45278 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: arch/x86: x86_64 implies SSE2 support
by Patrick Rudolph (Code Review) 24 Oct '22

24 Oct '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44869 ) Change subject: arch/x86: x86_64 implies SSE2 support ...................................................................... arch/x86: x86_64 implies SSE2 support Enable SSE2 when compiling for x86_64. Tested on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig M src/arch/x86/bootblock_crt0.S 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44869/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index d906436..d0e4693 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -33,22 +33,27 @@ config ARCH_BOOTBLOCK_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_VERSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_ROMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_POSTCAR_X86_64 bool default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE + select SSE2 config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 if ARCH_X86 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413..9e17b7e 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -52,9 +52,15 @@ #if CONFIG(SSE) enable_sse: +#if ENV_X86_32 mov %cr4, %eax or $CR4_OSFXSR, %ax mov %eax, %cr4 +#else + mov %cr4, %rax + or $CR4_OSFXSR, %ax + mov %rax, %cr4 +#endif #endif /* CONFIG(SSE) */ /* We're done. Now it's up to platform-specific code */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Gerrit-Change-Number: 44869 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: Kconfig: Allow x86 to compress pre-ram stages if not run XIP
by Arthur Heymans (Code Review) 21 Sep '22

21 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36613 ) Change subject: Kconfig: Allow x86 to compress pre-ram stages if not run XIP ...................................................................... Kconfig: Allow x86 to compress pre-ram stages if not run XIP Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36613/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..df86246 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -160,7 +160,7 @@ config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" - depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) + depends on HAVE_ROMSTAGE || HAVE_VERSTAGE # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash @@ -1217,7 +1217,7 @@ default y if !UNCOMPRESSED_RAMSTAGE config COMPRESS_PRERAM_STAGES - depends on !ARCH_X86 + depends on NO_XIP_EARLY_STAGES default y config INCLUDE_CONFIG_FILE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..db4f054 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -119,6 +119,7 @@ ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S +bootblock-y += memmove.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) -- To view, visit https://review.coreboot.org/c/coreboot/+/36613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Gerrit-Change-Number: 36613 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: cpu/intel/haswell: add Crystal Well CPU IDs
by Iru Cai (vimacs) (Code Review) 12 Sep '22

12 Sep '22

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44066 to review the following change. Change subject: cpu/intel/haswell: add Crystal Well CPU IDs ...................................................................... cpu/intel/haswell: add Crystal Well CPU IDs Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44066/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..5f3debb 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -778,6 +778,8 @@ { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Gerrit-Change-Number: 44066 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: device: Introduce RESOURCE_ALLOCATION_TOP_DOWN
by Nico Huber (Code Review) 07 Sep '22

07 Sep '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41957 ) Change subject: device: Introduce RESOURCE_ALLOCATION_TOP_DOWN ...................................................................... device: Introduce RESOURCE_ALLOCATION_TOP_DOWN Add option to resource allocators v4 and v4.5 that restores the top-down allocation approach at the domain level. Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/resource_allocator_v4.5.c M src/device/resource_allocator_v4.c M src/include/memrange.h M src/lib/memrange.c 5 files changed, 37 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41957/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index ee6fb21..35433b0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -821,4 +821,8 @@ endchoice +config RESOURCE_ALLOCATION_TOP_DOWN + bool "Allocate resources from top down" + depends on RESOURCE_ALLOCATOR_V4 || RESOURCE_ALLOCATOR_V4_5 + endmenu diff --git a/src/device/resource_allocator_v4.5.c b/src/device/resource_allocator_v4.5.c index 6b9e712..4a03a23 100644 --- a/src/device/resource_allocator_v4.5.c +++ b/src/device/resource_allocator_v4.5.c @@ -403,7 +403,8 @@ if (!res->size) continue; - if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base)) { + if (!memranges_steal(&ranges, res->limit, res->size, res->align, type, &base, + CONFIG(RESOURCE_ALLOCATION_TOP_DOWN))) { printk(BIOS_ERR, "ERROR: Resource didn't fit!!!\n"); print_failed_res(dev, res); continue; diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 3a11032..4e967f2 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -365,6 +365,9 @@ static void allocate_child_resources(struct bus *bus, struct memranges *ranges, unsigned long type_mask, unsigned long type_match) { + const bool allocate_top_down = + bus->dev->path.type == DEVICE_PATH_DOMAIN && + CONFIG(RESOURCE_ALLOCATION_TOP_DOWN); struct resource *resource = NULL; const struct device *dev; @@ -373,8 +376,9 @@ if (!resource->size) continue; - if (memranges_steal(ranges, resource->limit, resource->size, resource->align, - type_match, &resource->base) == false) { + if (memranges_steal(ranges, resource->limit, resource->size, + resource->align, type_match, &resource->base, + allocate_top_down)) == false) { printk(BIOS_ERR, " ERROR: Resource didn't fit!!! "); printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", dev_path(dev), resource->index, diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00e..d50a9c8 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -161,15 +161,17 @@ const struct range_entry *r); /* Steals memory from the available list in given ranges as per the constraints: - * limit = Upper bound for the memory range to steal (Inclusive). - * size = Requested size for the stolen memory. - * align = Required alignment(log 2) for the starting address of the stolen memory. - * tag = Use a range that matches the given tag. + * limit = Upper bound for the memory range to steal (Inclusive). + * size = Requested size for the stolen memory. + * align = Required alignment(log 2) for the starting address of the stolen memory. + * tag = Use a range that matches the given tag. + * from_top = Steal the highest possible range. * * If the constraints can be satisfied, this function creates a hole in the memrange, * writes the base address of that hole to stolen_base and returns true. Otherwise it returns * false. */ bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base); + unsigned char align, unsigned long tag, resource_t *stolen_base, + bool from_top); #endif /* MEMRANGE_H_ */ diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 39f502c..2f6d55c 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -378,11 +378,11 @@ /* Find a range entry that satisfies the given constraints to fit a hole that matches the * required alignment, is big enough, does not exceed the limit and has a matching tag. */ -static const struct range_entry *memranges_find_entry(struct memranges *ranges, - resource_t limit, resource_t size, - unsigned char align, unsigned long tag) +static const struct range_entry * +memranges_find_entry(struct memranges *ranges, resource_t limit, resource_t size, + unsigned char align, unsigned long tag, bool last) { - const struct range_entry *r; + const struct range_entry *r, *last_entry = NULL; resource_t base, end; if (size == 0) @@ -407,25 +407,30 @@ if (end > limit) break; - return r; + if (!last) + return r; + + last_entry = r; } - return NULL; + return last_entry; } bool memranges_steal(struct memranges *ranges, resource_t limit, resource_t size, - unsigned char align, unsigned long tag, resource_t *stolen_base) + unsigned char align, unsigned long tag, resource_t *stolen_base, + bool from_top) { - resource_t base; - const struct range_entry *r = memranges_find_entry(ranges, limit, size, align, tag); + const struct range_entry *r; + r = memranges_find_entry(ranges, limit, size, align, tag, from_top); if (r == NULL) return false; - base = ALIGN_UP(r->begin, POWER_OF_2(align)); - - memranges_create_hole(ranges, base, size); - *stolen_base = base; + if (from_top) + *stolen_base = ALIGN_DOWN(range_entry_end(r) - size, POWER_OF_2(align)); + else + *stolen_base = ALIGN_UP(r->begin, POWER_OF_2(align)); + memranges_create_hole(ranges, *stolen_base, size); return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4 Gerrit-Change-Number: 41957 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

8 11

Change in ...coreboot[master]: mb/lenovo/*/romstage: Use common hybrid_graphics_init
by Peter Lemenkov (Code Review) 02 Jun '22

02 Jun '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33807 Change subject: mb/lenovo/*/romstage: Use common hybrid_graphics_init ...................................................................... mb/lenovo/*/romstage: Use common hybrid_graphics_init Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h M src/drivers/lenovo/hybrid_graphics/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c 7 files changed, 30 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33807/1 diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h index b238440..2f7cce6 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -17,5 +17,6 @@ #define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); +void hybrid_graphics_init(void); #endif /* _DRIVERS_LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 35cb384..e4b27bb 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -24,6 +24,9 @@ #include "hybrid_graphics.h" #include "chip.h" +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> + /* * Returns the hybrid graphics presence and user's card preferences. */ @@ -94,3 +97,29 @@ " FIXME: dGPU power handling not implemented\n"); } } + +void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index ebf5aed..2f7ceb4 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 49de58d..2eed168 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 1f4b90d..98ff418 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5c23b8e..c23b896 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 67cf97c..1b76def 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Gerrit-Change-Number: 33807 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: configs: add Lenovo G505S sample configuration (use with dGPU patches)
by mikeb mikeb (Code Review) 02 Jun '22

02 Jun '22

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32352 to review the following change. Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches) ...................................................................... configs: add Lenovo G505S sample configuration (use with dGPU patches) This sample .config could not be merged before the dGPU patches at CB:31929 (see https://review.coreboot.org/c/coreboot/+/31929 for more information). I'm sharing it with you here partially for the archival purposes. After you have installed the dGPU patches above, you can use this .config as the base configuration for your G505S by saving it to ./coreboot/.config - however, you may want to change some of its' configs! For example: it specifies CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" CONFIG_VGA_BIOS_DGPU_ID="1002,6665" which is compatible with R5-M230 discrete GPU, but if your G505S has HD-8570M discrete GPU instead - you will need to change these configs to ",6663" etc. Or, if your G505S does not have a discrete GPU at all, please disable CONFIG_MULTIPLE_VGA_ADAPTERS=y and those DGPU configs will be disabled. Also, if you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I've disabled this WiFi adapter at my .config to save some space: If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 --- A configs/config.lenovo_g505s_use_with_dgpu_patches 1 file changed, 746 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32352/1 diff --git a/configs/config.lenovo_g505s_use_with_dgpu_patches b/configs/config.lenovo_g505s_use_with_dgpu_patches new file mode 100644 index 0000000..5ff218f --- /dev/null +++ b/configs/config.lenovo_g505s_use_with_dgpu_patches @@ -0,0 +1,746 @@ +# +# ./coreboot/.config for Lenovo G505S - 17 April 2019 +# +### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/g505s" +CONFIG_MAINBOARD_PART_NUMBER="LENOVO G505S" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x400000 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_VGA_BIOS_ID="1002,990b" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="pci1002,990b.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_POST_DEVICE=y +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="LENOVO G505S" +CONFIG_BOARD_LENOVO_G505S=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T520 is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T530 is not set +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_COMPAL_ENE932=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_HAS_MULTIPLE_VGA_ADAPTERS=y +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y +CONFIG_MULTIPLE_VGA_ADAPTERS=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_VGA_BIOS_DGPU=y +CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" +CONFIG_VGA_BIOS_DGPU_ID="1002,6665" +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/32352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 Gerrit-Change-Number: 32352 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020