coreboot-gerrit September 2020

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Change in coreboot[master]: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199
by Michael Niewöhner (Code Review) 20 Sep '20

20 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45561 ) Change subject: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199 ...................................................................... Patch Set 1: Code-Review-2 just a test -- To view, visit https://review.coreboot.org/c/coreboot/+/45561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3169ffcc44b24ab3844d9f34545dbcb525fbbd5 Gerrit-Change-Number: 45561 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 20 Sep 2020 13:59:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199
by Michael Niewöhner (Code Review) 20 Sep '20

20 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45561 ) Change subject: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199 ...................................................................... Patch Set 1: Well... at least intel/harcuvar should have failed but it wasn't even built o.O coreboot-builds/INTEL_HARCUVAR/generated/ramstage.o:(.data.device_ops+0x34): undefined reference to `southcluster_inject_dsdt -- To view, visit https://review.coreboot.org/c/coreboot/+/45561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3169ffcc44b24ab3844d9f34545dbcb525fbbd5 Gerrit-Change-Number: 45561 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 20 Sep 2020 13:58:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199
by Michael Niewöhner (Code Review) 20 Sep '20

20 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45561 ) Change subject: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199 ...................................................................... Patch Set 1: let's run the buildbot -- To view, visit https://review.coreboot.org/c/coreboot/+/45561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3169ffcc44b24ab3844d9f34545dbcb525fbbd5 Gerrit-Change-Number: 45561 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 20 Sep 2020 12:54:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: trival: Fix typo of Kconfig setting
by Bao Zheng (Code Review) 20 Sep '20

20 Sep '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45285 to review the following change. Change subject: trival: Fix typo of Kconfig setting ...................................................................... trival: Fix typo of Kconfig setting Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/45285/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..0e2db5f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -429,7 +429,7 @@ string default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" -config USE_PSPSCUREOS +config USE_PSPSECUREOS bool default y help diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index bbb064f..8eda2d8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -147,7 +147,7 @@ PSP_TOKEN_UNLOCK="--token-unlock" endif -ifeq ($(CONFIG_USE_PSPSCUREOS),y) +ifeq ($(CONFIG_USE_PSPSECUREOS),y) # types = 0x2 PSPSCUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1 Gerrit-Change-Number: 45285 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/{haswell,ironlake,pineview,sandybridge,x4x}: Refactor MCHBAR...
by HAOUAS Elyes (Code Review) 19 Sep '20

19 Sep '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45487 ) Change subject: nb/intel/{haswell,ironlake,pineview,sandybridge,x4x}: Refactor MCHBARx_AND_OR ...................................................................... nb/intel/{haswell,ironlake,pineview,sandybridge,x4x}: Refactor MCHBARx_AND_OR Add MCHBAR_AND_OR macro and refactor MCHBARx_AND_OR, MCHBARx_AND and MCHBARx_OR macros. Change-Id: Ica23f58ffd79b17d4d68bd7a34a719691d654525 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 5 files changed, 91 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45487/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 9a99c2a..fe37fb7 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -41,18 +41,24 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +#define MCHBAR_AND_OR(bits, x, and, or) \ + (MCHBAR##bits(x) = ((MCHBAR##bits(x) & (and)) | (or))) + +#define MCHBAR8_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR16_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR32_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) + +#define MCHBAR8_OR(x, or) MCHBAR_AND_OR(8, x, ~0UL, or) +#define MCHBAR16_OR(x, or) MCHBAR_AND_OR(16, x, ~0UL, or) +#define MCHBAR32_OR(x, or) MCHBAR_AND_OR(32, x, ~0UL, or) + +#define MCHBAR8_AND_OR(x, and, or) MCHBAR_AND_OR(8, x, and, or) +#define MCHBAR16_AND_OR(x, and, or) MCHBAR_AND_OR(16, x, and, or) +#define MCHBAR32_AND_OR(x, and, or) MCHBAR_AND_OR(32, x, and, or) /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 325de5b..9d11edd 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -103,18 +103,25 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +#define MCHBAR_AND_OR(bits, x, and, or) \ + (MCHBAR##bits(x) = ((MCHBAR##bits(x) & (and)) | (or))) + +#define MCHBAR8_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR16_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR32_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) + +#define MCHBAR8_OR(x, or) MCHBAR_AND_OR(8, x, ~0UL, or) +#define MCHBAR16_OR(x, or) MCHBAR_AND_OR(16, x, ~0UL, or) +#define MCHBAR32_OR(x, or) MCHBAR_AND_OR(32, x, ~0UL, or) + +#define MCHBAR8_AND_OR(x, and, or) MCHBAR_AND_OR(8, x, and, or) +#define MCHBAR16_AND_OR(x, and, or) MCHBAR_AND_OR(16, x, and, or) +#define MCHBAR32_AND_OR(x, and, or) MCHBAR_AND_OR(32, x, and, or) + /* * EPBAR - Egress Port Root Complex Register Block */ diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 47257dd..c565d0d 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -38,18 +38,24 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +#define MCHBAR_AND_OR(bits, x, and, or) \ + (MCHBAR##bits(x) = ((MCHBAR##bits(x) & (and)) | (or))) + +#define MCHBAR8_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR16_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR32_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) + +#define MCHBAR8_OR(x, or) MCHBAR_AND_OR(8, x, ~0UL, or) +#define MCHBAR16_OR(x, or) MCHBAR_AND_OR(16, x, ~0UL, or) +#define MCHBAR32_OR(x, or) MCHBAR_AND_OR(32, x, ~0UL, or) + +#define MCHBAR8_AND_OR(x, and, or) MCHBAR_AND_OR(8, x, and, or) +#define MCHBAR16_AND_OR(x, and, or) MCHBAR_AND_OR(16, x, and, or) +#define MCHBAR32_AND_OR(x, and, or) MCHBAR_AND_OR(32, x, and, or) /* As there are many registers, define them on a separate file */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 72724a3..5afba72 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -64,18 +64,24 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +#define MCHBAR_AND_OR(bits, x, and, or) \ + (MCHBAR##bits(x) = ((MCHBAR##bits(x) & (and)) | (or))) + +#define MCHBAR8_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR16_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR32_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) + +#define MCHBAR8_OR(x, or) MCHBAR_AND_OR(8, x, ~0UL, or) +#define MCHBAR16_OR(x, or) MCHBAR_AND_OR(16, x, ~0UL, or) +#define MCHBAR32_OR(x, or) MCHBAR_AND_OR(32, x, ~0UL, or) + +#define MCHBAR8_AND_OR(x, and, or) MCHBAR_AND_OR(8, x, and, or) +#define MCHBAR16_AND_OR(x, and, or) MCHBAR_AND_OR(16, x, and, or) +#define MCHBAR32_AND_OR(x, and, or) MCHBAR_AND_OR(32, x, and, or) /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 45785a0..d2a6fdc 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -40,21 +40,24 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) \ - (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR16_AND_OR(x, and, or) \ - (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR32_AND_OR(x, and, or) \ - (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +#define MCHBAR_AND_OR(bits, x, and, or) \ + (MCHBAR##bits(x) = ((MCHBAR##bits(x) & (and)) | (or))) + +#define MCHBAR8_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR16_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) +#define MCHBAR32_AND(x, and) MCHBAR_AND_OR(8, x, and, 0) + +#define MCHBAR8_OR(x, or) MCHBAR_AND_OR(8, x, ~0UL, or) +#define MCHBAR16_OR(x, or) MCHBAR_AND_OR(16, x, ~0UL, or) +#define MCHBAR32_OR(x, or) MCHBAR_AND_OR(32, x, ~0UL, or) + +#define MCHBAR8_AND_OR(x, and, or) MCHBAR_AND_OR(8, x, and, or) +#define MCHBAR16_AND_OR(x, and, or) MCHBAR_AND_OR(16, x, and, or) +#define MCHBAR32_AND_OR(x, and, or) MCHBAR_AND_OR(32, x, and, or) #define CHDECMISC 0x111 #define STACKED_MEM (1 << 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/45487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica23f58ffd79b17d4d68bd7a34a719691d654525 Gerrit-Change-Number: 45487 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/up/squared: move subsystem id from Kconfig to devicetree
by 9elements QA (Code Review) 19 Sep '20

19 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45527 ) Change subject: mb/up/squared: move subsystem id from Kconfig to devicetree ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20068 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20067 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20066 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20065 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20064 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20072 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20071 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20070 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20069 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/45527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf62a73ee568d9369c53bd767bd4cfb736ea76f1 Gerrit-Change-Number: 45527 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Sep 2020 18:09:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable ACPI Continuous Performance Control
by Jonathan Zhang (Code Review) 19 Sep '20

19 Sep '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45426 ) Change subject: soc/intel/xeon_sp/cpx: Enable ACPI Continuous Performance Control ...................................................................... Patch Set 3: How is this tested? What's the expected impact? -- To view, visit https://review.coreboot.org/c/coreboot/+/45426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612598a5189375f335315933b590e1f7d24b2944 Gerrit-Change-Number: 45426 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Sep 2020 17:49:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: move subsystem id from Kconfig to devicetree
by 9elements QA (Code Review) 19 Sep '20

19 Sep '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45528 ) Change subject: mb/system76/lemp9: move subsystem id from Kconfig to devicetree ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20059 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20058 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20057 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20056 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20055 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20063 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20062 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20061 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20060 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/45528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52 Gerrit-Change-Number: 45528 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 19 Sep 2020 17:33:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 19 Sep '20

19 Sep '20

Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45536 to look at the new patch set (#5). Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries ...................................................................... soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries Make use of the previously added common function for generating CPPC entries, when Intel SpeedShift is enabled. Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 6 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Michael Niewöhner (Code Review) 19 Sep '20

19 Sep '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/3/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/3/src/soc/intel/common/block… PS3, Line 367: cores_per_package > Unused param? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Sat, 19 Sep 2020 17:24:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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