Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45561 )
Change subject: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199
......................................................................
Patch Set 1:
Well... at least intel/harcuvar should have failed but it wasn't even built o.O
coreboot-builds/INTEL_HARCUVAR/generated/ramstage.o:(.data.device_ops+0x34): undefined reference to `southcluster_inject_dsdt
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45561 )
Change subject: [WIP|TEST] add missing soc_chip headers to fix build of CB:42199
......................................................................
Patch Set 1:
let's run the buildbot
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45527 )
Change subject: mb/up/squared: move subsystem id from Kconfig to devicetree
......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9
"QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20068
"QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20067
"QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20066
"QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20065
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20064
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20072
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20071
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20070
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20069
Please note: This test is under development and might not be accurate at all!
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45426 )
Change subject: soc/intel/xeon_sp/cpx: Enable ACPI Continuous Performance Control
......................................................................
Patch Set 3:
How is this tested? What's the expected impact?
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45528 )
Change subject: mb/system76/lemp9: move subsystem id from Kconfig to devicetree
......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9
"QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20059
"QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20058
"QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20057
"QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20056
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20055
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20063
"HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20062
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20061
"HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20060
Please note: This test is under development and might not be accurate at all!
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Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Kyösti Mälkki, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45536
to look at the new patch set (#5).
Change subject: soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
......................................................................
soc/intel/{cnl,icl,jsl,tgl}/acpi: generate CPPC entries
Make use of the previously added common function for generating CPPC
entries, when Intel SpeedShift is enabled.
Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/acpi.c
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/tigerlake/acpi.c
6 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/5
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Gerrit-MessageType: newpatchset
Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Kyösti Mälkki, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45535
to look at the new patch set (#4).
Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation
......................................................................
soc/intel/common/block/acpi: add code for CPPC entries generation
This adds the code for CPPC entries generation, needed for Intel
SpeedShift, to common acpi code. The function will be called from the
SoCs' acpi code in the follow-up change.
Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/4
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