coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Patrick Georgi (Code Review) 21 Sep '20

21 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... mb/intel/tglrvp: Enable HECI interface This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface is required between kernel and CSE Lite. BUG=None TEST=Build and boot tglrvp. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4390b0..a2d297d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -12,6 +12,9 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci1 communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a5cae1..c381d2e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -12,6 +12,9 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci1 communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 11 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/intel/mipi_camera: Avoid resource leak
by John Zhao (Code Review) 21 Sep '20

21 Sep '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45531 ) Change subject: drivers/intel/mipi_camera: Avoid resource leak ...................................................................... drivers/intel/mipi_camera: Avoid resource leak Coverity detects variable dsd going out of scope leaks the storage it points to. Move dsd resource allocation after sanity check for config->nvm_compact to avoid leak. Found-by: Coverity CID 1432727 TEST=Built and boot up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I86af322dc78845b8b312b6815135336c2c56b4dd --- M src/drivers/intel/mipi_camera/camera.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/45531/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index fed0ff6..d4cf33d 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -452,11 +452,13 @@ static void camera_fill_nvm(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + struct acpi_dp *dsd; if (!config->nvm_compat) return; + dsd = acpi_dp_new_table("_DSD"); + /* It might be possible to default size or width based on type. */ if (!config->disable_nvm_defaults && !config->nvm_pagesize) config->nvm_pagesize = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/45531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86af322dc78845b8b312b6815135336c2c56b4dd Gerrit-Change-Number: 45531 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: cpu/x86/smm.h: Add function to return the SMM revision
by Arthur Heymans (Code Review) 21 Sep '20

21 Sep '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44318 ) Change subject: cpu/x86/smm.h: Add function to return the SMM revision ...................................................................... cpu/x86/smm.h: Add function to return the SMM revision Change-Id: I3e4450088adbb654050e7420956cf58ee1170a98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 3 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44318/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 8fd95bb..8f7ebfb 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -120,6 +120,14 @@ return (void *)base; } +/* This returns the SMM revision from the savestate of CPU0, + which is assumed to be the same for all CPU's. See the memory + map in smmhandler.S */ +uint32_t smm_revision(void) +{ + return *(uint32_t *)(SMM_BASE + SMM_ENTRY_OFFSET * 2 - SMM_REVISION_OFFSET_FROM_TOP); +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {SMM_BASE, SMM_DEFAULT_SIZE}; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 02682b4..e50061d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -106,6 +106,13 @@ return base; } +uint32_t smm_revision(void) +{ + const uintptr_t save_state = (uintptr_t)(smm_get_save_state(0)); + + return *(uint32_t *)(save_state + smm_runtime->save_state_size - SMM_REVISION_OFFSET_FROM_TOP); +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {smm_runtime->smbase, smm_runtime->smm_size}; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a3101e5..ff91c96 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -175,4 +175,9 @@ /* Print the SMM memory layout on console. */ void smm_list_regions(void); +#define SMM_REVISION_OFFSET_FROM_TOP (0x8000 - 0x7efc) +/* Return the SMM revision. The revision is can be fetched from the smm savestate + which is always at the same offset downward from the top of the save state. */ +uint32_t smm_revision(void); + #endif /* CPU_X86_SMM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4450088adbb654050e7420956cf58ee1170a98 Gerrit-Change-Number: 44318 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/51nb/x210/gpio: 2/4 Exclude fields for PAD_CFG
by Maxim Polyakov (Code Review) 21 Sep '20

21 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43567 ) Change subject: mb/51nb/x210/gpio: 2/4 Exclude fields for PAD_CFG ...................................................................... mb/51nb/x210/gpio: 2/4 Exclude fields for PAD_CFG This patch excludes bit fields that must be ignored (1,2) in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -adv -ign -t 1 -file ../../src/mainboard/51nb/x210/gpio.h (1) ignore RO and reserved bit fields; (2) ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer Disable (bit 9:8) for the native function, because it does not affect the pad in this mode. This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": - 1/4 Decode raw register values - 2/4 Exclude fields for PAD_CFG - 3/4 Fixes PAD_RESET to convert to PAD_NC() - 4/4 Convert field macros to PAD_CFG Change-Id: Id0196b20783126c36f8552534b7ec3bd9049a24f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 140 insertions(+), 140 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43567/1 diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index 9df4769..36760bf 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -10,170 +10,170 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), /* GPIO */_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), /* GPIO */_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), /* GPIO */_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), /* GPIO */_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PD)), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), /* GPIO */_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1), 0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(NF1), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), /* GPIO */_PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), /* GPIO */_PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1), PAD_PULL(20K_PU)), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1), 0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1), PAD_PULL(NATIVE)), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1), PAD_PULL(20K_PU)), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1), 0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1), 0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1), 0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1), 0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1), 0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1), 0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0196b20783126c36f8552534b7ec3bd9049a24f Gerrit-Change-Number: 43567 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: security/tpm/tss/tcg-2.0: add const to marshalling functions
by Patrick Georgi (Code Review) 21 Sep '20

21 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45409 ) Change subject: security/tpm/tss/tcg-2.0: add const to marshalling functions ...................................................................... security/tpm/tss/tcg-2.0: add const to marshalling functions This adds the const qualifier to inputs of marshalling functions as they are intended to be read-only. Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45409 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.h 2 files changed, 30 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f31c7d0..3efd5ad 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -18,18 +18,18 @@ #define marshal_TPM_HANDLE(a, b) obuf_write_be32(a, b) #define marshal_TPMI_ALG_HASH(a, b) obuf_write_be16(a, b) -static int marshal_startup(struct obuf *ob, struct tpm2_startup *cmd_body) +static int marshal_startup(struct obuf *ob, const struct tpm2_startup *cmd_body) { return obuf_write_be16(ob, cmd_body->startup_type); } -static int marshal_shutdown(struct obuf *ob, struct tpm2_shutdown *cmd_body) +static int marshal_shutdown(struct obuf *ob, const struct tpm2_shutdown *cmd_body) { return obuf_write_be16(ob, cmd_body->shutdown_type); } static int marshal_get_capability(struct obuf *ob, - struct tpm2_get_capability *cmd_body) + const struct tpm2_get_capability *cmd_body) { int rc = 0; @@ -40,7 +40,7 @@ return rc; } -static int marshal_TPM2B(struct obuf *ob, TPM2B *data) +static int marshal_TPM2B(struct obuf *ob, const TPM2B *data) { int rc = 0; @@ -50,7 +50,7 @@ return rc; } -static int marshal_TPMA_NV(struct obuf *ob, TPMA_NV *nv) +static int marshal_TPMA_NV(struct obuf *ob, const TPMA_NV *nv) { uint32_t v; @@ -58,7 +58,7 @@ return obuf_write_be32(ob, v); } -static int marshal_TPMS_NV_PUBLIC(struct obuf *ob, TPMS_NV_PUBLIC *nvpub) +static int marshal_TPMS_NV_PUBLIC(struct obuf *ob, const TPMS_NV_PUBLIC *nvpub) { int rc = 0; @@ -71,7 +71,7 @@ return rc; } -static int marshal_TPMT_HA(struct obuf *ob, TPMT_HA *tpmtha) +static int marshal_TPMT_HA(struct obuf *ob, const TPMT_HA *tpmtha) { int rc = 0; @@ -104,7 +104,7 @@ } static int marshal_TPML_DIGEST_VALUES(struct obuf *ob, - TPML_DIGEST_VALUES *dvalues) + const TPML_DIGEST_VALUES *dvalues) { int i; int rc = 0; @@ -117,7 +117,7 @@ } static int marshal_session_header(struct obuf *ob, - struct tpm2_session_header *session_header) + const struct tpm2_session_header *session_header) { int rc = 0; struct obuf ob_sz; @@ -151,8 +151,8 @@ * session_header structure. */ static int marshal_common_session_header(struct obuf *ob, - const uint32_t *handles, - size_t handle_count) + const uint32_t *handles, + size_t handle_count) { size_t i; struct tpm2_session_header session_header; @@ -171,7 +171,7 @@ } static int marshal_nv_define_space(struct obuf *ob, - struct tpm2_nv_define_space_cmd *nvd_in) + const struct tpm2_nv_define_space_cmd *nvd_in) { const uint32_t handle[] = { TPM_RH_PLATFORM }; struct obuf ob_sz; @@ -198,10 +198,10 @@ } static int marshal_nv_write(struct obuf *ob, - struct tpm2_nv_write_cmd *command_body) + const struct tpm2_nv_write_cmd *command_body) { int rc = 0; - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= marshal_TPM2B(ob, &command_body->data.b); @@ -211,18 +211,18 @@ } static int marshal_nv_write_lock(struct obuf *ob, - struct tpm2_nv_write_lock_cmd *command_body) + const struct tpm2_nv_write_lock_cmd *command_body) { - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; return marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); } static int marshal_pcr_extend(struct obuf *ob, - struct tpm2_pcr_extend_cmd *command_body) + const struct tpm2_pcr_extend_cmd *command_body) { int rc = 0; - uint32_t handles[] = { command_body->pcrHandle }; + const uint32_t handles[] = { command_body->pcrHandle }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= marshal_TPML_DIGEST_VALUES(ob, &command_body->digests); @@ -231,10 +231,10 @@ } static int marshal_nv_read(struct obuf *ob, - struct tpm2_nv_read_cmd *command_body) + const struct tpm2_nv_read_cmd *command_body) { int rc = 0; - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= obuf_write_be16(ob, command_body->size); @@ -252,13 +252,13 @@ } static int marshal_selftest(struct obuf *ob, - struct tpm2_self_test *command_body) + const struct tpm2_self_test *command_body) { return obuf_write_be8(ob, command_body->yes_no); } static int marshal_hierarchy_control(struct obuf *ob, - struct tpm2_hierarchy_control_cmd *command_body) + const struct tpm2_hierarchy_control_cmd *command_body) { int rc = 0; struct tpm2_session_header session_header; @@ -277,7 +277,7 @@ } static int marshal_clear_control(struct obuf *ob, - struct tpm2_clear_control_cmd *command_body) + const struct tpm2_clear_control_cmd *command_body) { int rc = 0; struct tpm2_session_header session_header; @@ -294,10 +294,10 @@ return rc; } -static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body) +static int marshal_cr50_vendor_command(struct obuf *ob, const void *command_body) { int rc = 0; - uint16_t *sub_command = command_body; + const uint16_t *sub_command = command_body; switch (*sub_command) { case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET: @@ -343,7 +343,7 @@ return rc; } -int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) +int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obuf *ob) { struct obuf ob_hdr; const size_t hdr_sz = sizeof(uint16_t) + 2 * sizeof(uint32_t); @@ -432,7 +432,7 @@ } static int unmarshal_get_capability(struct ibuf *ib, - struct get_cap_response *gcr) + struct get_cap_response *gcr) { int i; int rc = 0; @@ -491,7 +491,7 @@ } static int unmarshal_TPM2B_MAX_NV_BUFFER(struct ibuf *ib, - TPM2B_MAX_NV_BUFFER *nv_buffer) + TPM2B_MAX_NV_BUFFER *nv_buffer) { if (ibuf_read_be16(ib, &nv_buffer->t.size)) return -1; @@ -542,7 +542,7 @@ } static int unmarshal_vendor_command(struct ibuf *ib, - struct vendor_command_response *vcr) + struct vendor_command_response *vcr) { if (ibuf_read_be16(ib, &vcr->vc_subcommand)) return -1; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index 432cf5a3..ae0b7fd 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -21,7 +21,7 @@ * Returns 0 on success or -1 on error. * */ -int tpm_marshal_command(TPM_CC command, void *tpm_command_body, +int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obuf *ob); /** -- To view, visit https://review.coreboot.org/c/coreboot/+/45409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099bf46c928733aff2c1d1c134deec35da6309ba Gerrit-Change-Number: 45409 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/intelp2m: Check keywords in common code
by Maxim Polyakov (Code Review) 21 Sep '20

21 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45167 ) Change subject: util/intelp2m: Check keywords in common code ...................................................................... util/intelp2m: Check keywords in common code TEST = ./intelp2m -n -file inteltool.log; ./intelp2m -fld cb -file inteltool.log; ./intelp2m -fld fsp -file inteltool.log; ./intelp2m -fld raw -file inteltool.log. Before and after the patch, gpio.h is no different. Change-Id: I8af28960e41fcb97f03fe97c42cdddde07b3615a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/parser/parser.go M util/intelp2m/platforms/apl/template.go M util/intelp2m/platforms/cnl/template.go A util/intelp2m/platforms/common/template.go M util/intelp2m/platforms/snr/template.go 5 files changed, 33 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45167/1 diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index 8a58ab7..d4c04cd 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -7,6 +7,7 @@ "strconv" ) +import "../platforms/common" import "../platforms/snr" import "../platforms/lbg" import "../platforms/apl" @@ -224,7 +225,8 @@ scanner := bufio.NewScanner(config.InputRegDumpFile) for scanner.Scan() { parser.line = scanner.Text() - if strings.Contains(parser.line, "GPIO Community") || strings.Contains(parser.line, "GPIO Group") { + isIncluded, _ := common.KeywordsCheck(parser.line, "GPIO Community", "GPIO Group"); + if isIncluded { parser.communityGroupExtract() } else if !parser.padConfigurationExtract() && parser.platform.KeywordCheck(parser.line) { if parser.padInfoExtract() != 0 { diff --git a/util/intelp2m/platforms/apl/template.go b/util/intelp2m/platforms/apl/template.go index 5944727..823b321 100644 --- a/util/intelp2m/platforms/apl/template.go +++ b/util/intelp2m/platforms/apl/template.go @@ -1,6 +1,6 @@ package apl -import "strings" +import "../common" // GroupNameExtract - This function extracts the group ID, if it exists in a row // line : string from the configuration file @@ -16,7 +16,7 @@ // returns true if the keyword is contained in the line. // line : string from the configuration file func (PlatformSpecific) KeywordCheck(line string) bool { - for _, keyword := range []string{ + isIncluded, _ := common.KeywordsCheck(line, "GPIO_", "TCK", "TRST_B", "TMS", "TDI", "CX_PMODE", "CX_PREQ_B", "JTAGX", "CX_PRDY_B", "TDO", "CNV_BRI_DT", "CNV_BRI_RSP", "CNV_RGI_DT", "CNV_RGI_RSP", "SVID0_ALERT_B", "SVID0_DATA", "SVID0_CLK", "PMC_SPI_FS", "PMC_SPI_RXD", "PMC_SPI_TXD", "PMC_SPI_CLK", @@ -25,11 +25,6 @@ "PMU_BATLOW_B", "PMU_PLTRST_B", "PMU_PWRBTN_B", "PMU_RESETBUTTON_B", "PMU_SLP_S0_B", "PMU_SLP_S3_B", "PMU_SLP_S4_B", "PMU_SUSCLK", "PMU_WAKE_B", "SUS_STAT_B", "SUSPWRDNACK", "SMB_ALERTB", "SMB_CLK", "SMB_DATA", "LPC_ILB_SERIRQ", "LPC_CLKOUT", "LPC_AD", "LPC_CLKRUNB", - "LPC_FRAMEB", - } { - if strings.Contains(line, keyword) { - return true - } - } - return false + "LPC_FRAMEB") + return isIncluded } diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go index f1a1741..3b028e6 100644 --- a/util/intelp2m/platforms/cnl/template.go +++ b/util/intelp2m/platforms/cnl/template.go @@ -1,9 +1,8 @@ package cnl -import "strings" +import "../common" type InheritanceTemplate interface { - KeywordCheck(line string) bool } @@ -13,16 +12,8 @@ // bool : true if the string contains a group identifier // string : group identifier func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { - for _, groupKeyword := range []string{ - "GPP_A", "GPP_B", "GPP_G", - "GPP_D", "GPP_F", "GPP_H", - "GPD", "GPP_C", "GPP_E", - } { - if strings.Contains(line, groupKeyword) { - return true, groupKeyword - } - } - return false, "" + return common.KeywordsCheck(line, + "GPP_A", "GPP_B", "GPP_G", "GPP_D", "GPP_F", "GPP_H", "GPD", "GPP_C", "GPP_E") } // KeywordCheck - This function is used to filter parsed lines of the configuration file and diff --git a/util/intelp2m/platforms/common/template.go b/util/intelp2m/platforms/common/template.go new file mode 100644 index 0000000..296f169 --- /dev/null +++ b/util/intelp2m/platforms/common/template.go @@ -0,0 +1,15 @@ +package common + +import "strings" + +// KeywordsCheck - check if one of the keyword from the <keywords> group is included in the +// <line> string. Returns false if no word was found, or true otherwise and also this word +// itself +func KeywordsCheck(line string, keywords ...string) (bool, string) { + for _, key := range keywords { + if strings.Contains(line, key) { + return true, key + } + } + return false, "" +} diff --git a/util/intelp2m/platforms/snr/template.go b/util/intelp2m/platforms/snr/template.go index c6c39b1..9bcf9e1 100644 --- a/util/intelp2m/platforms/snr/template.go +++ b/util/intelp2m/platforms/snr/template.go @@ -1,6 +1,6 @@ package snr -import "strings" +import "../common" // GroupNameExtract - This function extracts the group ID, if it exists in a row // line : string from the configuration file @@ -8,30 +8,16 @@ // bool : true if the string contains a group identifier // string : group identifier func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { - for _, groupKeyword := range []string{ - "GPP_A", "GPP_B", "GPP_F", - "GPP_C", "GPP_D", "GPP_E", - "GPD", "GPP_I", - "GPP_J", "GPP_K", - "GPP_G", "GPP_H", "GPP_L", - } { - if strings.Contains(line, groupKeyword) { - return true, groupKeyword - } - } - return false, "" + return common.KeywordsCheck(line, + "GPP_A", "GPP_B", "GPP_F", "GPP_C", "GPP_D", "GPP_E", "GPD", "GPP_I", "GPP_J", + "GPP_K", "GPP_G", "GPP_H", "GPP_L") } // KeywordCheck - This function is used to filter parsed lines of the configuration file and // returns true if the keyword is contained in the line. -// line : string from the configuration file +// line : string from the configuration file +// Returns false if no word was found, or true otherwise func (PlatformSpecific) KeywordCheck(line string) bool { - for _, keyword := range []string{ - "GPP_", "GPD", - } { - if strings.Contains(line, keyword) { - return true - } - } - return false + isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD") + return isIncluded } -- To view, visit https://review.coreboot.org/c/coreboot/+/45167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af28960e41fcb97f03fe97c42cdddde07b3615a Gerrit-Change-Number: 45167 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: volteer: set GSPI CS to deasserted by default
by Patrick Georgi (Code Review) 21 Sep '20

21 Sep '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45384 ) Change subject: volteer: set GSPI CS to deasserted by default ...................................................................... volteer: set GSPI CS to deasserted by default This sets the state of GSPI chip select to 1 (deasserted) as applied by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS mode manual in the SerialIoGSpiCsMode section which means we need to explicitly configure CS to deasserted in the SerialIoGSpiCsState section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We were running into problems where the normal expected CS toggle sequence to wake up CR50 did not work because CS was already asserted when it was expected to be deasserted, leading to TPM timeouts. BUG=b:168090038 TEST=booted on volteer, no more "TPM flow control failure" messages; verified fingerprint enrollment still works. Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 3c1c5f0..11542f8 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -142,8 +142,8 @@ }" register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/45384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Gerrit-Change-Number: 45384 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer: Add firmware configuration table for Halvor
by Frank Wu (Code Review) 21 Sep '20

21 Sep '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44560 ) Change subject: mb/google/volteer: Add firmware configuration table for Halvor ...................................................................... mb/google/volteer: Add firmware configuration table for Halvor According to chrome-internal:3217187, add MAX98373_ALC5682I_I2S_UP4 firmware configuration table for Halvor. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor: > AUDIO=MAX98373_ALC5682I_I2S_UP4 ectool cbi set 6 0x00000400 4 2 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600 --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44560/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..e930d9f 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -45,6 +45,18 @@ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ }; +static const struct pad_config i2s_up4_enable_pads[] = { + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S1_SCLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_RXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_TXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ +}; + static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_A23, NONE), PAD_NC(GPP_D19, NONE), @@ -78,5 +90,11 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_UP4))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP4.\n"); + gpio_configure_pads(i2s_up4_enable_pads, ARRAY_SIZE(i2s_up4_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ffae2f0..c8245c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -13,6 +13,7 @@ option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 + option MAX98373_ALC5682I_I2S_UP4 4 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/44560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600 Gerrit-Change-Number: 44560 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

9 28

Change in coreboot[master]: nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate files
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45359 ) Change subject: nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate files ...................................................................... nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate files Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/sandybridge/registers/dmibar.h A src/northbridge/intel/sandybridge/registers/epbar.h M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 79 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45359/1 diff --git a/src/northbridge/intel/sandybridge/registers/dmibar.h b/src/northbridge/intel/sandybridge/registers/dmibar.h new file mode 100644 index 0000000..d47588b --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/dmibar.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_DMIBAR_H__ +#define __SANDYBRIDGE_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIRCLDECH 0x040 /* 32bit */ +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ +#define TXTRN (1 << 11) + +#define DMILCTL2 0x098 /* 16bit */ +#define DMILSTS2 0x09a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#define DMIL0SLAT 0x22c /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ + +#endif /* __SANDYBRIDGE_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/registers/epbar.h b/src/northbridge/intel/sandybridge/registers/epbar.h new file mode 100644 index 0000000..386dbe1 --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/epbar.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_EPBAR_H__ +#define __SANDYBRIDGE_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#endif /* __SANDYBRIDGE_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5c15cb1..24360ac 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -76,23 +76,7 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCAP2 0x008 /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ +#include "registers/epbar.h" /* * DMIBAR @@ -102,52 +86,7 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ -#define DMIPVCCAP2 0x008 /* 32bit */ -#define DMIPVCCCTL 0x00c /* 16bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIVCPRCAP 0x028 /* 32bit */ -#define DMIVCPRCTL 0x02c /* 32bit */ -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP (1 << 1) - -#define DMIVCMRCAP 0x034 /* 32bit */ -#define DMIVCMRCTL 0x038 /* 32bit */ -#define DMIVCMRSTS 0x03e /* 16bit */ -#define VCMNP (1 << 1) - -#define DMIRCLDECH 0x040 /* 32bit */ -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ -#define TXTRN (1 << 11) - -#define DMILCTL2 0x098 /* 16bit */ -#define DMILSTS2 0x09a /* 16bit */ - -#define DMIUESTS 0x1c4 /* 32bit */ -#define DMICESTS 0x1d0 /* 32bit */ - -#define DMIL0SLAT 0x22c /* 32bit */ -#define DMILLTC 0x238 /* 32bit */ +#include "registers/dmibar.h" #ifndef __ASSEMBLER__ -- To view, visit https://review.coreboot.org/c/coreboot/+/45359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b Gerrit-Change-Number: 45359 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Documentation: Add ASan documentation
by Werner Zeh (Code Review) 21 Sep '20

21 Sep '20

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44814 ) Change subject: Documentation: Add ASan documentation ...................................................................... Documentation: Add ASan documentation Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/technotes/asan.md M Documentation/technotes/index.md 2 files changed, 303 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/Documentation/technotes/asan.md b/Documentation/technotes/asan.md new file mode 100644 index 0000000..e0d503a --- /dev/null +++ b/Documentation/technotes/asan.md @@ -0,0 +1,302 @@ +# Address Sanitizer + +Memory safety is hard to achieve. We, as humans, are bound to make mistakes in +our code. While it may be straightforward to detect memory corruption bugs in +few lines of code, it becomes quite challenging to find those bugs in a massive +code. In such cases, 'Address Sanitizer' may prove to be useful and could help +save time. + +[Address Sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) +, also known as ASan, is a runtime memory debugger designed to find +out-of-bounds accesses and use-after-scope bugs. coreboot has an in-built +Address Sanitizer. Therefore, it is advised to take advantage of this debugging +tool while working on large patches. This would further help to ensure code +quality and make runtime code more robust. + +## Types of errors detected +ASan in coreboot catches the following types of memory bugs: + +### Stack buffer overflow +Example stack-out-of-bounds: +```c +void foo() +{ + int stack_array[5] = {0}; + int i, out; + for (i = 0; i < 10; i++) + out = stack_array[i]; +} +``` +In this example, the array is of length 5 but it is being read even beyond the +index 4. + +### Global buffer overflow +Example global-out-of-bounds: +```c +char a[] = "I use coreboot"; + +void foo() +{ + char b[] = "proprietary BIOS"; + strcpy(a + 6, b); +} +``` +In this example, +> well, you are replacing coreboot with proprietary BIOS. In any case, that's +an "error". + +Let's come to the memory bug. The string 'a' is of length 14 but it is being +written to even beyond that. + +### Use after scope +Example use-after-scope: +```c +volatile int *p = 0; + +void foo() { + { + int x = 0; + p = &x; + } + *p = 5; +} +``` +In this example, the value 5 is written to an undefined address instead of the +variable 'x'. This happens because 'x' can't be accessed outside its scope. + +## Using ASan + +In order to enable ASan on a supported platform, +select `Address sanitizer support` from `General setup` menu while configuring +coreboot. + +Then build coreboot and run the image as usual. If your code contains any of the +above-mentioned memory bugs, ASan will report them in the console log as shown +below: +```text +ASan: <bug type> in <ip> +<access type> of <access size> bytes at addr <access address> +``` +where, + +`bug type` is either `stack-out-of-bounds`, `global-out-of-bounds` or +`use-after-scope`, + +`ip` is the address of the last good instruction before the bad access, + +`access type` is either `Read` or `Write`, + +`access size` is the number of bytes read or written, and + +`access address` is the memory location which is accessed while the error +occurs. + +Next, you have to use `ip` to retrieve the instruction which causes the error. +Since stages in coreboot are relocated, you need to normalize `ip`. For this, +first subtract the start address of the stage from `ip`. Then, read the section +headers from `<stage>.debug` file to determine the offset of the text segment. +Add this offset to the difference you calculated earlier. Let's call the +resultant address `ip'`. + +Next, read the contents of the symbol table and search for a function having +an address closest to `ip'`. This is the function in which our memory bug is +present. Let's denote the address of this function by `ip''`. + +Finally, read the assembly contents of the object file where this function is +present. Look for the affected function. Here, the instruction which exists at +the offset `ip' - ip''` corresponds to the address `ip`. Therefore, the very +next instruction is the one which causes the error. + +To see ASan in action, let's take an example. Suppose, there is a +stack-out-of-bounds error in cbfs.c that we aren’t aware of and we want ASan +to help us detect it. +```c +int cbfs_boot_region_device(struct region_device *rdev) +{ + int array[5], i; + boot_device_init(); + + for (i = 10; i > 0; i--) + array[i] = i; + + return vboot_locate_cbfs(rdev) && + fmap_locate_area_as_rdev("COREBOOT", rdev); +} +``` +First, we enable ASan from the configuration menu as shown above. Then, we +build coreboot and run the image. + +ASan reports the following error in the console log: +```text +ASan: stack-out-of-bounds in 0x7f7432fd +Write of 4 bytes at addr 0x7f7c2ac8 +``` +Here 0x7f7432fd is `ip` i.e. the address of the last good instruction before +the bad access. First we have to normalize this address as stated above. +As per the console log, this error happened in ramstage and the stage starts +from 0x7f72c000. So, let’s look at the sections headers of ramstage from +`ramstage.debug`. +```text +$ objdump -h build/cbfs/fallback/ramstage.debug + +build/cbfs/fallback/ramstage.debug: file format elf32-i386 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00070b20 00e00000 00e00000 00001000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .ctors 0000036c 00e70b20 00e70b20 00071b20 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 .data 0001c8f4 00e70e8c 00e70e8c 00071e8c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 3 .bss 00012940 00e8d780 00e8d780 0008e780 2**7 + ALLOC + 4 .heap 00004000 00ea00c0 00ea00c0 0008e780 2**0 + ALLOC +``` +As you can see, the offset of the text segment is 0x00e00000. Let's subtract the +start address of the stage from `ip` and add this offset to the difference. The +resultant address i.e. `ip'` is 0x00e172fd. + +Next, we read the contents of the symbol table and search for a function having +an address closest to 0x00e172fd. +```text +$ nm -n build/cbfs/fallback/ramstage.debug +........ +........ +00e17116 t _GLOBAL__sub_I_65535_1_gfx_get_init_done +00e17129 t tohex16 +00e171db T cbfs_load_and_decompress +00e1729b T cbfs_boot_region_device +00e17387 T cbfs_boot_locate +00e1740d T cbfs_boot_map_with_leak +00e174ef T cbfs_boot_map_optionrom +........ +........ +``` +The symbol having an address closest to 0x00e172fd is `cbfs_boot_region_device` and +its address i.e. `ip''` is 0x00e1729b. + +Now, as we know the affected function, let's read the assembly contents of +`cbfs_boot_region_device()` which is present in `cbfs.o` to find the faulty +instruction. +```text +$ objdump -d build/ramstage/lib/cbfs.o +........ +........ + 51: e8 fc ff ff ff call 52 <cbfs_boot_region_device+0x52> + 56: 83 ec 0c sub $0xc,%esp + 59: 57 push %edi + 5a: 83 ef 04 sub $0x4,%edi + 5d: e8 fc ff ff ff call 5e <cbfs_boot_region_device+0x5e> + 62: 83 c4 10 add $0x10,%esp + 65: 89 5f 04 mov %ebx,0x4(%edi) + 68: 4b dec %ebx + 69: 75 eb jne 56 <cbfs_boot_region_device+0x56> +........ +........ +``` +Here, we look for the instruction present at the offset 62 i.e. `ip' - ip''`. +The instruction is `add $0x10,%esp` and it corresponds to +`for (i = 10; i > 0; i--)` in our code. It means the very next instruction +i.e. `mov %ebx,0x4(%edi)` is the one that causes the error. Now, as we look at +C code of `cbfs_boot_region_device()` again, we find that this instruction +corresponds to `array[i] = i`. + +Voilà! We just caught the memory bug using ASan. + +## Supported platforms +Presently, the following architectures support ASan in ramstage: +```eval_rst ++------------------+--------------------------------+ +| Architecture | Notes | ++==================+================================+ +| x86 | Support for all x86 platforms | ++------------------+--------------------------------+ +``` + +And in romstage ASan is available on the following platforms: +```eval_rst ++---------------------+-----------------------------+ +| Platform | Notes | ++=====================+=============================+ +| QEMU i440-fx | | ++---------------------+-----------------------------+ +| Intel Apollo Lake | | ++---------------------+-----------------------------+ +| Intel Haswell | | ++---------------------+-----------------------------+ +``` +Alternatively, you can use `grep` to view the list of platforms that support +ASan in romstage: + + $ git grep "select HAVE_ASAN_IN_ROMSTAGE" + +If the x86 platform you are using is not listed here, there is +still a chance that it supports ASan in romstage. + +To test it, select `HAVE_ASAN_IN_ROMSTAGE` from the Kconfig file in the +platform's dedicated directory. Then, enable ASan from the config menu as +indicated in the previous section. + +If you are able to build coreboot without any errors and boot cleanly, that +means the platform supports ASan in romstage. In that case, please upload a +patch on Gerrit selecting this config option using 'ASan' topic. Also, update +the platform name in the table. + +However, if you end up in compilation errors or the linker error saying that +the cache got full, additional steps need to be taken to enable ASan in +romstage on the platform. While compile errors could be resolved easily and +therefore ASan in romstage has a good chance to be supported, a full cache is +an indication that it is way more work or even likely impossible to enable +ASan in romstage. + +## Future work +### Heap buffer overflow +Presently, ASan doesn't detect out-of-bounds accesses for the objects defined +in heap. + +To add support for these type of memory bugs, you have to make sure that +whenever some block of memory is allocated in the heap, the surrounding areas +(redzones) are poisoned. Correspondingly, these redzones should be unpoisoned +when the memory block is de-allocated. + +### ASan on other architectures +The following points should help when adding support for ASan to other +architectures like ARM or RISC-V: + +* Enabling ASan in ramstage on other architectures should be easy. You just +have to make sure the shadow memory is initialized as early as possible when +ramstage is loaded. This can be done by making a function call to `asan_init()` +at the appropriate place. + +* For romstage, you have to find out if there is enough room in the cache to fit +the shadow memory region. For this, find the boundary linker symbols for the +region you'd want to run ASan on, excluding the hardware mapped addresses. +Then define a new linker section named `asan_shadow` of size +`(_end - _start) >> 3`, where `_start` and `_end` are the linker symbols you +found earlier. This section should be appended to the region already occupied +by the coreboot program. Now build coreboot. If you don't see any errors while +building with the current translation function, ASan can be enabled on that +platform. + +* The shadow region we currently use consumes memory equal to 1/8th of the +program memory. So, if you end up in a linker error saying that the memory got +full, you'll have to use a more compact shadow region. In that case, the +translation function could be something like +`shadow = (mem >> 7) | shadow_offset`. Since the stack buffers are protected by +the compiler, you'll also have to create a GCC patch forcing it to use the new +translation function for this particular architecture. + +* Once you are sure that the architecture supports ASan in ramstage, select +`HAVE_ASAN_IN_RAMSTAGE` from the Kconfig file of that architecture. Similarly, +if the platform supports ASan in romstage, select `HAVE_ASAN_IN_ROMSTAGE` from +the platform's dedicated Kconfig file. + +### Post-processing script +Unlike Linux, coreboot doesn't have `%pS` printk format to dereference pointer +to its symbolic name. Therefore, we normalise the pointer address manually to +determine the name of the affected function and further use it to find the +instruction which causes the error. + +A custom script can be written to automate this process. diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index 5367e69..a9320fb 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,3 +3,4 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Address Sanitizer](asan.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/44814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Gerrit-Change-Number: 44814 Gerrit-PatchSet: 8 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020