coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: find IIO_UDS HOB once when creating DMAR table
by Jonathan Zhang (Code Review) 21 Sep '20

21 Sep '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45376 ) Change subject: soc/intel/xeon_sp/cpx: find IIO_UDS HOB once when creating DMAR table ...................................................................... soc/intel/xeon_sp/cpx: find IIO_UDS HOB once when creating DMAR table IIO_UDS HOB was found several times during the creation of DMAR table. Reduce it to only once to improve boot time. Both DRHD and ATSR subtable creations involve addition of PCIe bridge device entries, combine the functions with acpi_create_dmar_ds_pci_br_for_port(). When looping through ports to create PCIe bridge device entries, use MAX_PORTS intead of NUMBER_PORTS_PER_SOCKET to improve boot time. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 65 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45376/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a40d33d..62b1033 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -579,26 +579,61 @@ } /* - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACK0 stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 + * This function adds PCIe bridge device entry in DMAR table. If it is called + * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ -static int get_stack_for_port(int p) +static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, + int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + bool is_atsr, bool *first) { - if (p == 0) - return CSTACK; - else if (p >= PORT_1A && p <= PORT_1D) - return PSTACK0; - else if (p >= PORT_2A && p <= PORT_2D) - return PSTACK1; - else //if (p >= PORT_3A && p <= PORT_3D) - return PSTACK2; + /* + * If the port is not part of the stack, return back. + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ + if (port == PORT_0 && stack != CSTACK) + return 0; + else if (port >= PORT_1A && port <= PORT_1D && stack != PSTACK0) + return 0; + else if (port >= PORT_2A && port <= PORT_2D && stack != PSTACK1) + return 0; + else if (port >= PORT_3A && port <= PORT_3D && stack != PSTACK2) + return 0; + else if (port > PORT_3D) + return 0; + + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + return 0; + + unsigned long atsr_size = 0; + unsigned long pci_br_size = 0; + if (is_atsr == true && *first == true) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", 0, pcie_seg); + atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); + *first = false; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); + + return (atsr_size + pci_br_size); } -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +static unsigned long acpi_create_drhd(unsigned long current, int socket, + int stack, const IIO_UDS *hob) { int IoApicID[] = { // socket 0 @@ -612,12 +647,6 @@ uint32_t enum_id; unsigned long tmp = current; - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; uint32_t reg_base = @@ -670,24 +699,9 @@ if (socket != 0 || stack != CSTACK) { IIO_RESOURCE_INSTANCE iio_resource = hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, - bus, dev, func); - } + for (int p = 0; p < MAX_PORTS; ++p) + current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, + iio_resource, pcie_seg, false, NULL); // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && @@ -722,13 +736,8 @@ return current; } -static unsigned long acpi_create_atsr(unsigned long current) +static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) { - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; unsigned long tmp = current; @@ -752,32 +761,11 @@ if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 continue; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + for (int p = 0; p < MAX_PORTS; ++p) { if (socket == 0 && p == 0) continue; - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - if (first) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", - 0, pcie_seg); - current += acpi_create_dmar_atsr(current, 0, pcie_seg); - first = 0; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, + iio_resource, pcie_seg, true, &first); } } if (tmp != current) @@ -857,20 +845,21 @@ socket = 0; if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); + for (int stack = 1; stack <= PSTACK2; ++stack) { + current = acpi_create_drhd(current, socket, stack, hob); + } + current = acpi_create_drhd(current, socket, CSTACK, hob); } else { for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, stack, hob); } } // RMRR current = acpi_create_rmrr(current); - // ATSR - causes hang - current = acpi_create_atsr(current); + // Root Port ATS Capability + current = acpi_create_atsr(current, hob); // RHSA current = acpi_create_rhsa(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/45376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032 Gerrit-Change-Number: 45376 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable PMC support
by Rocky Phagura (Code Review) 21 Sep '20

21 Sep '20

Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42289 ) Change subject: soc/intel/xeon_sp: Enable PMC support ...................................................................... soc/intel/xeon_sp: Enable PMC support PMC support was not enabled on Xeon_sp platforms. This involves turning on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC specific code. This patch leverages code from the Skylake project and adds the bare bare minimum hooks to leverage PMC common code. Most importantly this enables power management registers located in the PMC device (under ACPI_BASE_ADDRESS). Access to this device is also needed for SMM setup and handling. TEST=build for Tiogapass and enable the following Kconfig options: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and check to ensure pmbase is programmed. (Look for pmbase in debug messages). Secondly check that SMIs are enabled by looking at the debug messages (search for "Enabling SMIs") and verifying in HW by reading IO port 0x530. Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/include/soc/gpe.h M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pmc.c A src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/chip.h 8 files changed, 385 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42289/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 9589e5a..a8f98e5 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmutil.c pmc.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/include/soc/gpe.h b/src/soc/intel/xeon_sp/include/soc/gpe.h new file mode 100644 index 0000000..c4acf1c --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/gpe.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE_MAX GPE0_DW0_02 +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 68f6f55..4b4367b 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -20,6 +20,7 @@ #define SPI_BASE_SIZE 0x1000 #define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_SIZE 0x100 /* Video RAM */ #define VGA_BASE_ADDRESS 0xa0000 @@ -28,6 +29,10 @@ /* High Performance Event Timer */ #define HPET_BASE_ADDRESS 0xfed00000 +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + + #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index c4c1a88..ef754e1 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -3,15 +3,105 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include <acpi/acpi.h> +#include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pmc.h> -#define PM1_CNT 0x04 -#define PM1_STS 0x00 -#define PM1_TMR 0x08 -#define PM2_CNT 0x50 -#define GPE0_REG_MAX 4 -#define GPE0_STS(x) (0x80 + (x * 4)) +/* ACPI_BASE_ADDRESS / PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define PM1_EN 0x02 +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define ESPI_SMI_EN (1 << 28) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define PM1_STS_BIT 8 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x80 + (x * 4)) +#define GPE0_EN(x) (0x90 + (x * 4)) +#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define GPIO_T2_STS (1 << 15) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define GPE0_EN(x) (0x90 + (x * 4)) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) + +#define ENABLE_SMI_PARAMS \ + (APMC_EN | GBL_SMI_EN | EOS) + +/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ +#define ETR 0xac +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define PRSTS 0x10 + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + +uint16_t get_pmbase(void); #endif + diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index d3bad1b..5487dc2b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -21,10 +21,22 @@ #define SCIS_IRQ23 7 #define PWRMBASE 0x48 #define GEN_PMCON_A 0xa0 +#define DISB (1 << 23) +#define GBL_RST_STS (1 << 16) #define SMI_LOCK (1 << 4) #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) +#define SUS_PWR_FLR (1 << 14) +#define HOST_RST_STS (1 << 9) +#define RTC_BATTERY_DEAD (1 << 2) +#define PWR_FLR (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) - +/* Memory mapped IO registers in PMC */ +#define GPIO_GPE_CFG 0x120 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) +#define GBLRST_CAUSE0 0x124 +#define GBLRST_CAUSE1 0x128 #endif diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c new file mode 100644 index 0000000..bead9d2 --- /dev/null +++ b/src/soc/intel/xeon_sp/pmc.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci_ops.h> +#include <intelblocks/pmc.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <reg_script.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include "chip.h" + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; +#if defined(__SIMPLE_DEVICE__) + const pci_devfn_t dev = PCH_DEV_PMC; +#else + const struct device *const dev = PCH_DEV_PMC; +#endif + + reg8 = pci_read_config8(dev, GEN_PMCON_B); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + pci_write_config8(dev, GEN_PMCON_B, reg8); +} + +#if ENV_RAMSTAGE +/* Fill up PMC resource structure */ +int pmc_soc_get_resources(struct pmc_resource_config *cfg) +{ + cfg->pwrmbase_offset = PWRMBASE; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; + cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; + cfg->abase_offset = ABASE; + cfg->abase_addr = ACPI_BASE_ADDRESS; + cfg->abase_size = ACPI_BASE_SIZE; + + return 0; +} + +static const struct reg_script pch_pmc_misc_init_script[] = { + /* Enable SCI and clear SLP requests. */ + REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), + REG_SCRIPT_END +}; + +static const struct reg_script pmc_write1_to_clear_script[] = { + REG_PCI_OR32(GEN_PMCON_A, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), + REG_SCRIPT_END +}; + +void pmc_soc_init(struct device *dev) +{ + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + /* Note that certain bits may be cleared from running script as + * certain bit fields are write 1 to clear. */ + reg_script_run_on_dev(dev, pch_pmc_misc_init_script); + pmc_set_acpi_mode(); + + /* Clear registers that contain write-1-to-clear bits. */ + reg_script_run_on_dev(dev, pmc_write1_to_clear_script); +} + +#endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c new file mode 100644 index 0000000..f7be484 --- /dev/null +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#include <acpi/acpi.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/tco.h> +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include "chip.h" + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *smi_arr) +{ + static const char *const smi_sts_bits[] = { + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [7] = "BIOS_RLS", + [8] = "PM1", + [9] = "GPE0", + [10] = "GPI", + [11] = "MCSMI", + [12] = "DEVMON", + [13] = "TCO", + [14] = "PERIODIC", + [20] = "PCI_EXP_SMI", + [23] = "IE_SMI", + [25] = "SCC_SMI", + [26] = "SPI", + [27] = "GPIO_UNLOCK", + [28] = "ESPI_SMI", + [29] = "SERIAL_I/O", + [30] = "ME_SMI", + [31] = "XHCI", + }; + + *smi_arr = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) +{ + static const char *const gpe_sts_bits[] = { + }; + + *gpe_arr = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +uint8_t *pmc_mmio_regs(void) +{ + uint32_t reg32; + + reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE); + + /* 4KiB alignment. */ + reg32 &= ~0xfff; + + return (void *)(uintptr_t) reg32; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t) (pmc_mmio_regs()); +} + +uint32_t *soc_pmc_etr_addr(void) +{ + /* + * The pointer returned must not be cached, because the address depends on the + * MMCONF base address and the assigned PCI bus number, which both may change + * during the boot process! + */ + return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_xeon_sp_skx_config *config; + + config = config_of_soc(); + + /* Assign to out variable */ + *dw0 = config->gpe0_dw0; + *dw1 = config->gpe0_dw1; + *dw2 = config->gpe0_dw2; +} + +int rtc_failure(void) +{ + u8 reg8; + int rtc_failed; + /* PMC Controller Device 0x1F, Func 02 */ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_PMC; +#else + struct device *dev = PCH_DEV_PMC; +#endif + reg8 = pci_read_config8(dev, GEN_PMCON_B); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_B, reg8); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + } + + return !!rtc_failed; +} + + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (!(ps->pm1_sts & WAK_STS) && + (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); + ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); + + pmc = pmc_mmio_regs(); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index c7f19ec..402a565 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -37,6 +37,13 @@ * 6h = PIRQG# * 7h = PIRQH# */ + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint16_t ir00_routing; uint16_t ir01_routing; uint16_t ir02_routing; -- To view, visit https://review.coreboot.org/c/coreboot/+/42289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd Gerrit-Change-Number: 42289 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-MessageType: newchange

8 31

Change in coreboot[master]: soc/intel/xeon_sp/cpx: remove DMAR_X2APIC_OPT_OUT flag
by Jonathan Zhang (Code Review) 21 Sep '20

21 Sep '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45375 ) Change subject: soc/intel/xeon_sp/cpx: remove DMAR_X2APIC_OPT_OUT flag ...................................................................... soc/intel/xeon_sp/cpx: remove DMAR_X2APIC_OPT_OUT flag CPX-SP processor supports X2APIC. Remove DMAR_X2APIC_OPT_OUT flag from DMAR table. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45375/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..a40d33d 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -909,9 +909,8 @@ current = ALIGN(current, 8); dmar = (acpi_dmar_t *)current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", - (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); - acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); -- To view, visit https://review.coreboot.org/c/coreboot/+/45375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158 Gerrit-Change-Number: 45375 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: nb/intel/ironlake: Clean up cosmetics of early ME functions
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45366 ) Change subject: nb/intel/ironlake: Clean up cosmetics of early ME functions ...................................................................... nb/intel/ironlake: Clean up cosmetics of early ME functions Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 38 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45366/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index c36b73b..aa73d99 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1623,8 +1623,8 @@ { while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c ; - write32((DEFAULT_HECIBAR + 0x4), - (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); + + write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); } /* FIXME: add timeout. */ @@ -1638,12 +1638,10 @@ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; - do + do { csr.raw = read32(DEFAULT_HECIBAR + 0x4); - while (len > - csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - - csr.csr.buffer_read_ptr)) - ; + } while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - + csr.csr.buffer_read_ptr)); } static void send_heci_packet(struct mei_header *head, u32 *payload) @@ -1662,8 +1660,7 @@ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4); } -static void -send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) +static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) { struct mei_header head; int maxlen; @@ -1689,9 +1686,7 @@ } /* FIXME: Add timeout. */ -static int -recv_heci_packet(struct mei_header *head, u32 *packet, - u32 *packet_size) +static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size) { union { struct mei_csr csr; @@ -1702,27 +1697,23 @@ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); do { csr.raw = read32(DEFAULT_HECIBAR + 0xc); - } - while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr) - ; + } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); + *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); if (!head->length) { - write32(DEFAULT_HECIBAR + 0x4, - read32(DEFAULT_HECIBAR + 0x4) | 2); + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); *packet_size = 0; return 0; } - if (head->length + 4 > 4 * csr.csr.buffer_depth - || head->length > *packet_size) { + if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { *packet_size = 0; return -1; } - do + do { csr.raw = read32(DEFAULT_HECIBAR + 0xc); - while (((head->length + 3) >> 2) > - (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)) - ; + } while (((head->length + 3) >> 2) > + (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)); for (i = 0; i < (head->length + 3) >> 2; i++) packet[i++] = read32(DEFAULT_HECIBAR + 0x8); @@ -1734,8 +1725,7 @@ } /* FIXME: Add timeout. */ -static int -recv_heci_message(u32 *message, u32 *message_size) +static int recv_heci_message(u32 *message, u32 *message_size) { struct mei_header head; int current_position; @@ -1784,18 +1774,24 @@ u8 result; u32 c2; u64 heci_uma_addr; - u32 memory_reserved_for_heci_mb; + u32 heci_uma_size; u16 c3; } __packed msg = { - 0, MKHI_SET_UMA, 0, 0, - 0x82, - heci_uma_addr, heci_uma_size, 0}; + .group_id = 0, + .cmd = MKHI_SET_UMA, + .reserved = 0, + .result = 0, + .c2 = 0x82, + .heci_uma_addr = heci_uma_addr, + .heci_uma_size = heci_uma_size, + .c3 = 0, + }; u32 reply_size; - send_heci_message((u8 *) & msg, sizeof(msg), 0, 7); + send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); reply_size = sizeof(reply); - if (recv_heci_message((u32 *) & reply, &reply_size) == -1) + if (recv_heci_message((u32 *) &reply, &reply_size) == -1) return; if (reply.command != (MKHI_SET_UMA | (1 << 7))) @@ -1809,30 +1805,23 @@ const u64 heci_uma_addr = ((u64) - ((((u64) pci_read_config16(NORTHBRIDGE, TOM)) << 6) - + ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; pci_read_config32(NORTHBRIDGE, DMIBAR); if (info->memory_reserved_for_heci_mb) { - write32(DEFAULT_DMIBAR + 0x14, - read32(DEFAULT_DMIBAR + 0x14) & ~0x80); - write32(DEFAULT_RCBA + 0x14, - read32(DEFAULT_RCBA + 0x14) & ~0x80); - write32(DEFAULT_DMIBAR + 0x20, - read32(DEFAULT_DMIBAR + 0x20) & ~0x80); - write32(DEFAULT_RCBA + 0x20, - read32(DEFAULT_RCBA + 0x20) & ~0x80); - write32(DEFAULT_DMIBAR + 0x2c, - read32(DEFAULT_DMIBAR + 0x2c) & ~0x80); - write32(DEFAULT_RCBA + 0x30, - read32(DEFAULT_RCBA + 0x30) & ~0x80); - write32(DEFAULT_DMIBAR + 0x38, - read32(DEFAULT_DMIBAR + 0x38) & ~0x80); - write32(DEFAULT_RCBA + 0x40, - read32(DEFAULT_RCBA + 0x40) & ~0x80); + write32(DEFAULT_DMIBAR + 0x14, read32(DEFAULT_DMIBAR + 0x14) & ~0x80); + write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80); + write32(DEFAULT_DMIBAR + 0x20, read32(DEFAULT_DMIBAR + 0x20) & ~0x80); + write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80); + write32(DEFAULT_DMIBAR + 0x2c, read32(DEFAULT_DMIBAR + 0x2c) & ~0x80); + write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80); + write32(DEFAULT_DMIBAR + 0x38, read32(DEFAULT_DMIBAR + 0x38) & ~0x80); + write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80); - write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK + write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK + while ((read16(DEFAULT_RCBA + 0x46) & 2) && read16(DEFAULT_DMIBAR + 0x3e) & 2) ; @@ -1844,7 +1833,6 @@ pci_write_config32(HECIDEV, 0x10, 0x0); pci_write_config8(HECIDEV, 0x4, 0x0); - } static int have_match_ranks(struct raminfo *info, int channel, int ranks) -- To view, visit https://review.coreboot.org/c/coreboot/+/45366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79 Gerrit-Change-Number: 45366 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: nb/intel/ironlake: Clean up `send_heci_uma_message` signature
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45365 ) Change subject: nb/intel/ironlake: Clean up `send_heci_uma_message` signature ...................................................................... nb/intel/ironlake: Clean up `send_heci_uma_message` signature The only raminfo field it needs is `memory_reserved_for_heci_mb`. So, pass in that value directly. As it's read-only, make it const as well. Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/45365/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 6e63b39..c36b73b 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1763,7 +1763,7 @@ return -1; } -static void send_heci_uma_message(struct raminfo *info, const u64 heci_uma_addr) +static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) { struct uma_reply { u8 group_id; @@ -1789,7 +1789,7 @@ } __packed msg = { 0, MKHI_SET_UMA, 0, 0, 0x82, - heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; + heci_uma_addr, heci_uma_size, 0}; u32 reply_size; send_heci_message((u8 *) & msg, sizeof(msg), 0, 7); @@ -1840,7 +1840,7 @@ MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb; - send_heci_uma_message(info, heci_uma_addr); + send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb); pci_write_config32(HECIDEV, 0x10, 0x0); pci_write_config8(HECIDEV, 0x4, 0x0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d Gerrit-Change-Number: 45365 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/ironlake: Reduce the scope of `heci_uma_addr`
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45364 ) Change subject: nb/intel/ironlake: Reduce the scope of `heci_uma_addr` ...................................................................... nb/intel/ironlake: Reduce the scope of `heci_uma_addr` There's no need to have it in raminfo. Also, bump MRC_CACHE_VERSION. Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45364/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 44b6a71..6e63b39 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -61,7 +61,7 @@ u8 largest; } timing_bounds_t[2][2][2][9]; -#define MRC_CACHE_VERSION 2 +#define MRC_CACHE_VERSION 3 struct ram_training { /* [TM][CHANNEL][SLOT][RANK][LANE] */ @@ -192,7 +192,6 @@ unsigned int interleaved_part_mb; unsigned int non_interleaved_part_mb; - u64 heci_uma_addr; unsigned int memory_reserved_for_heci_mb; struct ram_training training; @@ -1764,7 +1763,7 @@ return -1; } -static void send_heci_uma_message(struct raminfo *info) +static void send_heci_uma_message(struct raminfo *info, const u64 heci_uma_addr) { struct uma_reply { u8 group_id; @@ -1790,7 +1789,7 @@ } __packed msg = { 0, MKHI_SET_UMA, 0, 0, 0x82, - info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; + heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; u32 reply_size; send_heci_message((u8 *) & msg, sizeof(msg), 0, 7); @@ -1805,11 +1804,10 @@ static void setup_heci_uma(struct raminfo *info) { - info->heci_uma_addr = 0; if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20)) return; - info->heci_uma_addr = + const u64 heci_uma_addr = ((u64) ((((u64) pci_read_config16(NORTHBRIDGE, TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; @@ -1842,7 +1840,7 @@ MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb; - send_heci_uma_message(info); + send_heci_uma_message(info, heci_uma_addr); pci_write_config32(HECIDEV, 0x10, 0x0); pci_write_config8(HECIDEV, 0x4, 0x0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80 Gerrit-Change-Number: 45364 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/sandybridge: Drop unnecessary `gma.h`
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45360 ) Change subject: nb/intel/sandybridge: Drop unnecessary `gma.h` ...................................................................... nb/intel/sandybridge: Drop unnecessary `gma.h` It only contains prototypes for the long-gone native graphics init. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9413abb8e49496ada60dcdf801a1f8a03be38d2e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/gma.c D src/northbridge/intel/sandybridge/gma.h 2 files changed, 0 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45360/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index fee7513..f75dfda 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -16,7 +16,6 @@ #include "chip.h" #include "sandybridge.h" -#include "gma.h" struct gt_powermeter { u16 reg; diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h deleted file mode 100644 index bbff461..0000000 --- a/src/northbridge/intel/sandybridge/gma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H -#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H - -#include <stdint.h> - -struct i915_gpu_controller_info; - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, - u8 *mmio, u32 lfb); - -int i915lightup_ivy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, - u8 *mmio, u32 lfb); - -#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9413abb8e49496ada60dcdf801a1f8a03be38d2e Gerrit-Change-Number: 45360 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/cnl: Use the common code to set the PchPmPwrCycDur
by V Sowmya (Code Review) 21 Sep '20

21 Sep '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45029 ) Change subject: soc/intel/cnl: Use the common code to set the PchPmPwrCycDur ...................................................................... soc/intel/cnl: Use the common code to set the PchPmPwrCycDur This patch uses the common code to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. Change-Id: Id418480bc779d56ff5586516d9bd99ca15133203 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 1 insertion(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45029/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 51ed2a8..dd91de5 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -8,6 +8,7 @@ #include <fsp/util.h> #include <intelblocks/lpss.h> #include <intelblocks/power_limit.h> +#include <intelblocks/pmclib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <soc/intel/common/vbt.h> @@ -32,39 +33,6 @@ PCH_DEVFN_UART2 }; -/* List of Minimum Assertion durations in microseconds */ -enum min_assrt_dur { - MinAssrtDur0s = 0, - MinAssrtDur60us = 60, - MinAssrtDur1ms = 1000, - MinAssrtDur50ms = 50000, - MinAssrtDur98ms = 98000, - MinAssrtDur500ms = 500000, - MinAssrtDur1s = 1000000, - MinAssrtDur2s = 2000000, - MinAssrtDur3s = 3000000, - MinAssrtDur4s = 4000000, -}; - - -/* Signal Assertion duration values */ -struct cfg_assrt_dur { - /* Minimum assertion duration of SLP_A signal */ - enum min_assrt_dur slp_a; - - /* Minimum assertion duration of SLP_4 signal */ - enum min_assrt_dur slp_s4; - - /* Minimum assertion duration of SLP_3 signal */ - enum min_assrt_dur slp_s3; - - /* PCH PM Power Cycle duration */ - enum min_assrt_dur pm_pwr_cyc_dur; -}; - -/* Default value of PchPmPwrCycDur */ -#define PCH_PM_PWR_CYC_DUR 4 - /* * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP * UPD expected value for Serial IO since valid enum index starts from 1. @@ -90,93 +58,6 @@ } #if CONFIG(SOC_INTEL_COMETLAKE) -static enum min_assrt_dur get_high_asst_width(const struct cfg_assrt_dur *cfg_assrt_dur) -{ - enum min_assrt_dur max_assert_dur = cfg_assrt_dur->slp_s4; - - if (max_assert_dur < cfg_assrt_dur->slp_s3) - max_assert_dur = cfg_assrt_dur->slp_s3; - - if (max_assert_dur < cfg_assrt_dur->slp_a) - max_assert_dur = cfg_assrt_dur->slp_a; - - return max_assert_dur; -} - -static void get_min_assrt_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, - uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur, - struct cfg_assrt_dur *cfg_assrt_dur) -{ - /* - * Ensure slp_x_dur_list[] elements are in sync with devicetree config to FSP encoded - * values. - * slp_s4_asst_dur_list : 1s, 1s, 2s, 3s, 4s(Default) - */ - const enum min_assrt_dur slp_s4_asst_dur_list[] = { - MinAssrtDur1s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s - }; - - /* slp_s3_asst_dur_list: 50ms, 60us, 50ms (Default), 2s */ - const enum min_assrt_dur slp_s3_asst_dur_list[] = { - MinAssrtDur50ms, MinAssrtDur60us, MinAssrtDur50ms, MinAssrtDur2s - }; - - /* slp_a_asst_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ - const enum min_assrt_dur slp_a_asst_dur_list[] = { - MinAssrtDur2s, MinAssrtDur0s, MinAssrtDur4s, MinAssrtDur98ms, MinAssrtDur2s - }; - - /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ - const enum min_assrt_dur pm_pwr_cyc_dur_list[] = { - MinAssrtDur4s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s - }; - - /* Get signal assertion width */ - if (slp_s4_min_asst < ARRAY_SIZE(slp_s4_asst_dur_list)) - cfg_assrt_dur->slp_s4 = slp_s4_asst_dur_list[slp_s4_min_asst]; - - if (slp_s3_min_asst < ARRAY_SIZE(slp_s3_asst_dur_list)) - cfg_assrt_dur->slp_s3 = slp_s3_asst_dur_list[slp_s3_min_asst]; - - if (slp_a_min_asst < ARRAY_SIZE(slp_a_asst_dur_list)) - cfg_assrt_dur->slp_a = slp_a_asst_dur_list[slp_a_min_asst]; - - if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) - cfg_assrt_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; -} - - -static uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, - uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur) -{ - /* Sets default minimum asserton duration values */ - struct cfg_assrt_dur cfg_assrt_dur = { - .slp_a = MinAssrtDur2s, - .slp_s4 = MinAssrtDur4s, - .slp_s3 = MinAssrtDur50ms, - .pm_pwr_cyc_dur = MinAssrtDur4s - }; - - enum min_assrt_dur high_asst_width; - - /* Convert assertion durations from register-encoded to microseconds */ - get_min_assrt_dur(slp_s4_min_asst, slp_s3_min_asst, slp_a_min_asst, pm_pwr_cyc_dur, - &cfg_assrt_dur); - - /* Get the higher assertion duration among PCH EDS specified signals for pwr_cyc_dur */ - high_asst_width = get_high_asst_width(&cfg_assrt_dur); - - if (cfg_assrt_dur.pm_pwr_cyc_dur >= high_asst_width) - return pm_pwr_cyc_dur; - - printk(BIOS_DEBUG, - "Set PmPwrCycDur to 4s as configured PmPwrCycDur(%d) violates PCH EDS " - "spec\n", pm_pwr_cyc_dur); - - return PCH_PM_PWR_CYC_DUR; -} - - static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) { uint32_t dev_offset = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/45029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id418480bc779d56ff5586516d9bd99ca15133203 Gerrit-Change-Number: 45029 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/sandybridge: Move register headers into a subfolder
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45358 ) Change subject: nb/intel/sandybridge: Move register headers into a subfolder ...................................................................... nb/intel/sandybridge: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- R src/northbridge/intel/sandybridge/registers/host_bridge.h R src/northbridge/intel/sandybridge/registers/mchbar.h M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45358/1 diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h similarity index 90% rename from src/northbridge/intel/sandybridge/hostbridge_regs.h rename to src/northbridge/intel/sandybridge/registers/host_bridge.h index 2d2fcff..4814b94 100644 --- a/src/northbridge/intel/sandybridge/hostbridge_regs.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ -#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ +#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,4 +60,4 @@ #define DIDOR 0xf3 /* Device ID override, for debug and samples only */ -#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h similarity index 98% rename from src/northbridge/intel/sandybridge/mchbar_regs.h rename to src/northbridge/intel/sandybridge/registers/mchbar.h index 370dd74..2fe6b24 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ -#define __SANDYBRIDGE_MCHBAR_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ +#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__ /* * ### IOSAV memory controller interface poking state machine notes ### @@ -533,4 +533,4 @@ #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ #define CRDTLCK 0x77fc -#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5318d0b..5c15cb1 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ @@ -66,7 +66,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" /* * EPBAR - Egress Port Root Complex Register Block -- To view, visit https://review.coreboot.org/c/coreboot/+/45358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Gerrit-Change-Number: 45358 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45357 ) Change subject: nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers ...................................................................... nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers Several registers have been copy-pasted from i945 and do not exist on Sandy Bridge. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 26 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45357/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 287c441..d4cbec8 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -157,8 +157,8 @@ DMIBAR32(0x0914 + (i << 5)) = 0x98200280; } - DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; + DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 + DMIBAR32(DMIL0SLAT) = 0x00c2403c; early_pch_init_native_dmi_pre(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e670c09..541bf73 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -262,8 +262,8 @@ u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -273,9 +273,9 @@ DMIBAR32(0x250) = reg32; } - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; if (bridge_silicon_revision() >= SNB_STEP_D0) { reg32 = DMIBAR32(0x1f8); @@ -300,9 +300,9 @@ DMIBAR32(0xd04) = reg32; } - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9db5ae3..5318d0b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -87,9 +87,6 @@ #define EPVC1RCTL 0x020 /* 32bit */ #define EPVC1RSTS 0x026 /* 16bit */ -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - #define EPESD 0x044 /* 32bit */ #define EPLE1D 0x050 /* 32bit */ @@ -97,8 +94,6 @@ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ -#define PORTARB 0x100 /* 256bit */ - /* * DMIBAR */ @@ -110,27 +105,30 @@ #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP2 0x008 /* 32bit */ - #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ #define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP 0x2 +#define VC0NP (1 << 1) #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP 0x2 +#define VC1NP (1 << 1) +#define DMIVCPRCAP 0x028 /* 32bit */ #define DMIVCPRCTL 0x02c /* 32bit */ - #define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP 0x2 +#define VCPNP (1 << 1) -#define DMIVCMRCTL 0x0038 /* 32 bit */ -#define DMIVCMRSTS 0x003e /* 16 bit */ -#define VCMNP 0x2 +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIRCLDECH 0x040 /* 32bit */ +#define DMIESD 0x044 /* 32bit */ #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -141,12 +139,15 @@ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ #define TXTRN (1 << 11) -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ -#define DMICC 0x208 /* 32bit */ +#define DMILCTL2 0x098 /* 16bit */ +#define DMILSTS2 0x09a /* 16bit */ -#define DMIDRCCFG 0xeb4 /* 32bit */ +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#define DMIL0SLAT 0x22c /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ #ifndef __ASSEMBLER__ -- To view, visit https://review.coreboot.org/c/coreboot/+/45357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892 Gerrit-Change-Number: 45357 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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