coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig
by Michael Niewöhner (Code Review) 21 Sep '20

21 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45413 ) Change subject: soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig ...................................................................... soc/intel/common/block/sgx: drop no-ops from PRMRR Kconfig Since PRMRR size can only be set when SGX is enabled and since SGX depends on PRMRR size >= 32MB, any lower setting (including "Disabled") is invalid. Drop these settings. Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45413 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/sgx/Kconfig 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index ef3365f..48ba1fc 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -31,14 +31,11 @@ default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB default 64 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB - default 32 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB - default 1 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB choice prompt "PRMRR size" depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE help PRMRR (Protected Memory Range) is the space in RAM that is used to provide a protected memory area (e.g. for the Intel SGX Secure Enclaves). The memory region is accessible @@ -63,14 +60,6 @@ config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB bool "32 MiB" -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB - depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB - bool "1 MiB" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED - depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB - bool "Disabled" - endchoice endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7a19c7223a0de2e03b7df9184cddf7c9fc87a68 Gerrit-Change-Number: 45413 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Michael Niewöhner (Code Review) 21 Sep '20

21 Sep '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45412 ) Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... soc/intel/common/block/sgx: make PRMRR size setting depend on SGX PRMRR size shall only be set when SGX is enabled. Make PRMRR depend on SGX enablement in Kconfig. Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45412 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/sgx/Kconfig 2 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index fd39197..9ff7923 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -346,7 +346,7 @@ int i; int valid_size; - if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) return 0; msr = rdmsr(MSR_PRMRR_VALID_CONFIG); diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 771c54c..ef3365f 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -26,6 +26,7 @@ config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE int + depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB @@ -35,6 +36,7 @@ choice prompt "PRMRR size" + depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE help -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse_lite: Defer cse_fw_sync for JSL
by Karthik Ramasubramanian (Code Review) 21 Sep '20

21 Sep '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45515 ) Change subject: soc/intel/common/cse_lite: Defer cse_fw_sync for JSL ...................................................................... soc/intel/common/cse_lite: Defer cse_fw_sync for JSL Defer cse_fw_sync to BS_DEV_RESOURCES boot state so that MRC training data can be cached before CSE FW Sync and a second MRC training can be avoided. BUG=b:168850641 TEST=Build and boot the waddledoo board to OS. Ensure that the memory training is performed only once. Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45515/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 7daa35e..c9e4e1f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -751,7 +751,7 @@ } } -#if CONFIG(SOC_INTEL_TIGERLAKE) +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) /* * This needs to happen after the MRC cache write to avoid a 2nd * memory training sequence. -- To view, visit https://review.coreboot.org/c/coreboot/+/45515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ef5693eaa6ed34dc08c94e5db153f4295578f5f Gerrit-Change-Number: 45515 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX
by Nico Huber (Code Review) 21 Sep '20

21 Sep '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45412 ) Change subject: soc/intel/common/block/sgx: make PRMRR size setting depend on SGX ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I551942fd9cb8e7123d00dbd752abffe24788148c Gerrit-Change-Number: 45412 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 21 Sep 2020 15:48:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/51nb/x210/gpio: 1/4 Decode raw register values
by Maxim Polyakov (Code Review) 21 Sep '20

21 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43566 ) Change subject: mb/51nb/x210/gpio: 1/4 Decode raw register values ...................................................................... mb/51nb/x210/gpio: 1/4 Decode raw register values Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... ./intelp2m -adv -t 1 -file ../../src/mainboard/51nb/x210/gpio.h [*] Some changes have been made to intelp2m so that the utility can decode RO fields. [*] The test with BUILD_TIMELESS = 1 is successfully. The images before and after the patch are the same. This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": - 1/4 Decode raw register values - 2/4 Exclude fields for PAD_CFG - 3/4 Fixes PAD_RESET to convert to PAD_NC() - 4/4 Convert field macros to PAD_CFG [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I19282c985cf35a9f99be449915aa9bab7e03472d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43566/1 diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index c517b44..9df4769 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -10,170 +10,170 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PD)), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), /* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), /* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PD)), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(20K_PU)), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), (1 << 25) | PAD_PULL(20K_PU)), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19282c985cf35a9f99be449915aa9bab7e03472d Gerrit-Change-Number: 43566 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: soc/intel/cnl: Enable HECI3 depending on devicetree
by Felix Singer (Code Review) 21 Sep '20

21 Sep '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44579 ) Change subject: soc/intel/cnl: Enable HECI3 depending on devicetree ...................................................................... soc/intel/cnl: Enable HECI3 depending on devicetree Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/purism/librem_whl/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 4 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44579/1 diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index c122bb8..2f4bca3 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -277,9 +277,7 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off # Management Engine Interface 3 - register "Heci3Enabled" = "0" - end + device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 9cdeeab..ff088c9 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -201,9 +201,7 @@ device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off # Management Engine Interface 3 - register "Heci3Enabled" = "0" - end + device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2923efc..1b92f0a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -226,7 +226,6 @@ uint8_t PchIshEnable; /* Heci related */ - uint8_t Heci3Enabled; uint8_t DisableHeciRetry; /* Gfx related */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0779ce2..e7d4fb2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -523,7 +523,8 @@ else params->ScsUfsEnabled = dev->enabled; - params->Heci3Enabled = config->Heci3Enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = is_dev_enabled(dev); #if !CONFIG(HECI_DISABLE_USING_SMM) dev = pcidev_path_on_root(PCH_DEVFN_CSE); params->Heci1Disabled = !is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/44579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Gerrit-Change-Number: 44579 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: mb/razer/blade_stealth_kbl: 1/3 Decode raw register values
by Maxim Polyakov (Code Review) 21 Sep '20

21 Sep '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43857 ) Change subject: mb/razer/blade_stealth_kbl: 1/3 Decode raw register values ...................................................................... mb/razer/blade_stealth_kbl: 1/3 Decode raw register values Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... ./intelp2m -fld cb -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h In the initial patch [3], gpio.h contains comments with additional information about the changes required to convert to macros. This can also be generated using the command: ./intelp2m -iiii -fld cb -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m": - 1/3 Decode raw register values - 2/3 Exclude fields for PAD_CFG - 3/3 Convert field macros to PAD_CFG [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 [3] Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 714 insertions(+), 153 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43857/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266dde..0c1cb04 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -8,160 +8,721 @@ #ifndef __ACPI__ -/* Pad configuration in ramstage. */ +/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), + /* GPP_A0 - RCIN# DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A1 - LAD0 DW0: 0x44000702, DW1: 0x00003c00 */ + /* PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + + /* GPP_A2 - LAD1 DW0: 0x44000702, DW1: 0x00003c00 */ + /* PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + + /* GPP_A3 - LAD2 DW0: 0x44000702, DW1: 0x00003c00 */ + /* PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + + /* GPP_A4 - LAD3 DW0: 0x44000702, DW1: 0x00003c00 */ + /* PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), + + /* GPP_A5 - LFRAME# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A6 - SERIRQ DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A7 - GPIO DW0: 0x84000102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_A7, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_A8 - CLKRUN# DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A9 - CLKOUT_LPC0 DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_A10 - CLKOUT_LPC1 DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_A11 - GPIO DW0: 0x40100102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), */ + _PAD_CFG_STRUCT(GPP_A11, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_A12 - GPIO DW0: 0x04000201, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_A12, 1, PWROK), */ + _PAD_CFG_STRUCT(GPP_A12, PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_A13 - SUSWARN# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A14 - SUS_STAT# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A15 - SUS_ACK# DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_A16 - SD_1P8_SEL DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A17 - SD_PWR_EN# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A18 - ISH_GP0 DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A19 - ISH_GP1 DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A20 - ISH_GP2 DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A21 - ISH_GP3 DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A22 - GPIO DW0: 0x44000201, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_A22, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_A22, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_A23 - GPIO DW0: 0x40100102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), */ + _PAD_CFG_STRUCT(GPP_A23, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_B0 - CORE_VID0 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B1 - CORE_VID1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B2 - VRALERT# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B3 - GPIO DW0: 0x80100100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), */ + _PAD_CFG_STRUCT(GPP_B3, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_B4 - GPIO DW0: 0x44000201, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_B4, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_B4, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B5 - SRCCLKREQ0# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B6 - SRCCLKREQ1# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B7 - SRCCLKREQ2# DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B8 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ + /* PAD_NC(GPP_B8, NONE), */ + _PAD_CFG_STRUCT(GPP_B8, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B9 - SRCCLKREQ4# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B10 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ + /* PAD_NC(GPP_B10, NONE), */ + _PAD_CFG_STRUCT(GPP_B10, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B11 - EXT_PWR_GATE# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B12 - SLP_S0# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B13 - PLTRST# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B14 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_B14, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + + /* GPP_B15 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_B15, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_B15, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_B16 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ + /* PAD_NC(GPP_B16, NONE), */ + _PAD_CFG_STRUCT(GPP_B16, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B17 - GPIO DW0: 0x42880100, DW1: 0x00001000 */ + /* PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), */ + _PAD_CFG_STRUCT(GPP_B17, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_B18 - GPIO DW0: 0x80880102, DW1: 0x00003000 */ + /* PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), */ + _PAD_CFG_STRUCT(GPP_B18, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), + + /* GPP_B19 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ + /* PAD_NC(GPP_B19, NONE), */ + _PAD_CFG_STRUCT(GPP_B19, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B20 - GSPI1_CLK DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_B21 - GSPI1_MISO DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_B22 - GSPI1_MOSI DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_B23 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_B23, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + + /* GPP_C0 - SMBCLK DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C1 - SMBDATA DW0: 0x44000702, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_C2 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_C2, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + + /* GPP_C3 - SML0CLK DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C4 - SML0DATA DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C5 - GPIO DW0: 0x40900100, DW1: 0x00001000 */ + /* PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_C5, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_C6 - RESERVED */ + + /* GPP_C7 - RESERVED */ + + /* GPP_C8 - UART0_RXD DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C9 - UART0_TXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C10 - UART0_RTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C11 - UART0_CTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C12 - UART1_RXD DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C13 - UART1_TXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C14 - UART1_RTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C15 - UART1_CTS# DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C16 - I2C0_SDA DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C17 - I2C0_SCL DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C18 - I2C1_SDA DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C19 - I2C1_SCL DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C20 - UART2_RXD DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C21 - UART2_TXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C22 - UART2_RTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C23 - UART2_CTS# DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D0 - SPI1_CS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D1 - SPI1_CLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D2 - SPI1_MISO DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D3 - SPI1_MOSI DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D4 - FLASHTRIG DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D5 - ISH_I2C0_SDA DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D6 - ISH_I2C0_SCL DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D7 - ISH_I2C1_SDA DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D8 - ISH_I2C1_SCL DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D9 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), */ + _PAD_CFG_STRUCT(GPP_D9, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_D10 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), */ + _PAD_CFG_STRUCT(GPP_D10, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_D11 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), */ + _PAD_CFG_STRUCT(GPP_D11, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_D12 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), */ + _PAD_CFG_STRUCT(GPP_D12, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_D13 - ISH_UART0_RXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D14 - ISH_UART0_TXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D15 - ISH_UART0_RTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D16 - ISH_UART0_CTS# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D17 - DMIC_CLK1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D18 - DMIC_DATA1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D19 - DMIC_CLK0 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D20 - DMIC_DATA0 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D21 - SPI1_IO2 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D22 - SPI1_IO3 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D23 - I2S_MCLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E0 - GPIO DW0: 0x42880100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), */ + _PAD_CFG_STRUCT(GPP_E0, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E1 - SATAXPCIE1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E2 - SATAXPCIE2 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E3 - GPIO DW0: 0x40000000, DW1: 0x00000000 */ + /* PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), */ + _PAD_CFG_STRUCT(GPP_E3, PAD_RESET(DEEP), 0), + + /* GPP_E4 - SATA_DEVSLP0 DW0: 0x04000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E5 - GPIO DW0: 0x82880102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), */ + _PAD_CFG_STRUCT(GPP_E5, PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E6 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_E6, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_E6, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_E7 - GPIO DW0: 0x80180102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), */ + _PAD_CFG_STRUCT(GPP_E7, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E8 - SATALED# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E9 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_E9, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_E9, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_E10 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_E10, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + + /* GPP_E11 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), */ + _PAD_CFG_STRUCT(GPP_E11, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + + /* GPP_E12 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ + /* PAD_NC(GPP_E12, NONE), */ + _PAD_CFG_STRUCT(GPP_E12, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E13 - DDPB_HPD0 DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E14 - DDPC_HPD1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E15 - GPIO DW0: 0x42840102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), */ + _PAD_CFG_STRUCT(GPP_E15, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E16 - GPIO DW0: 0x80880102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), */ + _PAD_CFG_STRUCT(GPP_E16, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E17 - EDP_HPD DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E18 - DDPB_CTRLCLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E19 - DDPB_CTRLDATA DW0: 0x44000700, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_E20 - DDPC_CTRLCLK DW0: 0x44000702, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E21 - DDPC_CTRLDATA DW0: 0x44000702, DW1: 0x00001000 */ + /* PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_E22 - GPIO DW0: 0x40900100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), */ + _PAD_CFG_STRUCT(GPP_E22, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_E23 - GPIO DW0: 0x84000200, DW1: 0x00001000 */ + /* PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), */ + _PAD_CFG_STRUCT(GPP_E23, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(20K_PD)), + + /* GPP_F0 - I2S2_SCLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F1 - I2S2_SFRM DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F2 - I2S2_TXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F3 - I2S2_RXD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F4 - I2C2_SDA DW0: 0x44000700, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F5 - I2C2_SCL DW0: 0x44000702, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F6 - I2C3_SDA DW0: 0x44000702, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F7 - I2C3_SCL DW0: 0x44000702, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F8 - I2C4_SDA DW0: 0x44000702, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F9 - I2C4_SCL DW0: 0x44000702, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F10 - ISH_I2C2_SDA DW0: 0x44000b02, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F11 - ISH_I2C2_SCL DW0: 0x44000b02, DW1: 0x02000000 */ + /* PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_CFG1_TOL_1V8), + + /* GPP_F12 - EMMC_CMD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F13 - GPIO DW0: 0x44000102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F13, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_F14 - GPIO DW0: 0x44000102, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F14, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_F15 - GPIO DW0: 0x44000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F15, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_F16 - EMMC_DATA3 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F17 - EMMC_DATA4 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F18 - EMMC_DATA5 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F19 - EMMC_DATA6 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F20 - EMMC_DATA7 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F21 - EMMC_RCLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F22 - EMMC_CLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F23 - GPIO DW0: 0x40100100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), */ + _PAD_CFG_STRUCT(GPP_F23, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G0 - SD_CMD DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G1 - SD_DATA0 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G2 - SD_DATA1 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G3 - SD_DATA2 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G4 - SD_DATA3 DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G5 - SD_CD# DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G6 - SD_CLK DW0: 0x44000700, DW1: 0x00000000 */ + /* PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), */ + /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G7 - GPIO DW0: 0x44000100, DW1: 0x00000000 */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G7, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c Gerrit-Change-Number: 43857 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Felix Singer (Code Review) 21 Sep '20

21 Sep '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/39995/15/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/smbios.c: PS15: > Please remove the whole file and use `SECUNET_DMI` instead. Kconfig select + […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 18 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 21 Sep 2020 15:19:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by build bot (Jenkins) (Code Review) 21 Sep '20

21 Sep '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39995 ) Change subject: mb/siemens/chili: Add Chili variant ...................................................................... Patch Set 18: (4 comments) https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/romstage.c: https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… PS18, Line 46: __weak void variant_romstage_params(FSPM_UPD *const mupd) need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… File src/mainboard/siemens/chili/variants/chili/gpio.c: https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… PS18, Line 44: /* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… PS18, Line 49: /* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ line over 96 characters https://review.coreboot.org/c/coreboot/+/39995/18/src/mainboard/siemens/chi… PS18, Line 95: /* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 18 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 21 Sep 2020 15:18:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/chili: Add Chili variant
by Felix Singer (Code Review) 21 Sep '20

21 Sep '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39995 to look at the new patch set (#18). Change subject: mb/siemens/chili: Add Chili variant ...................................................................... mb/siemens/chili: Add Chili variant This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Fac… Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/chili/Kconfig.name M src/mainboard/siemens/chili/mainboard.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variant.h A src/mainboard/siemens/chili/variants/chili/Makefile.inc A src/mainboard/siemens/chili/variants/chili/board_info.txt A src/mainboard/siemens/chili/variants/chili/data.vbt A src/mainboard/siemens/chili/variants/chili/devicetree.cb A src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads A src/mainboard/siemens/chili/variants/chili/gpio.c A src/mainboard/siemens/chili/variants/chili/hda_verb.c A src/mainboard/siemens/chili/variants/chili/romstage.c 13 files changed, 483 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39995/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/39995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Gerrit-Change-Number: 39995 Gerrit-PatchSet: 18 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2020