coreboot-gerrit July 2020

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Change in coreboot[master]: soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions
by Tim Wawrzynczak (Code Review) 15 Jul '20

15 Jul '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35406 ) Change subject: soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions ...................................................................... Patch Set 62: (1 comment) https://review.coreboot.org/c/coreboot/+/35406/62/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35406/62/src/soc/intel/common/bloc… PS62, Line 9: INTERMEDIATE+=add_intel_me_rw > Why? Looks like following the example at src/southbridge/intel/common/firmware/Makefile.inc for add_intel_firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/35406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Gerrit-Change-Number: 35406 Gerrit-PatchSet: 62 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 15 Jul 2020 15:41:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/board-status: Reject logs with unknown timestamps
by Paul Menzel (Code Review) 15 Jul '20

15 Jul '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41857 ) Change subject: util/board-status: Reject logs with unknown timestamps ...................................................................... util/board-status: Reject logs with unknown timestamps Check the output of `cbmem -t` for unknown timestamps. If present, ask the user to rebuild `cbmem`. Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/board_status/board_status.sh 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41857/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 2e93fe2..e772238 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -431,6 +431,11 @@ echo "Getting timestamp data" cmd_nonfatal $LOCAL "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt" + if [ $(grep -- unknown "${tmpdir}/${results}/coreboot_timestamps.txt") ]; then + echo "Unknown timestamps found in 'coreboot_timestamps.txt'." \ + "Please rebuild the utility 'cbmem'." + exit $EXIT_FAILURE + fi if [ "$cmos_enabled" -eq 1 ]; then echo "Verifying that nvramtool is available" -- To view, visit https://review.coreboot.org/c/coreboot/+/41857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40 Gerrit-Change-Number: 41857 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/depthcharge: Makefile: resolve fail of concurrent build
by Patrick Georgi (Code Review) 15 Jul '20

15 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43407 ) Change subject: payloads/depthcharge: Makefile: resolve fail of concurrent build ...................................................................... payloads/depthcharge: Makefile: resolve fail of concurrent build Resolve missing dependency to fix concurrent building. Resolves: https://ticket.coreboot.org/issues/271 Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/external/depthcharge/Makefile 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index c4dd1bf..60aa92d5 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -50,8 +50,7 @@ # Check out the requested version of the tree # Don't write a file for master branch so the latest remote version is always used -$(project_dir)/.version_$(TAG-y): - $(MAKE) fetch +$(project_dir)/.version_$(TAG-y): fetch echo " Checking out $(project_name) revision $(TAG-y)" rm -f $(project_dir)/.version_* cd $(project_dir); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/43407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0 Gerrit-Change-Number: 43407 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/depthcharge: Makefile: resolve fail of concurrent build
by Patrick Georgi (Code Review) 15 Jul '20

15 Jul '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43407 ) Change subject: payloads/depthcharge: Makefile: resolve fail of concurrent build ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0 Gerrit-Change-Number: 43407 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Jul 2020 10:33:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Update SPI from 66MHz, 112 to 100MHz, 122
by Martin Roth (Code Review) 15 Jul '20

15 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43306 ) Change subject: Update SPI from 66MHz, 112 to 100MHz, 122 ...................................................................... Update SPI from 66MHz, 112 to 100MHz, 122 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe --- M src/mainboard/google/zork/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43306/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 9db0d23..ca33bbd 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -140,11 +140,11 @@ # SPI Configuration register "common_config.spi_config" = "{ - .normal_speed = SPI_SPEED_66M, /* MHz */ - .fast_speed = SPI_SPEED_66M, /* MHz */ + .normal_speed = SPI_SPEED_100M, /* MHz */ + .fast_speed = SPI_SPEED_100M, /* MHz */ .altio_speed = SPI_SPEED_66M, /* MHz */ .tpm_speed = SPI_SPEED_66M, /* MHz */ - .read_mode = SPI_READ_MODE_DUAL112, + .read_mode = SPI_READ_MODE_DUAL122, }" # eSPI Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/43306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Gerrit-Change-Number: 43306 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Change Morphius SPI speed to 66mhz
by Rob Barnes (Code Review) 15 Jul '20

15 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43459 ) Change subject: mb/google/zork: Change Morphius SPI speed to 66mhz ...................................................................... mb/google/zork: Change Morphius SPI speed to 66mhz Morphius cannot support 100Mhz SPI. Downgrade to 66Mhz. BUG=b:161233767 TEST=Boot morphius Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/morphius/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/43459/1 diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index c0de2ce..4b6b20d 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -37,6 +37,15 @@ .early_init = true, }" + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL122, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/43459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402 Gerrit-Change-Number: 43459 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable SIS touchscreen for Waddledee
by Patrick Georgi (Code Review) 15 Jul '20

15 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43304 ) Change subject: mb/google/dedede: Enable SIS touchscreen for Waddledee ...................................................................... mb/google/dedede: Enable SIS touchscreen for Waddledee Add SiS9813 USI touchscreen support. BUG=b:160129126 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Justin TerAvest <teravest(a)chromium.org> Reviewed-by: Marco Chen <marcochen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved Marco Chen: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 10e66bb..f070fa1 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -66,6 +66,25 @@ device i2c 0x2c on end end end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""SIS6496"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end # I2C 2 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/43304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Gerrit-Change-Number: 43304 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: security/vboot: ensure that NVMEN is save before potential brownout
by Jett Rink (Code Review) 15 Jul '20

15 Jul '20

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43414 ) Change subject: security/vboot: ensure that NVMEN is save before potential brownout ...................................................................... security/vboot: ensure that NVMEN is save before potential brownout Before we ask the EC to perform a cold reboot, we need to ensure that the TPM has actually saved its NVMEN, since it batches up all of the writes until a later time. BRANCH=none BUG=b:160913048 TEST=Verify that puff will no longer reboot loop when coreboot writes a new Hmir (Hash mirror) in the TPM Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/security/vboot/ec_sync.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43414/1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 97b8ed9..f5816f3 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -6,6 +6,7 @@ #include <delay.h> #include <ec/google/chromeec/ec.h> #include <halt.h> +#include <security/tpm/tss.h> #include <security/vboot/misc.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> @@ -57,6 +58,10 @@ case VB2_REQUEST_REBOOT_EC_TO_RO: printk(BIOS_INFO, "EC Reboot requested. Doing cold reboot\n"); + + /* Since cold reboots may brown out, ensure TPM data is saved */ + tlcl_cr50_enable_nvcommits(); + if (google_chromeec_reboot(0, EC_REBOOT_COLD, 0)) printk(BIOS_EMERG, "Failed to get EC to cold reboot\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/43414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a Gerrit-Change-Number: 43414 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable SATA Port Dito Config
by Shaunak Saha (Code Review) 15 Jul '20

15 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42415 ) Change subject: mb/google/volteer: Enable SATA Port Dito Config ...................................................................... mb/google/volteer: Enable SATA Port Dito Config Enable SataPortsEnableDitoConfig for port 0 and 1. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42415/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8ff790e..baf4c97 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -98,6 +98,8 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[0]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/42415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 Gerrit-Change-Number: 42415 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: SATA Port Enable Dito Config
by Shaunak Saha (Code Review) 15 Jul '20

15 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42214 ) Change subject: soc/intel/tigerlake: SATA Port Enable Dito Config ...................................................................... soc/intel/tigerlake: SATA Port Enable Dito Config SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to assert the DEVSLP signal as soon as there are no commands outstanding to the device and the port specific Device Sleep idle timer has expired. And the Device Sleep Idle Timeout value (PxDEVSLP.DITO and PxDEVSLP.DM) is a port specific timeout value used by the HBA for determining when to assert the DEVSLP signal. It provides a mechanism for the HBA to apply a programmable amount of hysteresis so as to prevent the HBA from asserting the DEVSLP signal too quickly which may result in undesirable latencies. *PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier. Default is 15. *PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer and TGL RVP. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42214/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index ed09aaa..d920fc9 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -98,6 +98,18 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[8]; + /* Audio related */ uint8_t PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; @@ -308,11 +320,6 @@ */ uint8_t DmiPwrOptimizeDisable; - /* - * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. - * Default 0. Setting this to 1 disables the SATA Power Optimizer. - */ - uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357..c2c963f 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -202,6 +202,18 @@ params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* + * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. + * SataPortsDmVal is the DITO multiplier. Default is 15. + * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625. + */ + for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { + if (config->SataPortsEnableDitoConfig[i]) { + params->SataPortsDmVal[i] = 15; + params->SataPortsDitoVal[1] = 625; + } + } + /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/42214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db Gerrit-Change-Number: 42214 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020