Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39428
to look at the new patch set (#5).
Change subject: soc/xeon_sp: add configs to use common/gpio diver
......................................................................
soc/xeon_sp: add configs to use common/gpio diver
Allows the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.
This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1]
[1] https://review.coreboot.org/c/coreboot/+/39425
Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39428/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Gerrit-Change-Number: 39428
Gerrit-PatchSet: 5
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39425
to look at the new patch set (#5).
Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]
......................................................................
soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]
Adds definitions that allow to use the common GPIO driver to configure
the Lewisburg PCH pads. Using the GPIO configuration from common/gpio,
unlike the FSP-style definitions from Intel RefCode [1] definitions,
is more understandable and makes the motherboards code much cleaner. In
addition, we can use utilities, such as intetool, to analyze the
configuration of proprietary firmware to add support for new server
motherboards with Skylake-SP processors.
The pin layout in this patch corresponds to the driver in the Linux
kernel for Lewisburg PCH GPIO hardware [2]
[1] https://designintools.intel.com/product_p/stlgrn45.htm
[2] drivers/pinctrl/intel/pinctrl-lewisburg.c
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/acpi/gpio.asl
A src/soc/intel/xeon_sp/gpio.c
A src/soc/intel/xeon_sp/include/soc/gpio.h
A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
6 files changed, 1,108 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/5
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Tristan Hsieh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27528 )
Change subject: mediatek/mt8183: Separate bootblock from coreboot image
......................................................................
Abandoned
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Nicolas Boichat has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29250 )
Change subject: ec/google/chromeec: Add 2 strings to chromeos_log information
......................................................................
Abandoned
no-op after rebase.
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