coreboot-gerrit March 2020

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Change in coreboot[master]: soc/xeon_sp: add configs to use common/gpio diver
by Maxim Polyakov (Code Review) 12 Mar '20

12 Mar '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39428 to look at the new patch set (#5). Change subject: soc/xeon_sp: add configs to use common/gpio diver ...................................................................... soc/xeon_sp: add configs to use common/gpio diver Allows the use of the common/gpio driver to create Lewisburg PCH pad configurations for server motherboards with Skylake-SP processors. This patch should only be applied after adding Lewisburg PCH definitions to the soc/intel/xeon_sp code [1] [1] https://review.coreboot.org/c/coreboot/+/39425 Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39428/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13 Gerrit-Change-Number: 39428 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]
by Maxim Polyakov (Code Review) 12 Mar '20

12 Mar '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39425 to look at the new patch set (#5). Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP] ...................................................................... soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP] Adds definitions that allow to use the common GPIO driver to configure the Lewisburg PCH pads. Using the GPIO configuration from common/gpio, unlike the FSP-style definitions from Intel RefCode [1] definitions, is more understandable and makes the motherboards code much cleaner. In addition, we can use utilities, such as intetool, to analyze the configuration of proprietary firmware to add support for new server motherboards with Skylake-SP processors. The pin layout in this patch corresponds to the driver in the Linux kernel for Lewisburg PCH GPIO hardware [2] [1] https://designintools.intel.com/product_p/stlgrn45.htm [2] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi/gpio.asl A src/soc/intel/xeon_sp/gpio.c A src/soc/intel/xeon_sp/include/soc/gpio.h A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 6 files changed, 1,108 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mediatek/mt8183: Separate bootblock from coreboot image
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27528 ) Change subject: mediatek/mt8183: Separate bootblock from coreboot image ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f0725dbf74120a3b0ba09363f6b673b8d20be5d Gerrit-Change-Number: 27528 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/dedede: Enable trackpad support
by Varshit B Pandya (Code Review) 12 Mar '20

12 Mar '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39236 ) Change subject: mb/google/dedede: Enable trackpad support ...................................................................... mb/google/dedede: Enable trackpad support 1. Configure trackpad interrupt GPIO. 2. Set i2c0 configuration. 3. Add trackpad ACPI support. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 --- M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 2 files changed, 51 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/39236/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index f4fcd8d..2b93159 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -55,7 +55,7 @@ /* B2 : PROCHOT_ODL */ PAD_NC(GPP_B2, NONE), /* B3 : TRACKPAD_INT_ODL */ - PAD_NC(GPP_B3, NONE), + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 1a61143..9694d1a 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,5 +1,55 @@ chip soc/intel/tigerlake + device domain 0 on end + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 device pci 1c.7 on chip drivers/intel/wifi register "wake" = "GPE0_DW2_03" -- To view, visit https://review.coreboot.org/c/coreboot/+/39236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 Gerrit-Change-Number: 39236 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/kukui: Load and run dram init blob
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34872 ) Change subject: google/kukui: Load and run dram init blob ...................................................................... google/kukui: Load and run dram init blob Load dram.bin and run it for full dram calibration. If any error occurred, try default dram init flow. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Iad05a77e6353f37cd5ea897203d528762f44176e Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/include/soc/memlayout.ld 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/34872/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..d7621f1 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += dram.bin +dram.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/dram.bin +dram.bin-type := raw +dram.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..8521cf8 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,9 +19,45 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <string.h> #include "early_init.h" +#include <cbfs.h> +#include <console/console.h> + +DECLARE_REGION(dram_init_code) + +static int dram_blob_load_and_run(void) +{ + int (*dram_init)(void *); + size_t blob_size, region_size; + + region_size = _edram_init_code - _dram_init_code; + blob_size = cbfs_boot_load_file("dram.bin", _dram_init_code, + region_size, CBFS_TYPE_RAW); + if (blob_size == 0) { + printk(BIOS_ERR, "dram.bin not found\n"); + return -1; + } + + memset(_dram_init_code + blob_size, 0, region_size - blob_size); + + dram_init = (int (*)(void *))_dram_init_code; + + return dram_init(NULL); +} + +static void dram_config(void) +{ + int err = dram_blob_load_and_run(); + if (err == 0) + return; + + printk(BIOS_ERR, "dram_blob error:%d\n", err); + mt_mem_init(get_sdram_config()); +} + void platform_romstage_main(void) { /* This will be done in verstage if CONFIG_VBOOT is enabled. */ @@ -33,6 +69,6 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); - mt_mem_init(get_sdram_config()); + dram_config(); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 7da282e..9a71645 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -24,6 +24,8 @@ */ #define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) #define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) SECTIONS { @@ -43,6 +45,7 @@ DECOMPRESSOR(0x00201000, 28K) BOOTBLOCK(0x00208000, 64K) OVERLAP_VERSTAGE_ROMSTAGE(0x00218000, 160K) + DRAM_INIT_CODE(0x00240000, 256K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/34872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad05a77e6353f37cd5ea897203d528762f44176e Gerrit-Change-Number: 34872 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: DRAM freq switch to 2400Mbps
by Tristan Hsieh (Code Review) 12 Mar '20

12 Mar '20

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30613 Change subject: google/kukui: DRAM freq switch to 2400Mbps ...................................................................... google/kukui: DRAM freq switch to 2400Mbps Forcing DRAM frequency 2400Mbps. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/emi.c 3 files changed, 53 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30613/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d2..555bb02 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -17,8 +17,8 @@ struct sdram_params params = { .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} + [ODT_OFF] = {0x5, 0x6, 0x0, 0xF}, + [ODT_ON] = {0x6, 0x9, 0x0, 0xE} }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9197ceb..551205f 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -126,17 +126,17 @@ {&ch[0].phy.pll2, 0x00000000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607c0}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[0].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[0].dll[1], 0x00022401}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, {&ch[1].phy.shu[0].b[1].dll[1], 0x00022401}, {&ch[0].phy.shu[0].pll[4], 0xe5780000}, {&ch[0].phy.shu[0].pll[6], 0xe5780000}, @@ -146,15 +146,15 @@ {&ch[0].ao.dvfsdll, 0x00000000}, {&ch[0].phy.shu[0].ca_dll[0], 0x00698619}, {&ch[0].phy.shu[0].ca_dll[1], 0x0004e104}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.b[0].dq[7], 0x00000055}, {&ch[0].phy.b[1].dq[7], 0x00000055}, {&ch[0].phy.ca_cmd[7], 0x00000055}, {&ch[0].phy.ca_cmd[2], 0x00200000}, {&ch[0].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x000604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x000607C0}, {&ch[0].phy.pll4, 0x000c0000}, {&ch[0].phy.pll1, 0x00000000}, {&ch[0].phy.pll2, 0x00000000}, @@ -169,26 +169,26 @@ {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[0].phy.shu[0].pll[8], 0x00040000}, {&ch[0].phy.shu[0].pll[10], 0x00040000}, - {&ch[0].phy.shu[0].pll[5], 0x7b000002}, - {&ch[0].phy.shu[0].pll[7], 0x7b000002}, + {&ch[0].phy.shu[0].pll[5], 0x5c000002}, + {&ch[0].phy.shu[0].pll[7], 0x5c000002}, {&ch[0].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[0].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[0].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[0].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x028604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x02C607C0}, {&ch[0].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[0].phy.pll1, 0x80000000}, {&ch[0].phy.pll2, 0x80000000}, {&ch[0].phy.pll4, 0x004d0000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, {&ch[0].phy.ca_dll_fine_tune[3], 0x000ba000}, {&ch[0].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[0].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -208,14 +208,6 @@ {&ch[0].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[0].phy.shu[0].pll[5], 0x7b000003}, - {&ch[0].phy.shu[0].pll[7], 0x7b000003}, - {&ch[0].phy.shu[0].pll[14], 0x00000002}, - {&ch[0].phy.shu[0].pll20, 0x00000002}, - {&ch[0].phy.shu[0].pll[14], 0x02080002}, - {&ch[0].phy.shu[0].pll20, 0x02080002}, - {&ch[0].phy.shu[0].pll[15], 0x0c030000}, - {&ch[0].phy.shu[0].pll21, 0x0c030000}, {&ch[1].phy.shu[0].pll[4], 0x00000000}, {&ch[1].phy.shu[0].pll[6], 0x00000000}, {&ch[1].phy.misc_shu_opt, 0x00090909}, @@ -224,15 +216,15 @@ {&ch[1].ao.dvfsdll, 0x00000000}, {&ch[1].phy.shu[0].ca_dll[0], 0xc0778609}, {&ch[1].phy.shu[0].ca_dll[1], 0x0004e101}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.b[0].dq[7], 0x00000055}, {&ch[1].phy.b[1].dq[7], 0x00000055}, {&ch[1].phy.ca_cmd[7], 0x00000055}, {&ch[1].phy.ca_cmd[2], 0x00200000}, {&ch[1].phy.misc_cg_ctrl0, 0x0000000f}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x00060440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x00060440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x00060740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x00060740}, {&ch[1].phy.pll4, 0x00000000}, {&ch[1].phy.pll1, 0x00000000}, {&ch[1].phy.pll2, 0x00000000}, @@ -247,26 +239,26 @@ {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000000}, {&ch[1].phy.shu[0].pll[8], 0x00040000}, {&ch[1].phy.shu[0].pll[10], 0x00040000}, - {&ch[1].phy.shu[0].pll[5], 0x7b000000}, - {&ch[1].phy.shu[0].pll[7], 0x7b000000}, + {&ch[1].phy.shu[0].pll[5], 0x5c000000}, + {&ch[1].phy.shu[0].pll[7], 0x5c000000}, {&ch[1].phy.ca_dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x00000002}, {&ch[1].phy.ca_dll_fine_tune[1], 0x00200000}, {&ch[1].phy.b[0].dll_fine_tune[1], 0x00000000}, {&ch[1].phy.b[1].dll_fine_tune[1], 0x00000000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x02860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x02860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x02C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x02C60740}, {&ch[1].phy.ca_dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[0].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.b[1].dll_fine_tune[0], 0x0000000a}, {&ch[1].phy.pll1, 0x80000000}, {&ch[1].phy.pll2, 0x80000000}, {&ch[1].phy.pll4, 0x00410000}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&ch[1].phy.ca_dll_fine_tune[3], 0x0003a000}, {&ch[1].phy.b[0].dll_fine_tune[3], 0x0002e800}, {&ch[1].phy.b[1].dll_fine_tune[3], 0x0002e800}, @@ -286,14 +278,6 @@ {&ch[1].phy.ca_cmd[7], 0x00000040}, {&ch[0].ao.ckectrl, 0x00100400}, {&ch[1].ao.ckectrl, 0x00100400}, - {&ch[1].phy.shu[0].pll[5], 0x00000001}, - {&ch[1].phy.shu[0].pll[7], 0x00000001}, - {&ch[1].phy.shu[0].pll[14], 0x00000002}, - {&ch[1].phy.shu[0].pll20, 0x00000002}, - {&ch[1].phy.shu[0].pll[14], 0x02080000}, - {&ch[1].phy.shu[0].pll20, 0x02080000}, - {&ch[1].phy.shu[0].pll[15], 0x0c030000}, - {&ch[1].phy.shu[0].pll21, 0x0c030000}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.drsctrl, 0x20080000}, {&ch[0].ao.ckectrl, 0x08100400}, @@ -431,12 +415,12 @@ {&ch[0].ao.shu[0].rk[1].selph_dq[2], 0x33333333}, {&ch[0].ao.shu[0].rk[1].selph_dq[3], 0x33333333}, {&ch[0].ao.shu[0].dqsg_retry, 0x8120050c}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].ao.shu[0].dqs2dq_tx, 0x00000000}, {&ch[0].ao.shu[0].odtctrl, 0xc0010003}, - {&ch[0].phy.shu[0].b[0].dq[7], 0x00008090}, - {&ch[0].phy.shu[0].b[1].dq[7], 0x00008080}, + {&ch[0].phy.shu[0].b[0].dq[7], 0x0000B090}, + {&ch[0].phy.shu[0].b[1].dq[7], 0x0000B080}, {&ch[0].phy.r[0].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[1].b[0].rxdvs[2], 0x20000000}, {&ch[0].phy.r[0].b[1].rxdvs[2], 0x20000000}, @@ -468,10 +452,10 @@ {&ch[0].phy.b[0].dq[6], 0x010352e9}, {&ch[0].phy.b[1].dq[6], 0x010352e9}, {&ch[0].phy.ca_cmd[6], 0x00034269}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.b[0].dq[5], 0x82110e00}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, - {&ch[0].phy.b[1].dq[5], 0x82110e00}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.b[0].dq[5], 0x82110E00}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, + {&ch[0].phy.b[1].dq[5], 0x82110E00}, {&ch[0].phy.b[0].dq[8], 0x00000007}, {&ch[0].phy.b[1].dq[8], 0x00000007}, {&ch[0].phy.ca_cmd[9], 0x00010007}, @@ -502,16 +486,16 @@ {&ch[0].phy.ca_cmd[8], 0x00080a0a}, {&ch[0].ao.shu[0].misc, 0x0000f132}, {&ch[0].ao.shu[0].dqsg, 0x02a19800}, - {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000e}, - {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000e}, + {&ch[0].phy.shu[0].b[0].dq[5], 0x0030000E}, + {&ch[0].phy.shu[0].b[1].dq[5], 0x0030000E}, {&ch[0].phy.shu[0].ca_cmd[5], 0x00000000}, {&mt8183_infracfg->dramc_wbr, 0x00000000}, - {&ch[0].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[0].phy.shu[0].ca_cmd[6], 0x068604c0}, - {&ch[1].phy.shu[0].b[0].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].b[1].dq[6], 0x06860440}, - {&ch[1].phy.shu[0].ca_cmd[6], 0x06860440}, + {&ch[0].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[0].phy.shu[0].ca_cmd[6], 0x06C607C0}, + {&ch[1].phy.shu[0].b[0].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].b[1].dq[6], 0x06C60740}, + {&ch[1].phy.shu[0].ca_cmd[6], 0x06C60740}, {&mt8183_infracfg->dramc_wbr, 0x0000001f}, {&ch[0].ao.shu[0].impcal1, 0x81080004}, {&ch[0].ao.srefctrl, 0x4840f000}, @@ -600,10 +584,10 @@ /* dramc duty calibration */ {&ch[0].phy.shu[0].rk[0].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x00000000}, + {&ch[0].phy.shu[0].rk[0].ca_cmd[0], 0x11000000}, {&ch[0].phy.shu[0].rk[1].ca_cmd[1], 0x00000000}, - {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x00000000}, - {&ch[0].phy.shu[0].ca_cmd[3], 0x00000400}, + {&ch[0].phy.shu[0].rk[1].ca_cmd[0], 0x11000000}, + {&ch[0].phy.shu[0].ca_cmd[3], 0x00000600}, {&ch[0].phy.shu[0].rk[0].b[0].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[0].b[1].dq[1], 0x00110000}, {&ch[0].phy.shu[0].rk[1].b[0].dq[1], 0x00110000}, diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index bb617f9..4d05dd0 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -272,10 +272,10 @@ { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); + 0xff << 16, 0x48 << 16); clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, 0x5B << 0); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ac04080b32a84b8451910d309b43f2f1921d9a Gerrit-Change-Number: 30613 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/tigerlake: Configure L1Substates for PCH Root ports
by Wonkyu Kim (Code Review) 12 Mar '20

12 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39412 ) Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports ...................................................................... soc/intel/tigerlake: Configure L1Substates for PCH Root ports Set value for PcieRpL1Substates as the values are different in ES1(L1.1: 2) and ES2(MAX: 0 - FSP default or 4) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39412/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a6bcf08..6a0d290 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -122,6 +122,11 @@ * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe RP L1 substate + * 0: FSP default(Max), 1: Disable, 2: L1.1 3: L1.2 4:Max + */ + uint8_t PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0dae0fe..f53517d 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -113,6 +113,12 @@ } } + /* RP Configs */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (config->PcieRpL1Substates[i]) + params->PcieRpL1Substates[i] = config->PcieRpL1Substates[i] - 1; + } + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); if (dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/39412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Gerrit-Change-Number: 39412 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: soc/intel/tigerlake: Enable HDA through dev_enabled
by Srinidhi N Kaushik (Code Review) 12 Mar '20

12 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39441 ) Change subject: soc/intel/tigerlake: Enable HDA through dev_enabled ...................................................................... soc/intel/tigerlake: Enable HDA through dev_enabled Check for dev enabled status for HDA controller and update the UPD accordingly. BUG=151174264 BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/39441/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index f0f3b4c..4b9b007 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -28,6 +28,7 @@ { unsigned int i; uint32_t mask = 0; + const struct device *dev; /* Set IGD stolen size to 60MB. */ m_cfg->IgdDvmt50PreAlloc = 0xFE; @@ -70,7 +71,7 @@ * Skip IGD initialization in FSP if device * is disable in devicetree.cb. */ - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) m_cfg->InternalGfx = 0; else @@ -113,6 +114,12 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, -- To view, visit https://review.coreboot.org/c/coreboot/+/39441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 Gerrit-Change-Number: 39441 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: nb/intel/i945: Program CxODT value for each channel
by Patrick Georgi (Code Review) 12 Mar '20

12 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Program CxODT value for each channel ...................................................................... Patch Set 30: (5 comments) https://review.coreboot.org/c/coreboot/+/18548/28//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/18548/28//COMMIT_MSG@9 PS28, Line 9: raison > reason :-) Done https://review.coreboot.org/c/coreboot/+/18548/28//COMMIT_MSG@9 PS28, Line 9: programm > program Done https://review.coreboot.org/c/coreboot/+/18548/28//COMMIT_MSG@10 PS28, Line 10: for > drop "for" Done https://review.coreboot.org/c/coreboot/+/18548/28//COMMIT_MSG@10 PS28, Line 10: eually > equally Done https://review.coreboot.org/c/coreboot/+/18548/21/src/northbridge/intel/i94… File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/c/coreboot/+/18548/21/src/northbridge/intel/i94… PS21, Line 2460: if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && : sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) { > The logic is not the same as the new code. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Mar 2020 07:37:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/google/chromeec: Add 2 strings to chromeos_log information
by Nicolas Boichat (Code Review) 11 Mar '20

11 Mar '20

Nicolas Boichat has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29250 ) Change subject: ec/google/chromeec: Add 2 strings to chromeos_log information ...................................................................... Abandoned no-op after rebase. -- To view, visit https://review.coreboot.org/c/coreboot/+/29250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0db5d0f996ecc8813cab670826b852e8545b6389 Gerrit-Change-Number: 29250 Gerrit-PatchSet: 2 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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