Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39511 )
Change subject: util/inteltool: gpio add code for dumping GPIO Community cfg registers
......................................................................
Patch Set 1:
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39510 )
Change subject: util/inteltool: powermgt: add Sunrise Point config registers
......................................................................
Patch Set 1:
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39523 )
Change subject: util/inteltool: add code for dumping APIC registers
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39524 )
Change subject: util/inteltool: add code for dumping IO registers
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Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39427
to look at the new patch set (#9).
Change subject: mb/ocp/tiogapass: use common GPIO config [WIP]
......................................................................
mb/ocp/tiogapass: use common GPIO config [WIP]
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the common pad configuration from soc/inte/
common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions.
This patch adds the GPIO configuration, which has the format required by
the driver from common/gpio. The data for this was taken from the
inteltool register dump with AMI firmware and converted to macros using
intelp2m [3].
[1] https://review.coreboot.org/c/coreboot/+/39425
[2] https://review.coreboot.org/c/coreboot/+/39428
[3] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/bootblock.c
A src/mainboard/ocp/tiogapass/gpio.h
M src/mainboard/ocp/tiogapass/ramstage.c
M src/mainboard/ocp/tiogapass/romstage.c
5 files changed, 623 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/9
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel
......................................................................
Patch Set 30: Code-Review+1
Looks much prettier now 😄
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel
......................................................................
Patch Set 30:
> Patch Set 30:
>
> I've populated only channel 0 with 2 DIMMs
> as you can see, we have the message "C1ODT: Channel 1 has one DIMM."
> https://pastebin.com/9pxTYPQx
> The board boots but this patch does not what expected
That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1
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