Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 )
Change subject: src/soc/tigerlake: add S0ix support fsp_params
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39367/3/src/soc/intel/tigerlake/fsā¦
File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39367/3/src/soc/intel/tigerlake/fsā¦
PS3, Line 162: params->PmcLpmS0ixSubStateEnableMask = 0x09;
: params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0;
: params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0;
: params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0;
I would like to understand from Intel what these mean and why these are required?
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 )
Change subject: src/soc/tigerlake: add S0ix support fsp_params
......................................................................
Patch Set 3: Code-Review+2
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Matt Delco has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27612 )
Change subject: lib/nhlt: add missing size field
......................................................................
Abandoned
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel
......................................................................
Patch Set 30:
I've populated only channel 0 with 2 DIMMs
as you can see, we have the message "C1ODT: Channel 1 has one DIMM."
https://pastebin.com/9pxTYPQx
The board boots but this patch does not what expected
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Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39427
to look at the new patch set (#8).
Change subject: mb/ocp/tiogapass: use common GPIO config [WIP]
......................................................................
mb/ocp/tiogapass: use common GPIO config [WIP]
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the common pad configuration from soc/inte/
common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions.
This GPIO configuration was taken from the inteltool.log dump with AMI
firmware and converted to macros using intelp2m [3].
[1] https://review.coreboot.org/c/coreboot/+/39425
[2] https://review.coreboot.org/c/coreboot/+/39428
[3] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/bootblock.c
A src/mainboard/ocp/tiogapass/gpio.h
M src/mainboard/ocp/tiogapass/ramstage.c
M src/mainboard/ocp/tiogapass/romstage.c
D src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
6 files changed, 623 insertions(+), 1,031 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/8
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