coreboot-gerrit March 2020

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Change in coreboot[master]: [TEST DO NOT MERGE]other temp changes to fix error.
by Ronak Kanabar (Code Review) 13 Mar '20

13 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39198 ) Change subject: [TEST DO NOT MERGE]other temp changes to fix error. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I390c7838b1a4c75254687e4b09b26527f8e26236 Gerrit-Change-Number: 39198 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: Temp full gpio.c and devicetree.cb
by Ronak Kanabar (Code Review) 13 Mar '20

13 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39426 ) Change subject: Temp full gpio.c and devicetree.cb ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfdd1bbb0865d57161c6fba23d0543fd4619ddc0 Gerrit-Change-Number: 39426 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: temp error fix
by Ronak Kanabar (Code Review) 13 Mar '20

13 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39404 ) Change subject: temp error fix ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib078eb27d1c7e046d42b371d1aa6834fae12c57b Gerrit-Change-Number: 39404 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/intel/jasperlake_rvp: update chromeos.fmd
by Ronak Kanabar (Code Review) 13 Mar '20

13 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39197 ) Change subject: mb/intel/jasperlake_rvp: update chromeos.fmd ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b58333022d1f098f56b08bdbf6ea7503e8fce11 Gerrit-Change-Number: 39197 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/tigerlake: fix PCI interrupts for D31
by Wonkyu Kim (Code Review) 13 Mar '20

13 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39445 ) Change subject: soc/intel/tigerlake: fix PCI interrupts for D31 ...................................................................... soc/intel/tigerlake: fix PCI interrupts for D31 Fix interrupt for eSPI, P2SB, PMC and HDA Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Id37c88c1ed9436626651ebd22156403dd94978b7 --- M src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl M src/soc/intel/tigerlake/include/soc/irq_tgl.h 2 files changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39445/1 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl index 8aadf8d..6440127 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl @@ -17,10 +17,11 @@ #include <soc/irq.h> Name (PICP, Package () { - /* D31:HSA, SMBUS, TraceHUB */ + /* D31: eSPI, P2SB, PMC, HDA */ + Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, + Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, + Package(){0x001FFFFF, 2, 0, PMC_IRQ }, Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, /* D30: UART0, UART1, SPI0, SPI1 */ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h index 0ea6053..7d0bd95 100644 --- a/src/soc/intel/tigerlake/include/soc/irq_tgl.h +++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h @@ -36,9 +36,10 @@ #define LPSS_UART1_IRQ 35 #define LPSS_UART2_IRQ 33 -#define HDA_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 +#define eSPI_IRQ 16 +#define P2SB_IRQ 17 +#define PMC_IRQ 18 +#define HDA_IRQ 19 #define PCIE_1_IRQ 16 #define PCIE_2_IRQ 17 -- To view, visit https://review.coreboot.org/c/coreboot/+/39445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id37c88c1ed9436626651ebd22156403dd94978b7 Gerrit-Change-Number: 39445 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] USB Config dedede
by Ronak Kanabar (Code Review) 13 Mar '20

13 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39159 ) Change subject: [TEST] USB Config dedede ...................................................................... Abandoned it was test patch -- To view, visit https://review.coreboot.org/c/coreboot/+/39159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186e845ac7a4a5c88d047da7404629c520388b54 Gerrit-Change-Number: 39159 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: vboot: remove extraneous vboot_recovery_mode_memory_retrain
by Joel Kitching (Code Review) 12 Mar '20

12 Mar '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39343 ) Change subject: vboot: remove extraneous vboot_recovery_mode_memory_retrain ...................................................................... vboot: remove extraneous vboot_recovery_mode_memory_retrain Just call get_recovery_mode_retrain_switch() directly. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/mrc_cache/mrc_cache.c M src/security/vboot/bootmode.c M src/security/vboot/vboot_common.h M src/soc/mediatek/mt8183/memory.c 5 files changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39343/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 455dfa5..004b9e4 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -117,10 +117,10 @@ * 1. Recovery cache is not supported, or * 2. Memory retrain switch is set. */ - if (vboot_recovery_mode_enabled()) { + if (get_recovery_mode_retrain_switch()) { if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) return; - if (vboot_recovery_mode_memory_retrain()) + if (get_recovery_mode_retrain_switch()) return; } diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 2881a6f..565feb8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -516,7 +516,7 @@ /* Invalidate only on recovery mode with retraining enabled. */ if (!vboot_recovery_mode_enabled()) return; - if (!vboot_recovery_mode_memory_retrain()) + if (!get_recovery_mode_retrain_switch()) return; if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 55c1e79..c20117e 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -75,8 +75,3 @@ */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, do_clear_recovery_mode_switch, NULL); - -int vboot_recovery_mode_memory_retrain(void) -{ - return get_recovery_mode_retrain_switch(); -} diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 57f3475..8be9d2a 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -67,14 +67,12 @@ #if CONFIG(VBOOT) int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); -int vboot_recovery_mode_memory_retrain(void); int vboot_can_enable_udc(void); void vboot_run_logic(void); int vboot_locate_cbfs(struct region_device *rdev); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } -static inline int vboot_recovery_mode_memory_retrain(void) { return 0; } /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 78890ea..9b496fd 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -174,7 +174,7 @@ /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (vboot_recovery_mode_memory_retrain() || + if (get_recovery_mode_retrain_switch() || vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a Gerrit-Change-Number: 39343 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff
by Edward O'Callaghan (Code Review) 12 Mar '20

12 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39461 ) Change subject: mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff ...................................................................... mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff Early ec sync needs to be disabled for EFS2 to function. BUG=b:151115320 BRANCH=none TEST=none Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39461/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 92d94db..6ae79b9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -128,7 +128,8 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - select VBOOT_EARLY_EC_SYNC + # FIXME: allow kconfig to select on a subset of boards only + select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_PUFF select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/39461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19 Gerrit-Change-Number: 39461 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table
by John Zhao (Code Review) 12 Mar '20

12 Mar '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38165 ) Change subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table ...................................................................... soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR acpi table. BUG=None TEST=Booted to kernel and verified the DMAR table contents. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c 6 files changed, 184 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38165/1 diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5e04c9a..9254bd6 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -18,6 +18,8 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> +#include <console/console.h> +#include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> @@ -28,6 +30,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #include <string.h> #include <wrdd.h> @@ -190,6 +193,97 @@ return read32((void *)pmc_bar + IRQ_REG); } +static unsigned long soc_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (int i = 0; i < 4; i++) { + uint64_t tbtbar = MCHBAR64(TBT0BAR + i*8) & VTBAR_MASK; + bool tbten = MCHBAR32(TBT0BAR + i*8) & VTBAR_ENABLED; + if (tbtbar && tbten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() -1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if we have VT-d capability + * and FSP does not override its feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + void acpi_create_gnvs(struct global_nvs_t *gnvs) { config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index b3797c1..4f938fa 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -49,6 +49,27 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + #define REG_BASE_ADDRESS 0xfc000000 #define REG_BASE_SIZE 0x1000 diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b..2aa5d9e 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -43,6 +43,10 @@ #define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) #define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 56a2bd8..9b23a0b 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -34,10 +34,22 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) #define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 @@ -47,4 +59,21 @@ #define IMRBASE 0x6A40 #define IMRLIMIT 0x6A48 +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + #endif diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 810cff4..bb9b7b7 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -14,9 +14,36 @@ */ #include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> + +static void soc_fspm_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_tigerlake_dev_config *config) +{ + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; +} void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* TODO: Update with UPD override as FSP matures */ + const struct soc_intel_tigerlake_dev_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_fspm_params(m_cfg, config); } + diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f645..cb9ea18 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> @@ -56,6 +57,13 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/38165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib89d0835385487735c63062a084794d9da19605e Gerrit-Change-Number: 38165 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
by Srinidhi N Kaushik (Code Review) 12 Mar '20

12 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39315 ) Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ...................................................................... mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation This changes uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4b5a39..9506738 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,7 +121,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on end # I2C0 0xA0E8 device pci 15.1 on end # I2C1 0xA0E9 device pci 15.2 on end # I2C2 0xA0EA -- To view, visit https://review.coreboot.org/c/coreboot/+/39315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Gerrit-Change-Number: 39315 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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