coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC detection support
by Jonathan Kollasch (Code Review) 19 Mar '20

19 Mar '20

Jonathan Kollasch has uploaded a new patch set (#10) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/22214 ) Change subject: nb/intel/sandybridge/raminit: Add ECC detection support ...................................................................... nb/intel/sandybridge/raminit: Add ECC detection support Add support for detection ECC capability and forced ECC mode. Print the ECC mode in verbose debugging mode. Change-Id: … [View More]

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Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters
by Johnny Lin (Code Review) 19 Mar '20

19 Mar '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39625 ) Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters ...................................................................... soc/intel/xeon_sp: Modify FSP-T code caching parameters With a hard-coded CBFS_SIZE can solve the booting issue on Tioga Pass, a more ideal way can be explored in the future. Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424 Signed-off-by: Johnny … [View More]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/22/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/board_id.c: https://review.coreboot.org/c/coreboot/+/39195/22/src/mainboard/intel/jaspe… PS22, … [View More]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has uploaded a new patch set (#26) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and … [View More]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has uploaded a new patch set (#25) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and … [View More]another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/board_id.c M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c 8 files changed, 197 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 25 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset [View Less]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by build bot (Jenkins) (Code Review) 19 Mar '20

19 Mar '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 24: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/24/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/24/src/mainboard/intel/… [View More]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has uploaded a new patch set (#24) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and … [View More]another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/board_id.c M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c 8 files changed, 197 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 24 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset [View Less]

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 23: (6 comments) https://review.coreboot.org/c/coreboot/+/39195/21/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/board_id.c: https://review.coreboot.org/c/coreboot/+/39195/21/src/mainboard/intel/jaspe… PS21,… [View More]

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Change in coreboot[master]: jasperlake_rvp: Update UART config for JSLRVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: Update UART config for JSLRVP ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/Kconfig: https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe… PS11, Line 53: default 0 … [View More]

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Change in coreboot[master]: mb/scaleway/tagada: Use bmcInfo to enable Relaxed Security Mode
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25438 ) Change subject: mb/scaleway/tagada: Use bmcInfo to enable Relaxed Security Mode ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/25438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-… [View More]

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coreboot-gerrit March 2020