coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Documentation/Intel: s5 charging applet design document
by Furquan Shaikh (Code Review) 18 Mar '20

18 Mar '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37762 ) Change subject: Documentation/Intel: s5 charging applet design document ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/37762/4/Documentation/soc/intel/s5… File Documentation/soc/intel/s5_charging_applet/s5_charging_applet.md: https://review.coreboot.org/c/coreboot/+/37762/4/Documentation/soc/intel/s5… PS4, Line 84: We can display charging screen after graphics PEIM execution has finished after fsp-s. > I guess we are here dealing with entire PCI enumeration vs not doing PCI enumeration. Is there data on how much extra power is consumed during that time? -- To view, visit https://review.coreboot.org/c/coreboot/+/37762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb0d70d81890a60212c914b6bc2bfc7e35479ba9 Gerrit-Change-Number: 37762 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 05:39:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: add support to read SPD data from SMBus
by Aamir Bohra (Code Review) 18 Mar '20

18 Mar '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39401 ) Change subject: soc/intel/tigerlake: add support to read SPD data from SMBus ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Mar 2020 05:39:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/Intel: s5 charging applet design document
by Subrata Banik (Code Review) 18 Mar '20

18 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37762 ) Change subject: Documentation/Intel: s5 charging applet design document ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/37762/4/Documentation/soc/intel/s5… File Documentation/soc/intel/s5_charging_applet/s5_charging_applet.md: https://review.coreboot.org/c/coreboot/+/37762/4/Documentation/soc/intel/s5… PS4, Line 84: We can display charging screen after graphics PEIM execution has finished after fsp-s. > If we are waiting until FSP-S i.e. […] I guess we are here dealing with entire PCI enumeration vs not doing PCI enumeration. https://review.coreboot.org/c/coreboot/+/37762/4/Documentation/soc/intel/s5… PS4, Line 86: charging applet onto screen. > coreboot is about only initializing the necessary hardware, so payloads can start. […] As long as we are not mandatorily making S5 charging applet implementation for all platform, its not violating the spec. its an option like other bootloader has for modern OS tablet usecase, we have added this feature, if we are not intended to enable this for certain platform, then don't select the required Kconfig but i don't think we can say no to innovation in coreboot space as violation of previous assumptions -- To view, visit https://review.coreboot.org/c/coreboot/+/37762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb0d70d81890a60212c914b6bc2bfc7e35479ba9 Gerrit-Change-Number: 37762 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 03:52:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Set BIOS_REGION_SIZE for FSP-T code caching
by Johnny Lin (Code Review) 18 Mar '20

18 Mar '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39628 ) Change subject: mb/ocp/tiogapass: Set BIOS_REGION_SIZE for FSP-T code caching ...................................................................... mb/ocp/tiogapass: Set BIOS_REGION_SIZE for FSP-T code caching Tested on OCP Tioga Pass. Change-Id: Id6070974db1db54cb12109044a1f720ee7585a1f Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/tiogapass/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39628/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 87e2760..017d8c2 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -41,4 +41,8 @@ string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" +config BIOS_REGION_SIZE + hex + default 0x1000000 + endif # BOARD_OCP_TIOGAPASS -- To view, visit https://review.coreboot.org/c/coreboot/+/39628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6070974db1db54cb12109044a1f720ee7585a1f Gerrit-Change-Number: 39628 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

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Change in coreboot[master]: assert.h: add assertions with descriptive failuresx
by Felix Held (Code Review) 18 Mar '20

18 Mar '20

Hello Eric Peers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39620 to review the following change. Change subject: assert.h: add assertions with descriptive failuresx ...................................................................... assert.h: add assertions with descriptive failuresx BUG=None TEST=tested in following patches on Trembyle board Change-Id: Ib30ccd41759e5a2a61d3182cc08ed5eb762eca98 Signed-off-by: Eric Peers <epeers(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/1971443 Tested-by: Martin Roth <martinroth(a)chromium.org> Reviewed-by: Martin Roth <martinroth(a)chromium.org> --- M src/include/assert.h 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39620/1 diff --git a/src/include/assert.h b/src/include/assert.h index 8f5af1f..990cee1 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -33,6 +33,17 @@ hlt(); \ } \ } + +#define ASSERT_MSG(x, msg) { \ + if (!(x)) { \ + printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ + ", line %d\n", __FILE__, __LINE__); \ + printk(BIOS_EMERG, "%s", msg); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ +} + #define BUG() { \ printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ ", line %d\n", __FILE__, __LINE__); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/39620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib30ccd41759e5a2a61d3182cc08ed5eb762eca98 Gerrit-Change-Number: 39620 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: utin/lint/spelling.txt: Disable `afe`
by Angel Pons (Code Review) 18 Mar '20

18 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39619 ) Change subject: utin/lint/spelling.txt: Disable `afe` ...................................................................... utin/lint/spelling.txt: Disable `afe` Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid spelling, comment out its entry to prevent false positives. Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/lint/spelling.txt 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39619/1 diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 58fe30d..8738077 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -12,6 +12,9 @@ # Reason: Both spellings are correct. #acknowledgement||acknowledgment # +# Reason: AFE means `Analog Front-End`, and appears on register names. +#afe||safe +# # Reason: On RISC-V, `SEPC` is the name of a register. #sepc||spec # @@ -343,7 +346,6 @@ adviced||advised afecting||affecting afer||after -afe||safe affortable||affordable afforts||affords affort||afford -- To view, visit https://review.coreboot.org/c/coreboot/+/39619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6 Gerrit-Change-Number: 39619 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add CPUID of newer device
by Felix Held (Code Review) 18 Mar '20

18 Mar '20

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39617 to review the following change. Change subject: soc/amd/picasso: Add CPUID of newer device ...................................................................... soc/amd/picasso: Add CPUID of newer device Add a new device (Family 17h Models 20h-2Fh) to the cpu driver. Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Signed-off-by: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1950713 Reviewed-by: Martin Roth <martinroth(a)chromium.org> Tested-by: Martin Roth <martinroth(a)chromium.org> --- M src/soc/amd/picasso/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39617/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 66dfa6c..7831d3d 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -131,6 +131,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x810f80 }, { X86_VENDOR_AMD, 0x810f81 }, + { X86_VENDOR_AMD, 0x820f01 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/39617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Gerrit-Change-Number: 39617 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma: hook up GMA for Skylake+
by Benjamin Doron (Code Review) 18 Mar '20

18 Mar '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39638 ) Change subject: drivers/intel/gma: hook up GMA for Skylake+ ...................................................................... Patch Set 5: Code-Review-1 Nico: Would you really prefer local variables in common to entries in the globalnvs OpRegion? Past platforms used the latter. In any case, this presently redefines ACPI platforms on older platforms, so something will need correcting. -- To view, visit https://review.coreboot.org/c/coreboot/+/39638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2f0e8fe1ef91334d494c8a8605dd46cda80e3d Gerrit-Change-Number: 39638 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Mar 2020 21:47:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/haswell: Tidy up code and comments
by Angel Pons (Code Review) 18 Mar '20

18 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39599 ) Change subject: nb/intel/haswell: Tidy up code and comments ...................................................................... nb/intel/haswell: Tidy up code and comments - Reformat some lines of code - Move MCHBAR registers into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) Tested, it does not change the binary of Asus P8Z77-V LX2. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c A src/northbridge/intel/sandybridge/mchbar_regs.h M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.h M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/sandybridge/sandybridge.h 15 files changed, 1,509 insertions(+), 1,425 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39599/1 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index b6ba395..998b524 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -20,16 +20,14 @@ uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the + * The "io" variant of the config access is explicitly used to setup the + * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all + * subsequent non-explicit config accesses use MCFG. This code also assumes + * that bootblock_northbridge_init() is the first thing called in the non-asm + * boot block code. The final assumption is that no assembly code is using the * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = 0; pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 7dddb8a..34b25ec 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -20,9 +20,9 @@ /* * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse + * 0x04 = Enabled, 2ms short pulse * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse + * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ struct northbridge_intel_sandybridge_config { @@ -49,7 +49,7 @@ struct i915_gpu_controller_info gfx; /* - * Maximum PCI mmio size in MiB. + * Maximum PCI MMIO size in MiB. */ u16 pci_mmio_size; @@ -64,7 +64,8 @@ bool ec_present; bool ddr3lv_support; - /* N mode functionality. Leave this setting at 0. + /* + * N mode functionality. Leave this setting at 0. * 0 Auto * 1 1N * 2 2N @@ -75,12 +76,13 @@ DDR_NMODE_2N, } nmode; - /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows - * for DIMM SPD data to specify whether double-rate is required for - * extended operating temperature range. - * 0 Enable double rate based upon temperature thresholds - * 1 Normal rate - * 2 Always enable double rate + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to + * specify whether double-rate is required for extended operating temperature range. + * + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate */ enum { DDR_REFRESH_RATE_TEMP_THRES = 0, @@ -94,7 +96,7 @@ * [1] = overcurrent pin * [2] = length * - * Ports 0-7 can be mapped to OC0-OC3 + * Ports 0-7 can be mapped to OC0-OC3 * Ports 8-13 can be mapped to OC4-OC7 * * Port Length diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index e966095c..627aa42 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -29,17 +29,17 @@ static void systemagent_vtd_init(void) { - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); if (capid0_a & (1 << 23)) return; - /* setup BARs */ + /* Setup BARs */ MCHBAR32(VTD1_BASE + 4) = IOMMU_BASE1 >> 32; MCHBAR32(VTD1_BASE) = IOMMU_BASE1 | 1; MCHBAR32(VTD2_BASE + 4) = IOMMU_BASE2 >> 32; MCHBAR32(VTD2_BASE) = IOMMU_BASE2 | 1; - /* lock policies */ + /* Lock policies */ write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); const struct device *const azalia = pcidev_on_root(0x1b, 0); @@ -53,25 +53,25 @@ static void enable_pam_region(void) { - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); } static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); printk(BIOS_DEBUG, " done\n"); } @@ -83,7 +83,7 @@ u8 reg8; u8 gfxsize; - reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); + reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID); switch (reg16) { case 0x0102: /* GT1 Desktop */ case 0x0106: /* GT1 Mobile */ @@ -109,7 +109,7 @@ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ gfxsize = 0; } - reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); + reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; reg16 |= (gfxsize + 1) << 3; /* Program GTT memory by setting GGC[9:8] = 2MB */ @@ -117,7 +117,7 @@ reg16 |= 2 << 8; /* Enable VGA decode */ reg16 &= ~0x0002; - pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); + pci_write_config16(HOST_BRIDGE, GGC, reg16); /* Enable 256MB aperture */ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); @@ -127,7 +127,7 @@ /* Erratum workarounds */ reg32 = MCHBAR32(SAPMCTL); - reg32 |= (1 << 9)|(1 << 10); + reg32 |= (1 << 9) | (1 << 10); MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ @@ -154,14 +154,15 @@ u32 tmp; u32 deven; - /* PEG on IvyBridge+ needs a special startup sequence. - * As the MRC has its own initialization code skip it. */ - if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & - BASE_REV_MASK) != BASE_REV_IVB) || - CONFIG(HAVE_MRC)) + /* + * PEG on IvyBridge+ needs a special startup sequence. + * As the MRC has its own initialization code skip it. + */ + if (((pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK) != BASE_REV_IVB) + || CONFIG(HAVE_MRC)) return; - deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + deven = pci_read_config32(HOST_BRIDGE, DEVEN); if (deven & DEVEN_PEG10) { tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); @@ -191,17 +192,17 @@ u8 reg8; /* Device ID Override Enable should be done very early */ - capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + capid0_a = pci_read_config32(HOST_BRIDGE, 0xe4); if (capid0_a & (1 << 10)) { const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); + reg8 = pci_read_config8(HOST_BRIDGE, 0xf3); reg8 &= ~7; /* Clear 2:0 */ if (is_mobile) reg8 |= 1; /* Set bit 0 */ - pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); + pci_write_config8(HOST_BRIDGE, 0xf3, reg8); } /* Setup all BARs required for early PCIe and raminit */ @@ -214,18 +215,19 @@ systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); + deven = pci_read_config32(HOST_BRIDGE, DEVEN) | DEVEN_IGD; + pci_write_config32(HOST_BRIDGE, DEVEN, deven); sandybridge_setup_graphics(); - /* Write magic value to start PEG link training. - * This should be done in PCI device enumeration, but - * the PCIe specification requires to wait at least 100msec - * after reset for devices to come up. - * As we don't want to increase boot time, enable it early and - * assume the PEG is up as soon as PCI enumeration starts. - * TODO: use time stamps to ensure the timings are met */ + /* + * Write magic value to start PEG link training. This should be done in PCI device + * enumeration, but the PCIe specification requires to wait at least 100msec after + * reset for devices to come up. As we don't want to increase boot time, enable it + * early and assume the PEG is up as soon as PCI enumeration starts. + * + * TODO: use timestamps to ensure the timings are met. + */ start_peg_link_training(); } diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index e338372..8bd2270 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -17,36 +17,34 @@ #include <device/pci_ops.h> #include "sandybridge.h" -#define PCI_DEV_SNB PCI_DEV(0, 0, 0) - void intel_sandybridge_finalize_smm(void) { - pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); - pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); - pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK); - pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); - pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOUUD, 1 << 0); - pci_or_config32(PCI_DEV_SNB, BDSM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, BGSM, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0); - pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0); + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config16(HOST_BRIDGE, PAVPC, 1 << 2); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_MASK, MELCK); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(MMIO_PAVP_CTL, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(REQLIM, 1 << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); } diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h new file mode 100644 index 0000000..312b84e --- /dev/null +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ +#define __SANDYBRIDGE_MCHBAR_REGS_H__ + +/* Indexed register helper macros */ +#define Gz(r, z) ((r) + ((z) << 8)) +#define Ly(r, y) ((r) + ((y) << 2)) +#define Cx(r, x) ((r) + ((x) << 10)) +#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) +#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) + +/* Byte lane training register base addresses */ +#define LANEBASE_B0 0x0000 +#define LANEBASE_B1 0x0200 +#define LANEBASE_B2 0x0400 +#define LANEBASE_B3 0x0600 +#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ +#define LANEBASE_B4 0x1000 +#define LANEBASE_B5 0x1200 +#define LANEBASE_B6 0x1400 +#define LANEBASE_B7 0x1600 + +/* Byte lane register offsets */ +#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ +#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ +#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ +#define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ +#define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ + +/* Register definitions */ +#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ +#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ +#define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ +#define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ +#define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ +#define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ + +#define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ + +#define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ + +#define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ +#define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ +#define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) + +#define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ +#define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ +#define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ +#define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ + +#define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ +#define GDCRDATACOMP 0x340c /* COMP values register */ + +#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ + +/* MC per-channel registers */ +#define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ +#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ +#define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ +#define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ +#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ +#define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ +#define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ + +/* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) + +/* IOSAV Bytelane Bit-wise compare mask */ +#define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) +#define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ +#define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ + +#define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ + +/* IOSAV sub-sequence control registers */ +#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ +#define IOSAV_n_ADDR_UPDATE_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ +#define IOSAV_n_SP_CMD_CTRL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ +#define IOSAV_n_SUBSEQ_CTRL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ +#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ + +#define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ +#define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ +#define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ +#define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ +#define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ +#define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ +#define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ +#define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ + +#define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ +#define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define IOSAV_BYTE_SERROR_ch(ch) Cx(0x4368, ch) /** Byte-Wise Sticky Error */ +#define IOSAV_BYTE_SERROR_C_ch(ch) Cx(0x436c, ch) /** Byte-Wise Sticky Error Clear */ + +#define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ +#define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ +#define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ + +/* MC Channel Broadcast registers */ +#define TC_DBP 0x4c00 /* Timings: BIN */ +#define TC_RAP 0x4c04 /* Timings: Regular access */ +#define TC_RWP 0x4c08 /* Timings: Read / Write */ +#define TC_OTHP 0x4c0c /* Timings: Other parameters */ +#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ +#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ +#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ +#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ +#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ +#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ +#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ + +#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ +#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ + +/* + * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. + * Different counters for transactions that are issued on the ring agents (core or GT) and + * transactions issued in the SA. + */ +#define SC_PR_CNT_CONFIG 0x4ca8 +#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ +#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ +#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ +#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ +#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ + +/** Opportunistic reads configuration during write-major-mode (WMM) */ +#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ + +#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ + +#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ +#define IOSAV_n_ADDR_UPDATE(n) Ly(0x4e10, n) /* Address update after command execution */ +#define IOSAV_n_SP_CMD_CTRL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ +#define IOSAV_n_SUBSEQ_CTRL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ +#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ + +#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ +#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ +#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ +#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ +#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ +#define TC_RFP 0x4e94 /* Refresh Parameters */ +#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ +#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ +#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ +#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ + +/** + * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this + * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. + */ +#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ + +#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ +#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ + +#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ +#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define IOSAV_BYTE_SERROR 0x4f68 /** Byte-Wise Sticky Error */ +#define IOSAV_BYTE_SERROR_C 0x4f6c /** Byte-Wise Sticky Error Clear */ + +#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ +#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ +#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ +#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ + +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ +#define MAD_ZR 0x5014 /* Address Decode Zones */ +#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ +#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ + +#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ + +#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ +#define MRC_REVISION 0x5034 /* MRC Revision */ +#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ +#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define GFXVTBAR 0x5400 /* Base address for IGD */ +#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ + +#define VTD1_BASE 0x5400 /* Base address for IGD */ +#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ + +/* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ +#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ + +/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ +#define PAVP_MSG 0x5500 + +#define MEM_TRML_ESTIMATION_CONFIG 0x5880 +#define MEM_TRML_THRESHOLDS_CONFIG 0x5888 +#define MEM_TRML_INTERRUPT 0x58a8 + +/* Some power MSRs are also represented in MCHBAR */ +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ +#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ + +#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +/* PCODE will sample SAPM-related registers at the end of Phase 4. */ +#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ +#define M_COMP 0x5f08 /* Memory COMP control */ +#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ + +/* WARNING: Only applies to Sandy Bridge! */ +#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ +#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ + +/* Finalize registers. The names come from Haswell, as the finalize sequence is the same. */ +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define CRDTLCK 0x77fc + +#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 0784c11..965c145 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -27,7 +27,7 @@ static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB); + uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEGMB); return tom; } @@ -38,7 +38,7 @@ static uintptr_t northbridge_get_tseg_base(void) { - return ALIGN_DOWN(smm_region_start(), 1*MiB); + return ALIGN_DOWN(smm_region_start(), 1 * MiB); } static size_t northbridge_get_tseg_size(void) @@ -49,24 +49,27 @@ void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - top_of_ram = (uintptr_t)cbmem_top(); - /* Cache 8MiB below the top of ram. On sandybridge systems the top of + /* + * Cache 8MiB below the top of ram. On sandybridge systems the top of * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later - * for ramstage before setting up the entire RAM as cacheable. */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + * for ramstage before setting up the entire RAM as cacheable. + */ + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems + /* + * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. */ - postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + * handler as well as using the TSEG region for other purposes. + */ + postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4ec8492..46461a9 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -38,47 +38,48 @@ #define MRC_CACHE_VERSION 1 -/* FIXME: no ECC support. */ -/* FIXME: no support for 3-channel chipsets. */ +/* FIXME: no ECC support */ +/* FIXME: no support for 3-channel chipsets */ static const char *ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", - "active" + "active", }; static void wait_txt_clear(void) { - struct cpuid_result cp; + struct cpuid_result cp = cpuid_ext(1, 0); - cp = cpuid_ext(0x1, 0x0); - /* Check if TXT is supported? */ - if (!(cp.ecx & 0x40)) + /* Check if TXT is supported */ + if (!(cp.ecx & (1 << 6))) return; - /* Some TXT public bit. */ + + /* Some TXT public bit */ if (!(read32((void *)0xfed30010) & 1)) return; - /* Wait for TXT clear. */ - while (!(read8((void *)0xfed40000) & (1 << 7))); + + /* Wait for TXT clear */ + while (!(read8((void *)0xfed40000) & (1 << 7))) + ; } -/* - * Disable a channel in ramctr_timing. - */ -static void disable_channel(ramctr_timing *ctrl, int channel) { +/* Disable a channel in ramctr_timing */ +static void disable_channel(ramctr_timing *ctrl, int channel) +{ ctrl->rankmap[channel] = 0; + memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); + ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); + ctrl->cmd_stretch[channel] = 0; + ctrl->mad_dimm[channel] = 0; + memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } -/* - * Fill cbmem with information for SMBIOS type 17. - */ +/* Fill cbmem with information for SMBIOS type 17 */ static void fill_smbios17(ramctr_timing *ctrl) { int channel, slot; @@ -92,54 +93,49 @@ } } -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i, refclk; + int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 0) & 3, + (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, - ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? 16 : 8, ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? 16 : 8, ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } } -/* - * Return CRC16 match for all SPDs. - */ +/* Return CRC16 match for all SPDs */ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int channel, slot, spd_slot; @@ -149,7 +145,7 @@ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); } } return match; @@ -169,7 +165,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { - int dimms = 0, dimms_on_channel; + int dimms = 0, ch_dimms; int channel, slot, spd_slot; dimm_info *dimm = &ctrl->info; @@ -181,53 +177,55 @@ FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; - dimms_on_channel = 0; - /* count dimms on channel */ + ch_dimms = 0; + /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, - "SPD probe channel%d, slot%d\n", channel, slot); + printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) - dimms_on_channel++; + ch_dimms++; } for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, - "SPD probe channel%d, slot%d\n", channel, slot); + printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); - /* search for XMP profile */ - spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], - spd[spd_slot], + /* Search for XMP profile */ + spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot], DDR3_XMP_PROFILE_1); if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { printram("No valid XMP profile found.\n"); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - } else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) { - printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", - dimm->dimm[channel][slot].dimms_per_channel, - dimms_on_channel); + + } else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) { + printram( + "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", + dimm->dimm[channel][slot].dimms_per_channel, ch_dimms); + if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) - printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); + printk(BIOS_WARNING, + "XMP maximum DIMMs will be ignored.\n"); else - spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + spd_decode_ddr3(&dimm->dimm[channel][slot], + spd[spd_slot]); + } else if (dimm->dimm[channel][slot].voltage != 1500) { - /* TODO: support other DDR3 voltage than 1500mV */ + /* TODO: Support DDR3 voltages other than 1500mV */ printram("XMP profile's requested %u mV is unsupported.\n", dimm->dimm[channel][slot].voltage); spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } - /* fill in CRC16 for MRC cache */ + /* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { - // set dimm invalid - dimm->dimm[channel][slot].ranks = 0; + /* Mark DIMM as invalid */ + dimm->dimm[channel][slot].ranks = 0; dimm->dimm[channel][slot].size_mb = 0; continue; } @@ -235,30 +233,40 @@ dram_print_spd_ddr3(&dimm->dimm[channel][slot]); dimms++; ctrl->rank_mirror[channel][slot * 2] = 0; - ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; + ctrl->rank_mirror[channel][slot * 2 + 1] = + dimm->dimm[channel][slot].flags.pins_mirrored; + ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; - ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; - ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); - printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", - channel, ctrl->rankmap[channel]); + ctrl->extended_temperature_range &= + dimm->dimm[channel][slot].flags.ext_temp_refresh; + + ctrl->rankmap[channel] |= + ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); + + printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, + ctrl->rankmap[channel]); } - if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) - && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { + if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c) + && dimm->dimm[channel][0].reference_card <= 5 + && dimm->dimm[channel][1].reference_card <= 5) { + const int ref_card_offset_table[6][6] = { - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 2, 2, }, - { 0, 0, 0, 0, 1, 1, }, - { 2, 2, 2, 1, 0, 0, }, - { 2, 2, 2, 1, 0, 0, }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 2, 2 }, + { 0, 0, 0, 0, 1, 1 }, + { 2, 2, 2, 1, 0, 0 }, + { 2, 2, 2, 1, 0, 0 }, }; - ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card] - [dimm->dimm[channel][1].reference_card]; - } else + ctrl->ref_card_offset[channel] = ref_card_offset_table + [dimm->dimm[channel][0].reference_card] + [dimm->dimm[channel][1].reference_card]; + } else { ctrl->ref_card_offset[channel] = 0; + } } if (!dimms) @@ -268,29 +276,24 @@ static void save_timings(ramctr_timing *ctrl) { /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, - sizeof(*ctrl)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) { if (ctrl->sandybridge) - return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size); + return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); else - return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size); + return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); } static void init_dram_ddr3(int min_tck, int s3resume) { - int me_uma_size; - int cbmem_was_inited; + int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; - int fast_boot; spd_raw_data spds[4]; struct region_device rdev; ramctr_timing *ctrl_cached; - int err; u32 cpu; MCHBAR32(SAPMCTL) |= 1; @@ -301,17 +304,14 @@ printk(BIOS_DEBUG, "Starting native Platform init\n"); - u32 reg_5d10; - wait_txt_clear(); wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); - reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 - if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ - && reg_5d10 && !s3resume) { + u32 reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 + if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && reg_5d10 && !s3resume) { MCHBAR32(0x5d10) = 0; - /* Need reset. */ + /* Need reset */ system_reset(); } @@ -319,10 +319,9 @@ early_init_dmi(); early_thermal_init(); - /* try to find timings in MRC cache */ - int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, - MRC_CACHE_VERSION, &rdev); - if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { + /* Try to find timings in MRC cache */ + err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); + if (err || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ system_reset(); @@ -332,7 +331,7 @@ ctrl_cached = rdev_mmap_full(&rdev); } - /* verify MRC cache for fast boot */ + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); @@ -356,8 +355,8 @@ /* Failed S3 resume, reset to come up cleanly */ system_reset(); } - /* no need to erase bad mrc cache here, it gets overwritten on - * successful boot. */ + /* No need to erase bad MRC cache here, it gets overwritten on a + successful boot */ printk(BIOS_ERR, "Stored timings are invalid !\n"); fast_boot = 0; } @@ -380,7 +379,7 @@ } if (err) { - /* fallback: disable failing channel */ + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -395,7 +394,7 @@ /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); - /* disable failing channel */ + /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7136cd4..3cd61bc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -61,7 +61,7 @@ * [20..22] Bank Address. * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. * - * IOSAV_n_ADDR_UPD_ch(channel, index) + * IOSAV_n_ADDR_UPDATE_ch(channel, index) * How the address shall be updated after executing the sub-sequence command. * * Bitfields: @@ -86,7 +86,7 @@ * 1: LFSR XORs with address & command (excluding CS), but does not update. * 2: LFSR XORs with address & command (excluding CS), and updates. * - * IOSAV_n_SP_CMD_CTL_ch(channel, index) + * IOSAV_n_SP_CMD_CTRL_ch(channel, index) * Special command control register. Controls the DRAM command signals. * * Bitfields: @@ -118,7 +118,7 @@ * * [17] Auto Precharge. Only valid when using 10 row bits! * - * IOSAV_n_SUBSEQ_CTL_ch(channel, index) + * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) * Sub-sequence parameters. Controls repetititons, delays and data orientation. * * Bitfields: @@ -195,10 +195,11 @@ asm volatile ("sfence"); } -static void toggle_io_reset(void) { - /* toggle IO reset bit */ +/* Toggle IO reset bit */ +static void toggle_io_reset(void) +{ u32 r32 = MCHBAR32(MC_INIT_STATE_G); - MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; udelay(1); MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; udelay(1); @@ -213,43 +214,49 @@ { u32 reg; - // enable xover cmd + /* enable xover cmd */ reg = 0x4000; - // enable xover ctl - if (rankmap & 0x3) + /* enable xover ctl */ + if (rankmap & 0x03) reg |= 0x20000; - if (rankmap & 0xc) + if (rankmap & 0x0c) reg |= 0x4000000; return reg; } -/* CAS write latency. To be programmed in MR2. - * See DDR3 SPEC for MR2 documentation. */ +/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ u8 get_CWL(u32 tCK) { - /* Get CWL based on tCK using the following rule: */ + /* Get CWL based on tCK using the following rule */ switch (tCK) { case TCK_1333MHZ: return 12; + case TCK_1200MHZ: case TCK_1100MHZ: return 11; + case TCK_1066MHZ: case TCK_1000MHZ: return 10; + case TCK_933MHZ: case TCK_900MHZ: return 9; + case TCK_800MHZ: case TCK_700MHZ: return 8; + case TCK_666MHZ: return 7; + case TCK_533MHZ: return 6; + default: return 5; } @@ -263,22 +270,25 @@ ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; valid_dimms = 0; + FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { + const dimm_attr *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; + valid_dimms++; /* Find all possible CAS combinations */ ctrl->cas_supported &= dimm->cas_supported; /* Find the smallest common latencies supported by all DIMMs */ - ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); - ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); - ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); + ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); + ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); + ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); - ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); + ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); @@ -289,8 +299,8 @@ } if (!ctrl->cas_supported) - die("Unsupported DIMM combination. " - "DIMMS do not support common CAS latency"); + die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); + if (!valid_dimms) die("No valid DIMMs found"); } @@ -301,12 +311,12 @@ int channel; FOR_ALL_CHANNELS { - // enable xover clk + /* Enable xover clk */ reg = get_XOVER_CLK(ctrl->rankmap[channel]); printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; - // enable xover ctl & xover cmd + /* Enable xover ctl & xover cmd */ reg = get_XOVER_CMD(ctrl->rankmap[channel]); printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; @@ -318,22 +328,21 @@ u32 addr, cpu, stretch; stretch = ctrl->ref_card_offset[channel]; - /* ODT stretch: Delay ODT signal by stretch value. - * Useful for multi DIMM setups on the same channel. */ + /* + * ODT stretch: + * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. + */ cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; + addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, - (stretch << 12) | (stretch << 10)); - printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, - MCHBAR32(addr)); + MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { - // OTHP addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, - (stretch << 16) | (stretch << 18)); + MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -344,29 +353,29 @@ int channel; FOR_ALL_CHANNELS { - // DBP + /* BIN parameters */ reg = 0; - reg |= ctrl->tRCD; - reg |= (ctrl->tRP << 4); - reg |= (ctrl->CAS << 8); - reg |= (ctrl->CWL << 12); + reg |= (ctrl->tRCD << 0); + reg |= (ctrl->tRP << 4); + reg |= (ctrl->CAS << 8); + reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); MCHBAR32(TC_DBP_ch(channel)) = reg; - // RAP + /* Regular access parameters */ reg = 0; - reg |= ctrl->tRRD; - reg |= (ctrl->tRTP << 4); - reg |= (ctrl->tCKE << 8); + reg |= (ctrl->tRRD << 0); + reg |= (ctrl->tRTP << 4); + reg |= (ctrl->tCKE << 8); reg |= (ctrl->tWTR << 12); reg |= (ctrl->tFAW << 16); - reg |= (ctrl->tWR << 24); + reg |= (ctrl->tWR << 24); reg |= (3 << 30); printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); MCHBAR32(TC_RAP_ch(channel)) = reg; - // OTHP + /* Other parameters */ addr = TC_OTHP_ch(channel); reg = 0; reg |= ctrl->tXPDLL; @@ -376,6 +385,7 @@ printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; + /* FIXME: This register might as well not exist */ MCHBAR32(0x4014 + channel * 0x400) = 0; MCHBAR32_OR(addr, 0x00020000); @@ -383,33 +393,31 @@ dram_odt_stretch(ctrl, channel); /* - * TC-Refresh timing parameters - * The tREFIx9 field should be programmed to minimum of - * 8.9*tREFI (to allow for possible delays from ZQ or - * isoc) and tRASmax (70us) divided by 1024. + * TC-Refresh timing parameters: + * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow + * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. */ val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - reg = ((ctrl->tREFI & 0xffff) << 0) | - ((ctrl->tRFC & 0x1ff) << 16) | - (((val32 / 1024) & 0x7f) << 25); + reg = ((ctrl->tREFI & 0xffff) << 0) | + ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); + printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; MCHBAR32_OR(TC_RFP_ch(channel), 0xff); - // SRFTP + /* Self-refresh timing parameters */ reg = 0; val32 = tDLLK; - reg = (reg & ~0xfff) | val32; + reg = (reg & ~0x00000fff) | (val32 << 0); val32 = ctrl->tXSOffset; - reg = (reg & ~0xf000) | (val32 << 12); + reg = (reg & ~0x0000f000) | (val32 << 12); val32 = tDLLK - ctrl->tXSOffset; - reg = (reg & ~0x3ff0000) | (val32 << 16); + reg = (reg & ~0x03ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; - reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), - reg); + reg = (reg & ~0xf0000000) | (val32 << 28); + printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); MCHBAR32(TC_SRFTP_ch(channel)) = reg; } } @@ -423,19 +431,18 @@ dimm_attr *dimmA, *dimmB; u32 reg = 0; - if (info->dimm[channel][0].size_mb >= - info->dimm[channel][1].size_mb) { + if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { dimmA = &info->dimm[channel][0]; dimmB = &info->dimm[channel][1]; - reg |= 0 << 16; + reg |= (0 << 16); } else { dimmA = &info->dimm[channel][1]; dimmB = &info->dimm[channel][0]; - reg |= 1 << 16; + reg |= (1 << 16); } if (dimmA && (dimmA->ranks > 0)) { - reg |= dimmA->size_mb / 256; + reg |= dimmA->size_mb / 256; reg |= (dimmA->ranks - 1) << 17; reg |= (dimmA->width / 8 - 1) << 19; } @@ -446,8 +453,8 @@ reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* rank interleave */ - reg |= 1 << 22; /* enhanced interleave */ + reg |= 1 << 21; /* Rank interleave */ + reg |= 1 << 22; /* Enhanced interleave */ if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { @@ -472,6 +479,7 @@ u8 val; reg = 0; val = 0; + if (training) { ch0size = ctrl->channel_size_mb[0] ? 256 : 0; ch1size = ctrl->channel_size_mb[1] ? 256 : 0; @@ -484,14 +492,15 @@ reg = MCHBAR32(MAD_ZR); val = ch1size / 256; reg = (reg & ~0xff000000) | val << 24; - reg = (reg & ~0xff0000) | (2 * val) << 16; + reg = (reg & ~0x00ff0000) | (2 * val) << 16; MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x24; + } else { reg = MCHBAR32(MAD_ZR); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; - reg = (reg & ~0xff0000) | (2 * val) << 16; + reg = (reg & ~0x00ff0000) | (2 * val) << 16; MCHBAR32(MAD_ZR) = reg; MCHBAR32(MAD_CHNL) = 0x21; } @@ -512,13 +521,14 @@ /* If this is zero, it just means devicetree.cb didn't set it */ if (!cfg || cfg->max_mem_clock_mhz == 0) { + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ; rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* read Capabilities A Register DMFC bits */ + /* Read Capabilities A Register DMFC bits */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); reg32 &= 0x7; @@ -526,12 +536,12 @@ case 7: return TCK_533MHZ; case 6: return TCK_666MHZ; case 5: return TCK_800MHZ; - /* reserved: */ + /* Reserved */ default: break; } } else { - /* read Capabilities B Register DMFC bits */ + /* Read Capabilities B Register DMFC bits */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); reg32 = (reg32 >> 4) & 0x7; @@ -543,7 +553,7 @@ case 3: return TCK_1066MHZ; case 2: return TCK_1200MHZ; case 1: return TCK_1333MHZ; - /* reserved: */ + /* Reserved */ default: break; } @@ -585,11 +595,9 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { - u32 reg, val, reclaim; - u32 tom, gfxstolen, gttsize; - size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase, - tsegbase, mestolenbase; - size_t tsegbasedelta, remapbase, remaplimit; + u32 reg, val, reclaim, tom, gfxstolen, gttsize; + size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase; + size_t tsegbase, mestolenbase, tsegbasedelta, remapbase, remaplimit; uint16_t ggc; mmiosize = get_mmio_size(); @@ -597,10 +605,10 @@ ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { gfxstolen = ((ggc >> 3) & 0x1f) * 32; - gttsize = ((ggc >> 8) & 0x3); + gttsize = ((ggc >> 8) & 0x3); } else { gfxstolen = 0; - gttsize = 0; + gttsize = 0; } tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; @@ -609,14 +617,14 @@ mestolenbase = tom - me_uma_size; - toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, - tom - me_uma_size); + toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); + gfxstolenbase = toludbase - gfxstolen; gttbase = gfxstolenbase - gttsize; tsegbase = gttbase - tsegsize; - // Round tsegbase down to nearest address aligned to tsegsize + /* Round tsegbase down to nearest address aligned to tsegsize */ tsegbasedelta = tsegbase & (tsegsize - 1); tsegbase &= ~(tsegsize - 1); @@ -624,24 +632,23 @@ gfxstolenbase -= tsegbasedelta; toludbase -= tsegbasedelta; - // Test if it is possible to reclaim a hole in the RAM addressing + /* Test if it is possible to reclaim a hole in the RAM addressing */ if (tom - me_uma_size > toludbase) { - // Reclaim is possible - reclaim = 1; - remapbase = MAX(4096, tom - me_uma_size); - remaplimit = - remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; - touudbase = remaplimit + 1; + /* Reclaim is possible */ + reclaim = 1; + remapbase = MAX(4096, tom - me_uma_size); + remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; + touudbase = remaplimit + 1; } else { // Reclaim not possible - reclaim = 0; + reclaim = 0; touudbase = tom - me_uma_size; } - // Update memory map in pci-e configuration space + /* Update memory map in PCIe configuration space */ printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); - // TOM (top of memory) + /* TOM (top of memory) */ reg = pci_read_config32(HOST_BRIDGE, TOM); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -654,21 +661,21 @@ printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); pci_write_config32(HOST_BRIDGE, TOM + 4, reg); - // TOLUD (top of low used dram) + /* TOLUD (Top Of Low Usable DRAM) */ reg = pci_read_config32(HOST_BRIDGE, TOLUD); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); pci_write_config32(HOST_BRIDGE, TOLUD, reg); - // TOUUD LSB (top of upper usable dram) + /* TOUUD LSB (Top Of Upper Usable DRAM) */ reg = pci_read_config32(HOST_BRIDGE, TOUUD); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); pci_write_config32(HOST_BRIDGE, TOUUD, reg); - // TOUUD MSB + /* TOUUD MSB */ reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); @@ -676,29 +683,29 @@ pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); if (reclaim) { - // REMAP BASE - pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); + /* REMAP BASE */ + pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); - // REMAP LIMIT - pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); + /* REMAP LIMIT */ + pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); } - // TSEG + /* TSEG */ reg = pci_read_config32(HOST_BRIDGE, TSEGMB); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); pci_write_config32(HOST_BRIDGE, TSEGMB, reg); - // GFX stolen memory + /* GFX stolen memory */ reg = pci_read_config32(HOST_BRIDGE, BDSM); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); pci_write_config32(HOST_BRIDGE, BDSM, reg); - // GTT stolen memory + /* GTT stolen memory */ reg = pci_read_config32(HOST_BRIDGE, BGSM); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -712,7 +719,7 @@ printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); - // ME base + /* ME base */ reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); @@ -725,12 +732,12 @@ printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); - // ME mask + /* ME mask */ reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - reg = reg | ME_STLEN_EN; // set ME memory enable - reg = reg | MELCK; // set lockbit on ME mem + reg = reg | ME_STLEN_EN; /* Set ME memory enable */ + reg = reg | MELCK; /* Set lock bit on ME mem */ printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); } @@ -748,21 +755,21 @@ { int channel, slotrank; - /* choose a populated channel. */ + /* Choose a populated channel */ channel = (ctrl->rankmap[0]) ? 0 : 1; wait_for_iosav(channel); - /* choose a populated rank. */ + /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x80c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x80c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; - // execute command queue - why is bit 22 set here?! + /* Execute command queue - why is bit 22 set here?! */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -773,101 +780,99 @@ u32 reg; int channel; - while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; do { reg = MCHBAR32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); - // Set state of memory controller + /* Set state of memory controller */ reg = 0x112; MCHBAR32(MC_INIT_STATE_G) = reg; MCHBAR32(MC_INIT_STATE) = 0; - reg |= 2; //ddr reset + reg |= 2; /* DDR reset */ MCHBAR32(MC_INIT_STATE_G) = reg; - // Assert dimm reset signal - MCHBAR32_AND(MC_INIT_STATE_G, ~0x2); + /* Assert DIMM reset signal */ + MCHBAR32_AND(MC_INIT_STATE_G, ~2); - // Wait 200us + /* Wait 200us */ udelay(200); - // Deassert dimm reset signal + /* Deassert DIMM reset signal */ MCHBAR32_OR(MC_INIT_STATE_G, 2); - // Wait 500us + /* Wait 500us */ udelay(500); - // Enable DCLK + /* Enable DCLK */ MCHBAR32_OR(MC_INIT_STATE_G, 4); - // XXX Wait 20ns + /* XXX Wait 20ns */ udelay(1); FOR_ALL_CHANNELS { - // Set valid rank CKE + /* Set valid rank CKE */ reg = ctrl->rankmap[channel]; MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; - // Wait 10ns for ranks to settle - //udelay(0.01); + /* Wait 10ns for ranks to settle */ + // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; - // Write reset using a NOP + /* Write reset using a NOP */ write_reset(ctrl); } } static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) { - /* Get ODT based on rankmap: */ - int dimms_per_ch = (ctrl->rankmap[channel] & 1) - + ((ctrl->rankmap[channel] >> 2) & 1); + /* Get ODT based on rankmap */ + int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); if (dimms_per_ch == 1) { - return (const odtmap){60, 60}; + return (const odtmap){60, 60}; } else { return (const odtmap){120, 30}; } } -static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, - int reg, u32 val) +static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) { wait_for_iosav(channel); if (ctrl->rank_mirror[channel][slotrank]) { /* DDR3 Rank1 Address mirror - * swap the following pins: - * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ + swap the following pins: + A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ reg = ((reg >> 1) & 1) | ((reg << 1) & 2); - val = (val & ~0x1f8) | ((val >> 1) & 0xa8) - | ((val & 0xa8) << 1); + val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); } /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command MRS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | (reg << 20) | val | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); } @@ -891,12 +896,12 @@ // Convert tWR to MCH register friendly mch_wr = mch_wr_t[ctrl->tWR - 5]; - mr0reg = (mr0reg & ~0x4) | ((mch_cas & 0x1) << 2); - mr0reg = (mr0reg & ~0x70) | ((mch_cas & 0xe) << 3); - mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9); + mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); + mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); + mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); - // Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature - mr0reg = (mr0reg & ~0x1000) | (!is_mobile << 12); + // Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature + mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); return mr0reg; } @@ -926,7 +931,7 @@ u32 mr1reg; odt = get_ODT(ctrl, rank, channel); - mr1reg = 0x2; + mr1reg = 2; mr1reg |= encode_odt(odt.rttnom); @@ -955,7 +960,7 @@ srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; mr2reg = 0; - mr2reg = (mr2reg & ~0x7) | pasr; + mr2reg = (mr2reg & ~0x07) | pasr; mr2reg = (mr2reg & ~0x38) | (cwl << 3); mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); mr2reg = (mr2reg & ~0x80) | (srt << 7); @@ -976,42 +981,41 @@ FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_RANKS { - // MR2 + /* MR2 */ dram_mr2(ctrl, slotrank, channel); - // MR3 + /* MR3 */ dram_mr3(ctrl, slotrank, channel); - // MR1 + /* MR1 */ dram_mr1(ctrl, slotrank, channel); - // MR0 + /* MR0 */ dram_mr0(ctrl, slotrank, channel); } } /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL(0)) = 0x7; - MCHBAR32(IOSAV_n_SUBSEQ_CTL(0)) = 0xf1001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = 0x7; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; - MCHBAR32(IOSAV_n_ADDR_UPD(0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0; /* DRAM command ZQCL */ - MCHBAR32(IOSAV_n_SP_CMD_CTL(1)) = 0x1f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL(1)) = 0x1901001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = 0x1f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001; MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD(1)) = 0x288; + MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288; - // execute command queue on all channels? Why isn't bit 0 set here? + /* Execute command queue on all channels? Why isn't bit 0 set here? */ MCHBAR32(IOSAV_SEQ_CTL) = 0x40004; - // Drain FOR_ALL_CHANNELS { - // Wait for ref drained + /* Wait for ref drained */ wait_for_iosav(channel); } - // Refresh enable + /* Refresh enable */ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { @@ -1021,20 +1025,20 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - // Drain + /* Drain */ wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); - // Drain + /* Drain */ wait_for_iosav(channel); } } @@ -1066,42 +1070,41 @@ break; case 1: pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 0].pi_coding + - full_shift; + ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; break; case 2: pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 1].pi_coding + - full_shift; + ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; break; case 3: pi_coding_ctrl[slot] = (ctrl->timings[channel][2 * slot].pi_coding + - ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + - full_shift; + ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; break; } - /* enable CMD XOVER */ + /* Enable CMD XOVER */ reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); - reg32 |= ((pi_coding_ctrl[0] & 0x3f) << 6) | ((pi_coding_ctrl[0] & 0x40) << 9); + reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; + reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; - /* enable CLK XOVER */ + /* Enable CLK XOVER */ reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); reg_logic_delay = 0; FOR_ALL_POPULATED_RANKS { - int shift = - ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; int offset_pi_code; if (shift < 0) shift = 0; + offset_pi_code = ctrl->pi_code_offset + shift; - /* set CLK phase shift */ + + /* Set CLK phase shift */ reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; } @@ -1115,11 +1118,10 @@ reg_roundtrip_latency = 0; FOR_ALL_POPULATED_RANKS { - int post_timA_min_high = 7, post_timA_max_high = 0; - int pre_timA_min_high = 7, pre_timA_max_high = 0; + int post_timA_min_high = 7, pre_timA_min_high = 7; + int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = - ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; if (shift < 0) shift = 0; @@ -1142,6 +1144,7 @@ if (pre_timA_max_high - pre_timA_min_high < post_timA_max_high - post_timA_min_high) shift_402x = +1; + else if (pre_timA_max_high - pre_timA_min_high > post_timA_max_high - post_timA_min_high) shift_402x = -1; @@ -1149,6 +1152,7 @@ reg_io_latency |= (ctrl->timings[channel][slotrank].io_latency + shift_402x - post_timA_min_high) << (4 * slotrank); + reg_roundtrip_latency |= (ctrl->timings[channel][slotrank].roundtrip_latency + shift_402x) << (8 * slotrank); @@ -1190,45 +1194,45 @@ wait_for_iosav(channel); /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4040c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS - * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + write MR3 MPR disable */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); } -static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, - int lane) +static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> - (timA % 32)) & 1); + + return (MCHBAR32(lane_base[lane] + + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; } struct run { @@ -1256,24 +1260,23 @@ } if (bl == 0) { ret.middle = sz / 2; - ret.start = 0; - ret.end = sz; + ret.start = 0; + ret.end = sz; ret.length = sz; - ret.all = 1; + ret.all = 1; return ret; } - ret.start = bs % sz; - ret.end = (bs + bl - 1) % sz; + ret.start = bs % sz; + ret.end = (bs + bl - 1) % sz; ret.middle = (bs + (bl - 1) / 2) % sz; ret.length = bl; - ret.all = 0; + ret.all = 0; return ret; } -static void discover_timA_coarse(ramctr_timing *ctrl, int channel, - int slotrank, int *upperA) +static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA; int statistics[NUM_LANES][128]; @@ -1288,8 +1291,7 @@ test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timA] = - !does_lane_work(ctrl, channel, slotrank, lane); + statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); } } FOR_ALL_LANES { @@ -1298,13 +1300,13 @@ upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; + printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } } -static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, - int *upperA) +static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA_delta; int statistics[NUM_LANES][51]; @@ -1313,16 +1315,18 @@ memset(statistics, 0, sizeof(statistics)); for (timA_delta = -25; timA_delta <= 25; timA_delta++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. - timA = upperA[lane] + timA_delta + 0x40; + + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timA + = upperA[lane] + timA_delta + 0x40; + } program_timings(ctrl, channel); for (i = 0; i < 100; i++) { test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, - lane); + does_lane_work(ctrl, channel, slotrank, lane); } } } @@ -1332,18 +1336,19 @@ for (last_zero = -25; last_zero <= 25; last_zero++) if (statistics[lane][last_zero + 25]) break; + last_zero--; for (first_all = -25; first_all <= 25; first_all++) if (statistics[lane][first_all + 25] == 100) break; - printram("lane %d: %d, %d\n", lane, last_zero, - first_all); + printram("lane %d: %d, %d\n", lane, last_zero, first_all); ctrl->timings[channel][slotrank].lanes[lane].timA = - (last_zero + first_all) / 2 + upperA[lane]; + (last_zero + first_all) / 2 + upperA[lane]; + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); + lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1351,13 +1356,16 @@ { int works[NUM_LANES]; int lane; + while (1) { int all_works = 1, some_works = 0; + program_timings(ctrl, channel); test_timA(ctrl, channel, slotrank); + FOR_ALL_LANES { - works[lane] = - !does_lane_work(ctrl, channel, slotrank, lane); + works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); + if (works[lane]) some_works = 1; else @@ -1365,6 +1373,7 @@ } if (all_works) return 0; + if (!some_works) { if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", @@ -1377,6 +1386,7 @@ } ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); + if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", channel, slotrank); @@ -1420,15 +1430,17 @@ struct timA_minmax post; int shift_402x = 0; - /* Get changed maxima. */ + /* Get changed maxima */ pre_timA_change(ctrl, channel, slotrank, &post); if (mnmx->timA_max_high - mnmx->timA_min_high < post.timA_max_high - post.timA_min_high) shift_402x = +1; + else if (mnmx->timA_max_high - mnmx->timA_min_high > post.timA_max_high - post.timA_min_high) shift_402x = -1; + else shift_402x = 0; @@ -1438,17 +1450,21 @@ printram("4028 += %d;\n", shift_402x); } -/* Compensate the skew between DQS and DQs. +/* + * Compensate the skew between DQS and DQs. + * * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. * The controller has to measure and compensate this skew for every byte-lane. By delaying - * either all DQs signals or DQS signal, a full phase shift can be introduced. It is assumed + * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed * that one byte-lane's DQs signals have the same routing delay. * * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates * over all possible values to do a full phase shift and issues read commands. With DQS and - * DQs in phase the data read is expected to alternate on every byte: + * DQ in phase the data being read is expected to alternate on every byte: + * * 0xFF 0x00 0xFF ... + * * Once the controller has detected this pattern a bit in the result register is set for the * current phase shift. */ @@ -1465,12 +1481,12 @@ wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; @@ -1522,7 +1538,8 @@ pre_timA_change(ctrl, channel, slotrank, &mnmx); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; + ctrl->timings[channel][slotrank].lanes[lane].timA -= + mnmx.timA_min_high * 0x40; } ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; printram("4028 -= %d;\n", mnmx.timA_min_high); @@ -1535,8 +1552,7 @@ printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1565,65 +1581,63 @@ wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 4 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8041001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8041001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x80411f4; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x80411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = + 0x08000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) - | 8 | (ctrl->CAS << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x244; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1637,30 +1651,32 @@ for (i = 1; i < count; i++) { if (min > data[i]) min = data[i]; + if (max < data[i]) max = data[i]; } - int threshold = min/2 + max/2; + int threshold = min / 2 + max / 2; for (i = 0; i < count; i++) data[i] = data[i] > threshold; + printram("threshold=%d min=%d max=%d\n", threshold, min, max); } static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; - int statistics[NUM_LANES][MAX_TIMC + 1]; + int stats[NUM_LANES][MAX_TIMC + 1]; int lane; wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); for (timC = 0; timC <= MAX_TIMC; timC++) { @@ -1670,24 +1686,22 @@ test_timC(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timC] = - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { - struct run rn = get_longest_zero_run( - statistics[lane], ARRAY_SIZE(statistics[lane])); + struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - /* With command training not happend yet, the lane can - * be erroneous. Take the avarage as reference and try - * again to find a run. + /* + * With command training not being done yet, the lane can be erroneous. + * Take the average as reference and try again to find a run. */ - timC_threshold_process(statistics[lane], - ARRAY_SIZE(statistics[lane])); - rn = get_longest_zero_run(statistics[lane], - ARRAY_SIZE(statistics[lane])); + timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); + rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC recovery failed\n"); return MAKE_ERR; @@ -1703,8 +1717,10 @@ static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) { int channel, ret = 0; + FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) ret++; + return ret; } @@ -1712,8 +1728,10 @@ { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + sfence(); } @@ -1730,10 +1748,13 @@ unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); + for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); + sfence(); } @@ -1753,40 +1774,40 @@ wait_for_iosav(channel); /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1805,37 +1826,37 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * write MR3 MPR disable */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -1850,19 +1871,19 @@ wait_for_iosav(channel); /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f107; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f107; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); wait_for_iosav(channel); @@ -1895,23 +1916,25 @@ } FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); - /* timC is a direct function of timB's 6 LSBs. - * Some tests increments the value of timB by a small value, - * which might cause the 6bit value to overflow, if it's close - * to 0x3F. Increment the value by a small offset if it's likely - * to overflow, to make sure it won't overflow while running - * tests and bricks the system due to a non matching timC. + /* + * timC is a direct function of timB's 6 LSBs. Some tests increments the value + * of timB by a small value, which might cause the 6-bit value to overflow if + * it's close to 0x3f. Increment the value by a small offset if it's likely + * to overflow, to make sure it won't overflow while running tests and bricks + * the system due to a non matching timC. * - * TODO: find out why some tests (edge write discovery) - * increment timB. */ - if ((rn.start & 0x3F) == 0x3E) + * TODO: find out why some tests (edge write discovery) increment timB. + */ + if ((rn.start & 0x3f) == 0x3e) rn.start += 2; - else if ((rn.start & 0x3F) == 0x3F) + else if ((rn.start & 0x3f) == 0x3f) rn.start += 1; + ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", channel, slotrank, lane); + return MAKE_ERR; } printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", @@ -1957,56 +1980,56 @@ wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8040c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8040c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x8041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x8041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x3e2; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x3e2; /* DRAM command NOP */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f207; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); /* DRAM command PREA */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x3f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x3f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].roundtrip_latency + ctrl->timings[channel][slotrank].io_latency) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60008; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); wait_for_iosav(channel); @@ -2036,28 +2059,28 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); } -/* Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. - * DDR3 adopted the fly-by topology. The data and strobes signals reach - * the chips at different times with respect to command, address and - * clock signals. - * By delaying either all DQ/DQs or all CMD/ADDR/CLK signals, a full phase - * shift can be introduced. - * It is assumed that the CLK/ADDR/CMD signals have the same routing delay. +/* + * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. * - * To find the required phase shift the DRAM is placed in "write leveling" mode. - * In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the - * sampled value on the data lanes (DQs). + * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different + * times with respect to command, address and clock signals. By delaying either all DQ/DQS or + * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the + * CLK/ADDR/CMD signals have the same routing delay. + * + * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, + * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data + * lanes (DQ). */ int write_training(ramctr_timing *ctrl) { @@ -2072,42 +2095,40 @@ MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); } - /* refresh disable */ + /* Refresh disable */ MCHBAR32_AND(MC_INIT_STATE_G, ~8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } - /* enable write leveling on all ranks - * disable all DQ outputs - * only NOP is allowed in this mode */ - FOR_ALL_CHANNELS - FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, + /* Enable write leveling on all ranks + Disable all DQ outputs + Only NOP is allowed in this mode */ + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 0x1080); MCHBAR32(GDCRTRAININGMOD) = 0x108052; toggle_io_reset(); - /* set any valid value for timB, it gets corrected later */ + /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_timB(ctrl, channel, slotrank); if (err) return err; } - /* disable write leveling on all ranks */ + /* Disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, - slotrank, 1, make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); MCHBAR32(GDCRTRAININGMOD) = 0; FOR_ALL_POPULATED_CHANNELS wait_for_iosav(channel); - /* refresh enable */ + /* Refresh enable */ MCHBAR32_OR(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { @@ -2116,12 +2137,12 @@ wait_for_iosav(channel); /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x659001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -2185,37 +2206,37 @@ wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x20e42; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xf1001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xf1001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2240,8 +2261,8 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) { unsigned int i, j; - unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - unsigned int channel_step = 0x40 * num_of_channels(ctrl); + unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; + unsigned int step = 0x40 * num_of_channels(ctrl); if (patno) { u8 base8 = 0x80 >> ((patno - 1) % 8); @@ -2249,21 +2270,20 @@ for (i = 0; i < 32; i++) { for (j = 0; j < 16; j++) { u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; + if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val; - write32((void *)(0x04000000 + channel_offset + i * channel_step + - j * 4), val); + + write32((void *)((1 << 26) + offset + i * step + j * 4), val); } } - - } else { - for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) { - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + i * channel_step + - j * 4), pattern[i][j]); - } - sfence(); + return; } + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + for (j = 0; j < 16; j++) + write32((void *)((1 << 26) + offset + i * step + j * 4), pattern[i][j]); + } + sfence(); } static void reprogram_320c(ramctr_timing *ctrl) @@ -2273,16 +2293,16 @@ FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); - /* choose an existing rank. */ + /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); @@ -2298,20 +2318,21 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0f003; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x41001; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x3e0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); wait_for_iosav(channel); } - /* jedec reset */ + /* JEDEC reset */ dram_jedecreset(ctrl); - /* mrs commands. */ + + /* MRS commands */ dram_mrscommands(ctrl); toggle_io_reset(); @@ -2336,12 +2357,12 @@ ctrl->cmd_stretch[channel] = cmd_stretch; MCHBAR32(TC_RAP_ch(channel)) = - ctrl->tRRD - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) + (ctrl->tRRD << 0) + | (ctrl->tRTP << 4) + | (ctrl->tCKE << 8) | (ctrl->tWTR << 12) | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) + | (ctrl->tWR << 24) | (ctrl->cmd_stretch[channel] << 30); if (ctrl->cmd_stretch[channel] == 2) @@ -2364,11 +2385,12 @@ } } FOR_ALL_POPULATED_RANKS { - struct run rn = - get_longest_zero_run(stat[slotrank], 255); + struct run rn = get_longest_zero_run(stat[slotrank], 255); + ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, rn.start, rn.middle, rn.end); + if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] = @@ -2381,9 +2403,10 @@ return 0; } -/* Adjust CMD phase shift and try multiple command rates. - * A command rate of 2T doubles the time needed for address and - * command decode. */ +/* + * Adjust CMD phase shift and try multiple command rates. + * A command rate of 2T doubles the time needed for address and command decode. + */ int command_training(ramctr_timing *ctrl) { int channel; @@ -2398,12 +2421,12 @@ /* * Dual DIMM per channel: - * Issue: While c320c discovery seems to succeed raminit - * will fail in write training. - * Workaround: Skip 1T in dual DIMM mode, that's only - * supported by a few DIMMs. - * Only try 1T mode for XMP DIMMs that request it in dual DIMM - * mode. + * Issue: + * While c320c discovery seems to succeed raminit will fail in write training. + * + * Workaround: + * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. + * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. * * Single DIMM per channel: * Try command rate 1T and 2T @@ -2435,16 +2458,15 @@ return 0; } - static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; - int statistics[NUM_LANES][MAX_EDGE_TIMING + 1]; + int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; int lane; for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = edge; + ctrl->timings[channel][slotrank].lanes[lane].rising = edge; ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } program_timings(ctrl, channel); @@ -2455,54 +2477,55 @@ } wait_for_iosav(channel); + /* DRAM command MRS - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x40411f4; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x40411f4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS - * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); + MR3 disable MPR */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); FOR_ALL_LANES { - statistics[lane][edge] = - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } + FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); + struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; + if (rn.all) { - printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, + slotrank, lane); return MAKE_ERR; } - printram("eval %d, %d, %d: %02x\n", channel, slotrank, - lane, edges[lane]); + printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } return 0; } @@ -2540,41 +2563,41 @@ wait_for_iosav(channel); /* DRAM command MRS - * MR3 enable MPR - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MR3 enable MPR + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2584,7 +2607,7 @@ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + ctrl->timings[channel][slotrank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -2593,42 +2616,42 @@ wait_for_iosav(channel); /* DRAM command MRS - * MR3 enable MPR - * write MR3 MPR enable - * in this mode only RD and RDA are allowed - * all reads return a predefined pattern */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MR3 enable MPR + write MR3 MPR enable + in this mode only RD and RDA are allowed + all reads return a predefined pattern */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4041003; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; /* DRAM command MRS * MR3 disable MPR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2685,12 +2708,11 @@ return 0; } -static int discover_edges_write_real(ramctr_timing *ctrl, int channel, - int slotrank, int *edges) +static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; - u32 raw_statistics[MAX_EDGE_TIMING + 1]; - int statistics[MAX_EDGE_TIMING + 1]; + u32 raw_stats[MAX_EDGE_TIMING + 1]; + int stats[MAX_EDGE_TIMING + 1]; const int reg3000b24[] = { 0, 0xc, 0x2c }; int lane, i; int lower[NUM_LANES]; @@ -2704,12 +2726,13 @@ for (i = 0; i < 3; i++) { MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", - GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; printram("using pattern %d\n", pat); + for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -2726,68 +2749,70 @@ wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x4 | (ctrl->tRCD << 16) | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x8005020 | + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = - IOSAV_RUN_ONCE(4); + /* Execute command queue */ + MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } - raw_statistics[edge] = MCHBAR32(0x436c + channel * 0x400); + /* FIXME: This register only exists on Ivy Bridge */ + raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); } + FOR_ALL_LANES { struct run rn; for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) - statistics[edge] = - ! !(raw_statistics[edge] & (1 << lane)); - rn = get_longest_zero_run(statistics, - MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", - channel, slotrank, i, rn.start, rn.middle, - rn.end, rn.start + ctrl->edge_offset[i], + stats[edge] = !!(raw_stats[edge] & (1 << lane)); + + rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); + + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, + rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); - lower[lane] = - MAX(rn.start + ctrl->edge_offset[i], lower[lane]); - upper[lane] = - MIN(rn.end - ctrl->edge_offset[i], upper[lane]); + + lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); + upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); + edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { - printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, "edge write discovery failed: " + "%d, %d, %d\n", channel, slotrank, lane); + return MAKE_ERR; } } @@ -2802,17 +2827,19 @@ int discover_edges_write(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; - int err; + int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + int channel, slotrank, lane, err; - /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ + /* + * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will + * also use a single loop. It would seem that it is a debugging configuration. + */ MCHBAR32(IOSAV_DC_MASK) = 0x300; printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + falling_edges[channel][slotrank]); if (err) return err; } @@ -2822,7 +2849,7 @@ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_write_real(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + rising_edges[channel][slotrank]); if (err) return err; } @@ -2831,9 +2858,10 @@ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; + falling_edges[channel][slotrank][lane]; + ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + rising_edges[channel][slotrank][lane]; } FOR_ALL_POPULATED_CHANNELS @@ -2848,34 +2876,34 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); + /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x60000; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x0244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -2883,7 +2911,7 @@ int discover_timC_write(ramctr_timing *ctrl) { - const u8 rege3c_b24[3] = { 0, 0xf, 0x2f }; + const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; int i, pat; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2904,53 +2932,65 @@ for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000, - rege3c_b24[i] << 24); + + /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ + MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), + ~0x3f000000, rege3c_b24[i] << 24); + udelay(2); + for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { int timC; - u32 raw_statistics[MAX_TIMC + 1]; - int statistics[MAX_TIMC + 1]; + u32 raw_stats[MAX_TIMC + 1]; + int stats[MAX_TIMC + 1]; /* Make sure rn.start < rn.end */ - statistics[MAX_TIMC] = 1; + stats[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = - 0x1f; + MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; + for (timC = 0; timC < MAX_TIMC; timC++) { - FOR_ALL_LANES - ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + FOR_ALL_LANES { + ctrl->timings[channel][slotrank] + .lanes[lane].timC = timC; + } program_timings(ctrl, channel); test_timC_write (ctrl, channel, slotrank); - raw_statistics[timC] = + /* FIXME: Another IVB-only register! */ + raw_stats[timC] = MCHBAR32(0x436c + channel * 0x400); } FOR_ALL_LANES { struct run rn; - for (timC = 0; timC < MAX_TIMC; timC++) - statistics[timC] = - !!(raw_statistics[timC] & - (1 << lane)); + for (timC = 0; timC < MAX_TIMC; timC++) { + stats[timC] = !!(raw_stats[timC] + & (1 << lane)); + } - rn = get_longest_zero_run(statistics, - MAX_TIMC + 1); + rn = get_longest_zero_run(stats, MAX_TIMC + 1); if (rn.all) { - printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + printk(BIOS_EMERG, + "timC write discovery failed: " + "%d, %d, %d\n", channel, + slotrank, lane); + return MAKE_ERR; } - printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", - channel, slotrank, i, rn.start, - rn.middle, rn.end, + printram("timC: %d, %d, %d: " + "0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, + i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], - rn.end - ctrl->timC_offset[i]); + rn.end - ctrl->timC_offset[i]); + lower[channel][slotrank][lane] = MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); + upper[channel][slotrank][lane] = MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]); @@ -2961,6 +3001,7 @@ } FOR_ALL_CHANNELS { + /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); udelay(2); } @@ -2974,10 +3015,10 @@ printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC %d, %d, %d: %x\n", channel, - slotrank, lane, + printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); + ctrl->timings[channel][slotrank].lanes[lane].timC = (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2; @@ -3052,30 +3093,30 @@ wait_for_iosav(channel); /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0001f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x0028a004; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x0028a004; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x00000244; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000244; /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x0001f201; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x08281064; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x0001f201; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x00000242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; /* DRAM command RD */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0001f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x04281064; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0001f105; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x04281064; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x00000242; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000242; /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x0001f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x00280c01; + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x0001f002; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x00280c01; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x00000240; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x00000240; - // execute command queue + /* Execute command queue */ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); wait_for_iosav(channel); @@ -3093,8 +3134,7 @@ { int channel; - /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? - I don't think so. */ + /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ static u32 seeds[NUM_CHANNELS][3] = { {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, {0x00028bfa, 0x53fe4b49, 0x19ed5483} @@ -3107,15 +3147,14 @@ } } -void set_4f8c(void) +void set_wmm_behavior(void) { - u32 cpu; + u32 cpu = cpu_get_cpuid(); - cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { - MCHBAR32(SC_WDBWM) = 0x141D1519; + MCHBAR32(SC_WDBWM) = 0x141d1519; } else { - MCHBAR32(SC_WDBWM) = 0x551D1519; + MCHBAR32(SC_WDBWM) = 0x551d1519; } } @@ -3124,7 +3163,7 @@ int channel; FOR_ALL_POPULATED_CHANNELS { - // Always drive command bus + /* Always drive command bus */ MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); } @@ -3135,7 +3174,7 @@ } } -void set_4008c(ramctr_timing *ctrl) +void set_read_write_timings(ramctr_timing *ctrl) { int channel, slotrank; @@ -3149,20 +3188,13 @@ min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); } - if (max_pi - min_pi > 51) - b20 = 0; - else - b20 = ctrl->ref_card_offset[channel]; + b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; - if (ctrl->pi_coding_threshold < max_pi - min_pi) - b4_8_12 = 0x3330; - else - b4_8_12 = 0x2220; + b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = - 0x0a000000 | (b20 << 20) | + MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -3181,7 +3213,7 @@ return (ns + 499) / 500; } -/* FIXME: values in this function should be hardware revision-dependent. */ +/* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; @@ -3191,17 +3223,17 @@ int t3_ns; u32 r32; - /* FIXME: This register only exists on Ivy Bridge. */ - MCHBAR32(WMM_READ_CONFIG) = 0x00000046; + /* FIXME: This register only exists on Ivy Bridge */ + MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ + /* APD - PPD, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; FOR_ALL_CHANNELS @@ -3212,35 +3244,35 @@ FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { - /* Unpopulated channel. */ + /* Unpopulated channel */ case 0: MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; break; - /* Only single-ranked dimms. */ + /* Only single-ranked dimms */ case 1: case 4: case 5: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x373131; + MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; break; - /* Dual-ranked dimms present. */ + /* Dual-ranked dimms present */ default: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x9b6ea1; + MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; break; } } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0); + MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); MCHBAR32_OR(MC_INIT_STATE_G, 1); MCHBAR32_OR(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; - /* Find a populated channel. */ + /* Find a populated channel */ FOR_ALL_POPULATED_CHANNELS break; @@ -3255,32 +3287,33 @@ t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); if (MCHBAR32(SAPMCTL) & 8) { - t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); + t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); } else { t3_ns = 500; } - printk(BIOS_DEBUG, "t123: %d, %d, %d\n", - t1_ns, t2_ns, t3_ns); + + /* The graphics driver will use these values */ + printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); MCHBAR32_AND_OR(0x5d10, 0xC0C0C0C0, - ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | - (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + - encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | 0xc); + ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | (encode_5d10(t1_ns) << 8) | + ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | 0x0c); } void restore_timings(ramctr_timing *ctrl) { int channel, slotrank, lane; - FOR_ALL_POPULATED_CHANNELS - MCHBAR32(TC_RAP_ch(channel)) = - ctrl->tRRD - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + FOR_ALL_POPULATED_CHANNELS { + MCHBAR32(TC_RAP_ch(channel)) + = (ctrl->tRRD) + | (ctrl->tRTP << 4) + | (ctrl->tCKE << 8) + | (ctrl->tWTR << 12) + | (ctrl->tFAW << 16) + | (ctrl->tWR << 24) + | (ctrl->cmd_stretch[channel] << 30); + } udelay(1); @@ -3293,11 +3326,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); FOR_ALL_POPULATED_CHANNELS { - udelay (1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + udelay(1); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); } printram("CPE\n"); @@ -3313,36 +3346,39 @@ u32 reg, addr; - while (!(MCHBAR32(RCOMP_TIMER) & 0x10000)); + /* Poll for RCOMP */ + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + do { reg = MCHBAR32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); - // Set state of memory controller + /* Set state of memory controller */ MCHBAR32(MC_INIT_STATE_G) = 0x116; - MCHBAR32(MC_INIT_STATE) = 0; + MCHBAR32(MC_INIT_STATE) = 0; - // Wait 500us + /* Wait 500us */ udelay(500); FOR_ALL_CHANNELS { - // Set valid rank CKE + /* Set valid rank CKE */ reg = 0; - reg = (reg & ~0xf) | ctrl->rankmap[channel]; + reg = (reg & ~0x0f) | ctrl->rankmap[channel]; addr = MC_INIT_STATE_ch(channel); MCHBAR32(addr) = reg; - // Wait 10ns for ranks to settle - //udelay(0.01); + /* Wait 10ns for ranks to settle */ + // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); MCHBAR32(addr) = reg; - // Write reset using a NOP + /* Write reset using a NOP */ write_reset(ctrl); } - /* mrs commands. */ + /* MRS commands */ dram_mrscommands(ctrl); printram("CP5c\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 8aa3068..a0426d4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -20,29 +20,29 @@ #include <stdint.h> -#define BASEFREQ 133 -#define tDLLK 512 +#define BASEFREQ 133 +#define tDLLK 512 -#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) -#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) +#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) +#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) -#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) +#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) #define IS_IVY_CPU_C(x) ((x & 0xf) == 4) #define IS_IVY_CPU_K(x) ((x & 0xf) == 5) #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) -#define NUM_CHANNELS 2 -#define NUM_SLOTRANKS 4 -#define NUM_SLOTS 2 -#define NUM_LANES 8 +#define NUM_CHANNELS 2 +#define NUM_SLOTRANKS 4 +#define NUM_SLOTS 2 +#define NUM_LANES 8 /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ -#define NUM_PATTERNS 4 +#define NUM_PATTERNS 4 typedef struct odtmap_st { u16 rttwr; @@ -85,7 +85,7 @@ u8 base_freq; u16 cas_supported; - /* tLatencies are in units of ns, scaled by x256 */ + /* Latencies are in units of ns, scaled by x256 */ u32 tCK; u32 tAA; u32 tWR; @@ -100,7 +100,7 @@ u32 tCWL; u32 tCMD; /* Latencies in terms of clock cycles - * They are saved separately as they are needed for DRAM MRS commands */ + They are saved separately as they are needed for DRAM MRS commands */ u8 CAS; /* CAS read latency */ u8 CWL; /* CAS write latency */ @@ -138,7 +138,6 @@ dimm_info info; } ramctr_timing; -#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) @@ -152,8 +151,8 @@ #define MAX_CAS 18 #define MIN_CAS 4 -#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) -#define GET_ERR_CHANNEL(x) (x>>16) +#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) +#define GET_ERR_CHANNEL(x) (x >> 16) u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing *ctrl); @@ -177,17 +176,14 @@ void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); -void set_4f8c(void); +void set_wmm_behavior(void); void prepare_training(ramctr_timing *ctrl); -void set_4008c(ramctr_timing *ctrl); +void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); -int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size); - -int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size); +int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); +int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size); #endif diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 8013636..2dc5e9c 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -22,12 +22,10 @@ #include "raminit_native.h" #include "raminit_common.h" -/* Frequency multiplier. */ +/* Frequency multiplier */ static u32 get_FRQ(u32 tCK, u8 base_freq) { - u32 FRQ; - - FRQ = 256000 / (tCK * base_freq); + const u32 FRQ = 256000 / (tCK * base_freq); if (base_freq == 100) { if (FRQ > 12) @@ -49,17 +47,16 @@ u32 refi; if (base_freq == 100) { - /* Get REFI based on MCU frequency using the following rule: + /* Get REFI based on MC frequency using the following rule: * tREFI = 7.8usec * _________________________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * REFI : | 5460 | 6240 | 7020 | 7800 | 8580 | 9360 | */ - static const u32 frq_xs_map[] = - { 5460, 6240, 7020, 7800, 8580, 9360 }; + static const u32 frq_xs_map[] = { 5460, 6240, 7020, 7800, 8580, 9360 }; refi = frq_xs_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get REFI based on MCU frequency using the following rule: + /* Get REFI based on MC frequency using the following rule: * tREFI = 7.8usec * ________________________________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | @@ -78,7 +75,7 @@ u8 xsoffset; if (base_freq == 100) { - /* Get XSOffset based on MCU frequency using the following rule: + /* Get XSOffset based on MC frequency using the following rule: * tXS-offset: tXS = tRFC+10ns. * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | @@ -87,7 +84,7 @@ static const u8 frq_xs_map[] = { 7, 8, 9, 10, 11, 12 }; xsoffset = frq_xs_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get XSOffset based on MCU frequency using the following rule: + /* Get XSOffset based on MC frequency using the following rule: * ___________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | 12 | 14 | @@ -104,7 +101,7 @@ u8 mod; if (base_freq == 100) { - /* Get MOD based on MCU frequency using the following rule: + /* Get MOD based on MC frequency using the following rule: * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * MOD : | 12 | 12 | 14 | 15 | 17 | 18 | @@ -113,7 +110,7 @@ static const u8 frq_mod_map[] = { 12, 12, 14, 15, 17, 18 }; mod = frq_mod_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get MOD based on MCU frequency using the following rule: + /* Get MOD based on MC frequency using the following rule: * _______________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | 18 | 20 | @@ -130,7 +127,7 @@ u8 wlo; if (base_freq == 100) { - /* Get WLO based on MCU frequency using the following rule: + /* Get WLO based on MC frequency using the following rule: * Write leveling output delay * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | @@ -140,7 +137,7 @@ static const u8 frq_wlo_map[] = { 6, 6, 7, 8, 9, 9 }; wlo = frq_wlo_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get WLO based on MCU frequency using the following rule: + /* Get WLO based on MC frequency using the following rule: * Write leveling output delay * ________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | @@ -158,7 +155,7 @@ u8 cke; if (base_freq == 100) { - /* Get CKE based on MCU frequency using the following rule: + /* Get CKE based on MC frequency using the following rule: * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * MOD : | 4 | 4 | 5 | 5 | 6 | 6 | @@ -167,7 +164,7 @@ static const u8 frq_cke_map[] = { 4, 4, 5, 5, 6, 6 }; cke = frq_cke_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get CKE based on MCU frequency using the following rule: + /* Get CKE based on MC frequency using the following rule: * ________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * WLO : | 3 | 3 | 4 | 4 | 5 | 6 | 6 | 7 | @@ -184,7 +181,7 @@ u8 xpdll; if (base_freq == 100) { - /* Get XPDLL based on MCU frequency using the following rule: + /* Get XPDLL based on MC frequency using the following rule: * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * XPDLL : | 17 | 20 | 22 | 24 | 27 | 32 | @@ -193,7 +190,7 @@ static const u8 frq_xpdll_map[] = { 17, 20, 22, 24, 27, 32 }; xpdll = frq_xpdll_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get XPDLL based on MCU frequency using the following rule: + /* Get XPDLL based on MC frequency using the following rule: * _______________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | 29 | 32 | @@ -210,7 +207,7 @@ u8 xp; if (base_freq == 100) { - /* Get XP based on MCU frequency using the following rule: + /* Get XP based on MC frequency using the following rule: * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * XP : | 5 | 5 | 6 | 6 | 7 | 8 | @@ -219,7 +216,7 @@ static const u8 frq_xp_map[] = { 5, 5, 6, 6, 7, 8 }; xp = frq_xp_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get XP based on MCU frequency using the following rule: + /* Get XP based on MC frequency using the following rule: * _______________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 | @@ -236,7 +233,7 @@ u8 aonpd; if (base_freq == 100) { - /* Get AONPD based on MCU frequency using the following rule: + /* Get AONPD based on MC frequency using the following rule: * _____________________________ * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | * AONPD : | 6 | 8 | 8 | 9 | 10 | 11 | @@ -245,7 +242,7 @@ static const u8 frq_aonpd_map[] = { 6, 8, 8, 9, 10, 11 }; aonpd = frq_aonpd_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get AONPD based on MCU frequency using the following rule: + /* Get AONPD based on MC frequency using the following rule: * _______________________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | 11 | 12 | @@ -257,27 +254,24 @@ return aonpd; } +/* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK, u8 base_freq) { u32 comp2; if (base_freq == 100) { - /* Get COMP2 based on MCU frequency using the following rule: - * ______________________________________________________________ - * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | - * COMP : | CA8C264 | C6671E4 | C6671E4 | C446964 | C235924 | C235924 | - */ - - static const u32 frq_comp2_map[] = { 0xCA8C264, 0xC6671E4, 0xC6671E4, 0xC446964, 0xC235924, 0xC235924 }; + static const u32 frq_comp2_map[] = { + // FRQ: 7, 8, 9, 10, 11, 12, + 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, 0x0C235924, 0x0C235924, + }; comp2 = frq_comp2_map[get_FRQ(tCK, 100) - 7]; } else { - /* Get COMP2 based on MCU frequency using the following rule: - * ________________________________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | - * COMP : | D6FF5E4 | CEBDB64 | CA8C264 | C6671E4 | C446964 | C235924 | C235924 | C235924 | - */ - static const u32 frq_comp2_map[] = { 0xD6FF5E4, 0xCEBDB64, 0xCA8C264, - 0xC6671E4, 0xC446964, 0xC235924, 0xC235924, 0xC235924 + static const u32 frq_comp2_map[] = { + /* FRQ: 3, 4, 5, 6, */ + 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, + + /* FRQ: 7, 8, 9, 10, */ + 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, }; comp2 = frq_comp2_map[get_FRQ(tCK, 133) - 3]; } @@ -327,7 +321,7 @@ } if (!ref_100mhz_support && ctrl->base_freq == 100) { - /* Skip unsupported frequency. */ + /* Skip unsupported frequency */ ctrl->tCK++; ivb_normalize_tclk(ctrl, ref_100mhz_support); } @@ -336,29 +330,31 @@ static void find_cas_tck(ramctr_timing *ctrl) { u8 val; - u32 val32; u32 reg32; u8 ref_100mhz_support; /* 100 Mhz reference clock supported */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); ref_100mhz_support = !!((reg32 >> 21) & 0x7); - printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", - ref_100mhz_support ? "yes" : "no"); + printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" + : "no"); /* Find CAS latency */ while (1) { - /* Normalising tCK before computing clock could potentially - * results in lower selected CAS, which is desired. + /* + * Normalising tCK before computing clock could potentially + * result in a lower selected CAS, which is desired. */ ivb_normalize_tclk(ctrl, ref_100mhz_support); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); for (; val <= MAX_CAS; val++) if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) break; + if (val == (MAX_CAS + 1)) { ctrl->tCK++; continue; @@ -368,9 +364,7 @@ } } - val32 = NS2MHZ_DIV256 / ctrl->tCK; - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); - + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; } @@ -378,9 +372,11 @@ static void dram_timing(ramctr_timing *ctrl) { - /* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). - * We cap it at 1200Mhz (DDR3 2400). - * Then, align it to the closest JEDEC standard frequency */ + /* + * Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * We cap it at 1200MHz (DDR3 2400). + * Then, align it to the closest JEDEC standard frequency. + */ if (ctrl->tCK == TCK_1200MHZ) { ctrl->edge_offset[0] = 18; //XXX: guessed ctrl->edge_offset[1] = 8; @@ -389,6 +385,7 @@ ctrl->timC_offset[1] = 8; ctrl->timC_offset[2] = 8; ctrl->pi_coding_threshold = 10; + } else if (ctrl->tCK == TCK_1100MHZ) { ctrl->edge_offset[0] = 17; //XXX: guessed ctrl->edge_offset[1] = 7; @@ -397,6 +394,7 @@ ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_1066MHZ) { ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -405,6 +403,7 @@ ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_1000MHZ) { ctrl->edge_offset[0] = 15; //XXX: guessed ctrl->edge_offset[1] = 6; @@ -413,6 +412,7 @@ ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_933MHZ) { ctrl->edge_offset[0] = 14; ctrl->edge_offset[1] = 6; @@ -421,6 +421,7 @@ ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_900MHZ) { ctrl->edge_offset[0] = 14; //XXX: guessed ctrl->edge_offset[1] = 6; @@ -429,6 +430,7 @@ ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 12; + } else if (ctrl->tCK == TCK_800MHZ) { ctrl->edge_offset[0] = 13; ctrl->edge_offset[1] = 5; @@ -437,6 +439,7 @@ ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_700MHZ) { ctrl->edge_offset[0] = 13; //XXX: guessed ctrl->edge_offset[1] = 5; @@ -445,6 +448,7 @@ ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_666MHZ) { ctrl->edge_offset[0] = 10; ctrl->edge_offset[1] = 4; @@ -453,6 +457,7 @@ ctrl->timC_offset[1] = 4; ctrl->timC_offset[2] = 4; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_533MHZ) { ctrl->edge_offset[0] = 8; ctrl->edge_offset[1] = 3; @@ -461,6 +466,7 @@ ctrl->timC_offset[1] = 3; ctrl->timC_offset[2] = 3; ctrl->pi_coding_threshold = 17; + } else { /* TCK_400MHZ */ ctrl->edge_offset[0] = 6; ctrl->edge_offset[1] = 2; @@ -481,13 +487,14 @@ ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); else ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ @@ -495,7 +502,7 @@ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ @@ -518,21 +525,22 @@ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); - ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); + ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); + ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); - ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); - ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); - ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); - ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); + ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); + ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); + ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); } static void dram_freq(ramctr_timing *ctrl) { if (ctrl->tCK > TCK_400MHZ) { - printk (BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk(BIOS_ERR, + "DRAM frequency is under lowest supported frequency (400 MHz). " + "Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } @@ -543,11 +551,12 @@ /* Step 1 - Set target PCU frequency */ find_cas_tck(ctrl); - /* Frequency multiplier. */ + /* Frequency multiplier */ u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); - /* The PLL will never lock if the required frequency is - * already set. Exit early to prevent a system hang. + /* + * The PLL will never lock if the required frequency is already set. + * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; @@ -557,10 +566,11 @@ /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ - reg1 |= 0x80000000; // set running bit + reg1 |= 0x100; /* Enable 100Mhz REF clock */ + + reg1 |= 0x80000000; /* set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; - int i=0; + int i = 0; printk(BIOS_DEBUG, "PLL busy... "); while (reg1 & 0x80000000) { udelay(10); @@ -584,61 +594,57 @@ static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg, comp2; + u32 reg; int channel; - // IO clock + /* IO clock */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO command + /* IO command */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO control + /* IO control */ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - // Rcomp + /* Perform RCOMP */ printram("RCOMP..."); - reg = 0; - while (reg == 0) { - reg = MCHBAR32(RCOMP_TIMER) & 0x10000; - } + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + printram("done\n"); - // Set comp2 - comp2 = get_COMP2(ctrl->tCK, ctrl->base_freq); - MCHBAR32(CRCOMPOFST2) = comp2; + /* Set COMP2 */ + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK, ctrl->base_freq); printram("COMP2 done\n"); - // Set comp1 + /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); //ch0 - reg = (reg & ~0xe00) | (1 << 9); //odt - reg = (reg & ~0xe00000) | (1 << 21); //clk drive up - reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + reg = MCHBAR32(CRCOMPOFST1_ch(channel)); + reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ + reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ + reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= 0x100; + MCHBAR32(M_COMP) |= (1 << 8); udelay(20); printram("done\n"); } -int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) { int err; - printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", - fast_boot); + printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */ @@ -647,7 +653,7 @@ dram_dimm_mapping(ctrl); } - /* Set MCU frequency */ + /* Set MC frequency */ dram_freq(ctrl); if (!fast_boot) { @@ -656,7 +662,7 @@ } /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xc04eb002; /* Enable crossover */ dram_xover(ctrl); @@ -670,11 +676,11 @@ /* Set scheduler chicken bits */ MCHBAR32(SCHED_CBIT) = 0x10100005; - /* Set CPU specific register */ - set_4f8c(); + /* Set up watermarks and starvation counter */ + set_wmm_behavior(); /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); @@ -696,7 +702,7 @@ if (fast_boot) { restore_timings(ctrl); } else { - /* Do jedec ddr3 reset sequence */ + /* Do JEDEC DDR3 reset sequence */ dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); @@ -740,7 +746,7 @@ normalize_training(ctrl); } - set_4008c(ctrl); + set_read_write_timings(ctrl); write_controller_mr(ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index db5bffc..6a4ba60 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -61,8 +61,7 @@ u16 c1, c2, checksum; /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - pei_data->mrc_output, + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ @@ -75,14 +74,12 @@ pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); /* Save a simple checksum of the seed values */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); - cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); + cmos_write((checksum >> 0) & 0xff, CMOS_OFFSET_MRC_SEED_CHK); + cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK + 1); } static void prepare_mrc_cache(struct pei_data *pei_data) @@ -90,7 +87,7 @@ struct region_device rdev; u16 c1, c2, checksum, seed_checksum; - // preset just in case there is an error + /* Preset just in case there is an error */ pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; @@ -104,14 +101,12 @@ pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); /* Compute seed checksum and compare */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); + c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); + c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; + seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; if (checksum != seed_checksum) { printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); @@ -120,68 +115,64 @@ return; } - if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - &rdev)) { - /* error message printed in find_current_mrc_cache */ + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) { + /* Error message printed in find_current_mrc_cache */ return; } pei_data->mrc_input = rdev_mmap_full(&rdev); pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x\n", - __func__, pei_data->mrc_input, pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, + pei_data->mrc_input_len); } static const char *ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", - "active" + "active", }; -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[2]; int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, + (addr_decoder_common >> 0) & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? 16 : 8, ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? 16 : 8, ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } } +#undef ON_OFF /** * Find PEI executable in coreboot filesystem and execute it. @@ -191,7 +182,7 @@ void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1))); + int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); /* Wait for ME to be ready */ intel_early_me_init(); @@ -246,18 +237,17 @@ if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); - /* For reference print the System Agent version - * after executing the UEFI PEI stage. - */ + /* For reference, print the System Agent version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); - /* Send ME init done for SandyBridge here. This is done - * inside the SystemAgent binary on IvyBridge. */ - if (BASE_REV_SNB == - (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) + /* + * Send ME init done for SandyBridge here. + * This is done inside the SystemAgent binary on IvyBridge. + */ + if (BASE_REV_SNB == (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); else intel_early_me_status(); @@ -265,31 +255,30 @@ report_memory_config(); } -/* These are the location and structure of MRC_VAR data in CAR. - The CAR region looks like this: - +------------------+ -> DCACHE_RAM_BASE - | | - | | - | COREBOOT STACK | - | | - | | - +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE - | | - | MRC HEAP | - | size = 0x5000 | - | | - +------------------+ - | | - | MRC VAR | - | size = 0x4000 | - | | - +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE - + DCACHE_RAM_MRC_VAR_SIZE - +/* + * These are the location and structure of MRC_VAR data in CAR. + * The CAR region looks like this: + * +------------------+ -> DCACHE_RAM_BASE + * | | + * | | + * | COREBOOT STACK | + * | | + * | | + * +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE + * | | + * | MRC HEAP | + * | size = 0x5000 | + * | | + * +------------------+ + * | | + * | MRC VAR | + * | size = 0x4000 | + * | | + * +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE + * + DCACHE_RAM_MRC_VAR_SIZE */ -#define DCACHE_RAM_MRC_VAR_BASE \ - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \ - CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) +#define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) struct mrc_var_data { u32 acpi_timer_flag; @@ -301,14 +290,14 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; - pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; - pei_data->epbar = DEFAULT_EPBAR; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; pei_data->hpet_address = CONFIG_HPET_ADDRESS; - pei_data->thermalbase = 0xfed08000; - pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; - pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { const struct device *dev = pcidev_on_root(1, 0); @@ -322,12 +311,12 @@ { const struct device *dev = pcidev_on_root(0x19, 0); - pei_data->smbusbar = SMBUS_IO_BASE; - pei_data->wdbbar = 0x4000000; - pei_data->wdbsize = 0x1000; - pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; - pei_data->pmbase = DEFAULT_PMBASE; - pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->gbe_enable = dev && dev->enabled; } @@ -361,13 +350,10 @@ } - memcpy(pei_data->spd_addresses, cfg->spd_addresses, - sizeof(pei_data->spd_addresses)); + memcpy(pei_data->spd_addresses, cfg->spd_addresses, sizeof(pei_data->spd_addresses)); + memcpy(pei_data->ts_addresses, cfg->ts_addresses, sizeof(pei_data->ts_addresses)); - memcpy(pei_data->ts_addresses, cfg->ts_addresses, - sizeof(pei_data->ts_addresses)); - - pei_data->ec_present = cfg->ec_present; + pei_data->ec_present = cfg->ec_present; pei_data->ddr3lv_support = cfg->ddr3lv_support; pei_data->nmode = cfg->nmode; @@ -376,15 +362,15 @@ memcpy(pei_data->usb_port_config, cfg->usb_port_config, sizeof(pei_data->usb_port_config)); - pei_data->usb3.mode = cfg->usb3.mode; + pei_data->usb3.mode = cfg->usb3.mode; pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; - pei_data->usb3.preboot_support = cfg->usb3.preboot_support; - pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; + pei_data->usb3.preboot_support = cfg->usb3.preboot_support; + pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; } static void disable_p2p(void) { - /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ + /* Disable PCI-to-PCI bridge early to prevent probing by MRC */ const struct device *const p2p = pcidev_on_root(0x1e, 0); if (p2p && p2p->enabled) return; @@ -394,7 +380,6 @@ void perform_raminit(int s3resume) { - int cbmem_was_initted; struct pei_data pei_data; struct mrc_var_data *mrc_var; @@ -439,18 +424,18 @@ timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); + /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; - /* Sanity check mrc_var location by verifying a known field. */ if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", - mrc_var->pool_base, - mrc_var->pool_base + mrc_var->pool_used); + mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); + } else { printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); - hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); + hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var) / sizeof(u32)); } - cbmem_was_initted = !cbmem_recovery(s3resume); + const int cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 2a91772..3f7f590 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -19,8 +19,8 @@ #include "sandybridge.h" #include <device/dram/ddr3.h> -/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ +/* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */ void read_spd(spd_raw_data *spd, u8 addr, bool id_only); void mainboard_get_spd(spd_raw_data *spd, bool id_only); -#endif /* RAMINIT_H */ +#endif /* RAMINIT_NATIVE_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 8417c2f..b4f61a8 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -21,116 +21,110 @@ #include "raminit_native.h" #include "raminit_common.h" -/* Frequency multiplier. */ +/* Frequency multiplier */ static u32 get_FRQ(u32 tCK) { - u32 FRQ; - FRQ = 256000 / (tCK * BASEFREQ); + const u32 FRQ = 256000 / (tCK * BASEFREQ); + if (FRQ > 8) return 8; if (FRQ < 3) return 3; + return FRQ; } +/* Get REFI based on MC frequency */ static u32 get_REFI(u32 tCK) { - /* Get REFI based on MCU frequency using the following rule: - * _________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | - */ - static const u32 frq_refi_map[] = - { 3120, 4160, 5200, 6240, 7280, 8320 }; + static const u32 frq_refi_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3120, 4160, 5200, 6240, 7280, 8320, + }; return frq_refi_map[get_FRQ(tCK) - 3]; } +/* Get XSOffset based on MC frequency */ static u8 get_XSOffset(u32 tCK) { - /* Get XSOffset based on MCU frequency using the following rule: + /* Get XSOffset based on MC frequency using the following rule: * _________________________ * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | */ - static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; + static const u8 frq_xs_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 6, 7, 8, 10, 11, + }; return frq_xs_map[get_FRQ(tCK) - 3]; } +/* Get MOD based on MC frequency */ static u8 get_MOD(u32 tCK) { - /* Get MOD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | - */ - static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; + static const u8 frq_mod_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 12, 12, 12, 12, 15, 16, + }; return frq_mod_map[get_FRQ(tCK) - 3]; } +/* Get WLO based on MC frequency */ static u8 get_WLO(u32 tCK) { - /* Get WLO based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | - */ - static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; + static const u8 frq_wlo_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 5, 6, 6, 8, 8, + }; return frq_wlo_map[get_FRQ(tCK) - 3]; } +/* Get CKE based on MC frequency */ static u8 get_CKE(u32 tCK) { - /* Get CKE based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | - */ - static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; + static const u8 frq_cke_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3, 3, 4, 4, 5, 6, + }; return frq_cke_map[get_FRQ(tCK) - 3]; } +/* Get XPDLL based on MC frequency */ static u8 get_XPDLL(u32 tCK) { - /* Get XPDLL based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | - */ - static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; + static const u8 frq_xpdll_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 10, 13, 16, 20, 23, 26, + }; return frq_xpdll_map[get_FRQ(tCK) - 3]; } +/* Get XP based on MC frequency */ static u8 get_XP(u32 tCK) { - /* Get XP based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XP : | 3 | 4 | 4 | 5 | 6 | 7 | - */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; + static const u8 frq_xp_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 3, 4, 4, 5, 6, 7, + }; return frq_xp_map[get_FRQ(tCK) - 3]; } +/* Get AONPD based on MC frequency */ static u8 get_AONPD(u32 tCK) { - /* Get AONPD based on MCU frequency using the following rule: - * ________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | - */ - static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; + static const u8 frq_aonpd_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 4, 5, 6, 8, 8, 10, + }; return frq_aonpd_map[get_FRQ(tCK) - 3]; } +/* Get COMP2 based on MC frequency */ static u32 get_COMP2(u32 tCK) { - /* Get COMP2 based on MCU frequency using the following rule: - * ___________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | - */ - static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, - 0xC6369CC, 0xC42514C, 0xC21410C + static const u32 frq_comp2_map[] = { + /* FRQ: 3, 4, 5, 6, 7, 8, */ + 0x0D6BEDCC, 0x0CE7C34C, 0x0CA57A4C, 0x0C6369CC, 0x0C42514C, 0x0C21410C, }; return frq_comp2_map[get_FRQ(tCK) - 3]; } @@ -157,21 +151,23 @@ static void find_cas_tck(ramctr_timing *ctrl) { u8 val; - u32 val32; /* Find CAS latency */ while (1) { - /* Normalising tCK before computing clock could potentially - * results in lower selected CAS, which is desired. + /* + * Normalising tCK before computing clock could potentially + * result in a lower selected CAS, which is desired. */ snb_normalize_tclk(&(ctrl->tCK)); if (!(ctrl->tCK)) die("Couldn't find compatible clock / CAS settings\n"); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); for (; val <= MAX_CAS; val++) if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) break; + if (val == (MAX_CAS + 1)) { ctrl->tCK++; continue; @@ -181,18 +177,18 @@ } } - val32 = NS2MHZ_DIV256 / ctrl->tCK; - printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); - + printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; } static void dram_timing(ramctr_timing *ctrl) { - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. - * Then, align it to the closest JEDEC standard frequency */ + /* + * Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * We cap it at 1200MHz (DDR3 2400). + * Then, align it to the closest JEDEC standard frequency. + */ if (ctrl->tCK == TCK_1066MHZ) { ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -201,6 +197,7 @@ ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->pi_coding_threshold = 13; + } else if (ctrl->tCK == TCK_933MHZ) { ctrl->edge_offset[0] = 14; ctrl->edge_offset[1] = 6; @@ -209,6 +206,7 @@ ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_800MHZ) { ctrl->edge_offset[0] = 13; ctrl->edge_offset[1] = 5; @@ -217,6 +215,7 @@ ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->pi_coding_threshold = 15; + } else if (ctrl->tCK == TCK_666MHZ) { ctrl->edge_offset[0] = 10; ctrl->edge_offset[1] = 4; @@ -225,6 +224,7 @@ ctrl->timC_offset[1] = 4; ctrl->timC_offset[2] = 4; ctrl->pi_coding_threshold = 16; + } else if (ctrl->tCK == TCK_533MHZ) { ctrl->edge_offset[0] = 8; ctrl->edge_offset[1] = 3; @@ -233,6 +233,7 @@ ctrl->timC_offset[1] = 3; ctrl->timC_offset[2] = 3; ctrl->pi_coding_threshold = 17; + } else { ctrl->tCK = TCK_400MHZ; ctrl->edge_offset[0] = 6; @@ -254,13 +255,14 @@ ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); else ctrl->CWL = get_CWL(ctrl->tCK); + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ @@ -268,7 +270,7 @@ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ @@ -288,25 +290,25 @@ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); /* FIXME: Why the -1 ? */ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); + ctrl->tREFI = get_REFI(ctrl->tCK); + ctrl->tMOD = get_MOD(ctrl->tCK); ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); + ctrl->tWLO = get_WLO(ctrl->tCK); + ctrl->tCKE = get_CKE(ctrl->tCK); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK); + ctrl->tXP = get_XP(ctrl->tCK); + ctrl->tAONPD = get_AONPD(ctrl->tCK); } static void dram_freq(ramctr_timing *ctrl) { - if (ctrl->tCK > TCK_400MHZ) { - printk(BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk(BIOS_ERR, + "DRAM frequency is under lowest supported frequency (400 MHz). " + "Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } @@ -316,11 +318,12 @@ find_cas_tck(ctrl); - /* Frequency multiplier. */ + /* Frequency multiplier */ u32 FRQ = get_FRQ(ctrl->tCK); - /* The PLL will never lock if the required frequency is - * already set. Exit early to prevent a system hang. + /* + * The PLL will never lock if the required frequency is already set. + * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; @@ -329,7 +332,7 @@ /* Step 1 - Select frequency in the MCU */ reg1 = FRQ; - reg1 |= 0x80000000; // set running bit + reg1 |= 0x80000000; /* set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i=0; printk(BIOS_DEBUG, "PLL busy... "); @@ -355,61 +358,57 @@ static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg, comp2; + u32 reg; int channel; - // IO clock + /* IO clock */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO command + /* IO command */ FOR_ALL_CHANNELS { MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; } - // IO control + /* IO control */ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - // Rcomp + /* Perform RCOMP */ printram("RCOMP..."); - reg = 0; - while (reg == 0) { - reg = MCHBAR32(RCOMP_TIMER) & 0x10000; - } + while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + ; + printram("done\n"); - // Set comp2 - comp2 = get_COMP2(ctrl->tCK); - MCHBAR32(CRCOMPOFST2) = comp2; + /* Set COMP2 */ + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK); printram("COMP2 done\n"); - // Set comp1 + /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); //ch0 - reg = (reg & ~0xe00) | (1 << 9); //odt - reg = (reg & ~0xe00000) | (1 << 21); //clk drive up - reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up + reg = MCHBAR32(CRCOMPOFST1_ch(channel)); + reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ + reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ + reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= 0x100; + MCHBAR32(M_COMP) |= (1 << 8); udelay(20); printram("done\n"); } -int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, - int s3_resume, int me_uma_size) +int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) { int err; - printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", - fast_boot); + printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */ @@ -418,7 +417,7 @@ dram_dimm_mapping(ctrl); } - /* Set MCU frequency */ + /* Set MC frequency */ dram_freq(ctrl); if (!fast_boot) { @@ -427,7 +426,7 @@ } /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xC04EB002; + MCHBAR32(MRC_REVISION) = 0xc04eb002; /* Enable crossover */ dram_xover(ctrl); @@ -441,11 +440,11 @@ /* Set scheduler chicken bits */ MCHBAR32(SCHED_CBIT) = 0x10100005; - /* Set CPU specific register */ - set_4f8c(); + /* Set up watermarks and starvation counter */ + set_wmm_behavior(); /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~0x20; + MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl); @@ -467,7 +466,7 @@ if (fast_boot) { restore_timings(ctrl); } else { - /* Do jedec ddr3 reset sequence */ + /* Do JEDEC DDR3 reset sequence */ dram_jedecreset(ctrl); printk(BIOS_DEBUG, "Done jedec reset\n"); @@ -511,7 +510,7 @@ normalize_training(ctrl); } - set_4008c(ctrl); + set_read_write_timings(ctrl); write_controller_mr(ctrl); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 7d1c019..db25789 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -42,13 +42,14 @@ { u8 reg8; - // reset rtc power status + /* Reset RTC power status */ reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } -/* Platform has no romstage entry point under mainboard directory, +/* + * Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(void) @@ -68,9 +69,7 @@ early_usb_init(mainboard_usb_ports); } - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* Perform some early chipset init needed before RAM initialization can work */ systemagent_early_init(); printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ffc1d9f..d725a3e 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -60,6 +60,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 @@ -120,246 +121,27 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or))) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -/* Indexed register helper macros */ -#define Gz(r, z) ((r) + ((z) << 8)) -#define Ly(r, y) ((r) + ((y) << 2)) -#define Cx(r, x) ((r) + ((x) << 10)) -#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) -#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) - -/* byte lane training register base addresses */ -#define LANEBASE_B0 0x0000 -#define LANEBASE_B1 0x0200 -#define LANEBASE_B2 0x0400 -#define LANEBASE_B3 0x0600 -#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ -#define LANEBASE_B4 0x1000 -#define LANEBASE_B5 0x1200 -#define LANEBASE_B6 0x1400 -#define LANEBASE_B7 0x1600 - -/* byte lane register offsets */ -#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ -#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ -#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ -#define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ -#define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ - -/* Register definitions */ -#define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ -#define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ -#define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ -#define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ -#define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ -#define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ - -#define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ - -#define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ - -#define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ -#define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ -#define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) - -#define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ -#define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ -#define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ -#define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ - -#define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ -#define GDCRDATACOMP 0x340c /* COMP values register */ - -#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ - -/* MC per-channel registers */ -#define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ -#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ -#define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ -#define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ -#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ -#define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ -#define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ - -/* IOSAV Bytelane Bit-wise error */ -#define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) - -/* IOSAV Bytelane Bit-wise compare mask */ -#define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) - -/* - * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. - * Different counters for transactions that are issued on the ring agents (core or GT) and - * transactions issued in the SA. - */ -#define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) -#define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ -#define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ - -#define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ - -/* IOSAV sub-sequence control registers */ -#define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ -#define IOSAV_n_ADDR_UPD_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ -#define IOSAV_n_SP_CMD_CTL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ -#define IOSAV_n_SUBSEQ_CTL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ -#define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ - -#define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ -#define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ -#define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ -#define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ -#define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ -#define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ -#define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ -#define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ - -#define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ -#define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ - -#define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ -#define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ -#define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ - -/* MC Channel Broadcast registers */ -#define TC_DBP 0x4c00 /* Timings: BIN */ -#define TC_RAP 0x4c04 /* Timings: Regular access */ -#define TC_RWP 0x4c08 /* Timings: Read / Write */ -#define TC_OTHP 0x4c0c /* Timings: Other parameters */ -#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ -#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ -#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ -#define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ -#define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ -#define SCRAMBLING_SEED_2_LOW 0x4c38 /* Scrambling seed 2 low */ -#define SCRAMBLING_SEED_2_HIGH 0x4c3c /* Scrambling seed 2 high */ - -#define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ -#define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ - -/* - * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. - * Different counters for transactions that are issued on the ring agents (core or GT) and - * transactions issued in the SA. - */ -#define SC_PR_CNT_CONFIG 0x4ca8 -#define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ -#define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ -#define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ -#define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ -#define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ - -/* Opportunistic reads configuration during write-major-mode (WMM) */ -#define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ - -#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ - -#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ -#define IOSAV_n_ADDR_UPD(n) Ly(0x4e10, n) /* Address update after command execution */ -#define IOSAV_n_SP_CMD_CTL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ -#define IOSAV_n_SUBSEQ_CTL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ -#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ - -#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ -#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ -#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ -#define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ -#define TC_ZQCAL 0x4e90 /* ZQCAL control register */ -#define TC_RFP 0x4e94 /* Refresh Parameters */ -#define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ -#define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ -#define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ -#define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ - -/* - * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this - * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. - */ -#define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ - -#define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ -#define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ - -#define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ -#define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ - -#define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ -#define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ -#define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ -#define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ - -#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on SNB) */ -#define MAD_ZR 0x5014 /* Address Decode Zones */ -#define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ -#define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ - -#define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ - -#define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ -#define MRC_REVISION 0x5034 /* MRC Revision */ -#define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ -#define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ - -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ - -#define VTD1_BASE 0x5400 /* Base address for IGD */ -#define VTD2_BASE 0x5410 /* Base address for PEG, USB, SATA, etc. */ -#define PAIR_CTL 0x5418 /* Power Aware Interrupt Routing Control */ - -/* PAVP control register, undocumented. Different from PAVPC on PCI config space. */ -#define MMIO_PAVP_CTL 0x5500 /* Bit 0 locks PAVP settings */ - -#define MEM_TRML_ESTIMATION_CONFIG 0x5880 -#define MEM_TRML_THRESHOLDS_CONFIG 0x5888 -#define MEM_TRML_INTERRUPT 0x58a8 - -#define MC_TURBO_PL1 0x59a0 /* Turbo Power Limit 1 parameters */ -#define MC_TURBO_PL2 0x59a4 /* Turbo Power Limit 2 parameters */ - -#define SSKPD_OK 0x5d10 /* 64-bit scratchpad register */ -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ - -/* PCODE will sample SAPM-related registers at the end of Phase 4. */ -#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ -#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -#define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ -#define M_COMP 0x5f08 /* Memory COMP control */ -#define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ - -/* WARNING: Only applies to Sandy Bridge! */ -#define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ - -/** WARNING: Only applies to Ivy Bridge! */ -#define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ -#define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ +/* As there are many registers, define them on a separate file */ +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) @@ -390,7 +172,7 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) @@ -438,7 +220,6 @@ #ifndef __ASSEMBLER__ void intel_sandybridge_finalize_smm(void); - int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -446,8 +227,7 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); -/* mainboard_early_init: Optional mainboard callback run after console init - but before raminit. */ +/* mainboard_early_init: Optional callback, run after console init but before raminit. */ void mainboard_early_init(int s3resume); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); @@ -456,7 +236,8 @@ #include <device/device.h> struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Gerrit-Change-Number: 39599 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/lint/spelling.txt: Explain the commented-out entries
by Angel Pons (Code Review) 18 Mar '20

18 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39618 ) Change subject: util/lint/spelling.txt: Explain the commented-out entries ...................................................................... util/lint/spelling.txt: Explain the commented-out entries If they were removed instead, it would be too easy to end up adding them back again. They are kept in a comment so that they can be tracked. Also, explain why these two entries have been commented out. Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/lint/spelling.txt 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39618/1 diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 1263144..58fe30d 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -7,10 +7,15 @@ # The format of each line is: # mistake||correction # -# Note that "sepc" and "acknowledgement" have been commented out. - +# Some entries may trigger false-positives, and have been commented out: +# +# Reason: Both spellings are correct. #acknowledgement||acknowledgment +# +# Reason: On RISC-V, `SEPC` is the name of a register. #sepc||spec +# + ACII||ASCII Debiab||Debian FTBS||FTBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/39618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd Gerrit-Change-Number: 39618 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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