coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: FSP 2.0: Add fsp_relax_security
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25437 ) Change subject: FSP 2.0: Add fsp_relax_security ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/notify.c: https://review.coreboot.org/c/coreboot/+/25437/18/src/drivers/intel/fsp2_0/… PS18, Line 70: fsp_relax_security Maybe rename this to sound less like an action? E. g.: `should_fsp_relax_security`, `is_fsp_security_relaxed`... Or even, don't we have something like CHIPSET_LOCKDOWN_COREBOOT ? -- To view, visit https://review.coreboot.org/c/coreboot/+/25437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Gerrit-Change-Number: 25437 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:28:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... Patch Set 18: Code-Review+1 (3 comments) https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/acpi.c: https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 339: MCH_VTBAR_MASK; nit: this would fit in 96 chars https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 354: fsp FSP https://review.coreboot.org/c/coreboot/+/25446/18/src/soc/intel/denverton_n… PS18, Line 359: drdh DRHD -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:24:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Implement AES-NI Lock
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25440 ) Change subject: soc/intel/denverton_ns: Implement AES-NI Lock ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Gerrit-Change-Number: 25440 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:22:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25439 ) Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/25439/13/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25439/13/src/soc/intel/denverton_n… PS13, Line 82: msr.lo &= (1 << 3); /* Clear TM enable */ > Need to add ~ to clear the targeted bit. Ping -- To view, visit https://review.coreboot.org/c/coreboot/+/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Steve Mooney Gerrit-MessageType: comment

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25436 ) Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... Patch Set 18: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/25436/18/src/mainboard/scaleway/ta… File src/mainboard/scaleway/tagada/hsio.c: https://review.coreboot.org/c/coreboot/+/25436/18/src/mainboard/scaleway/ta… PS18, Line 23: BL_HSIO_INFORMATION *config) Many of these fit in one line -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:21:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25434 ) Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... Patch Set 16: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/25434/12/src/soc/intel/denverton_n… File src/soc/intel/denverton_ns/cpu.c: https://review.coreboot.org/c/coreboot/+/25434/12/src/soc/intel/denverton_n… PS12, Line 65: needed ? > In English you do not put a space before the ?. Ping -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 16 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:19:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Subrata Banik (Code Review) 19 Mar '20

19 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 23: (3 comments) https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/board_id.c: https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 55: 1F 0x1f https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 43: remove https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 44: } else { : die("Unsupported Board id : 0x%x\n", board_id); : } isn't this check is duplicate between line #25 above and https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… ? you can remove this i believe from here ? -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 23 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:12:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: jasperlake_rvp: Update UART config for JSLRVP
by Subrata Banik (Code Review) 19 Mar '20

19 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: Update UART config for JSLRVP ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/Kconfig: https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe… PS11, Line 53: default 0 if !INTEL_LPSS_UART_FOR_CONSOLE this is good idea to support both UART is same build bt technically its not possible even line #14 also doesn't make sense as chrome will always use LPSS uart better u only keep on support -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Mar 2020 15:08:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Lock SPIBAR
by Patrick Georgi (Code Review) 19 Mar '20

19 Mar '20

Patrick Georgi has uploaded a new patch set (#18) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25441 ) Change subject: soc/intel/denverton_ns: Lock SPIBAR ...................................................................... soc/intel/denverton_ns: Lock SPIBAR - Allow flash access when "Security Override" is set. - Don't lock when relax_security is set. Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/denverton_ns/lpc.c 2 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25441/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/25441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9 Gerrit-Change-Number: 25441 Gerrit-PatchSet: 18 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: add support to read SPD data from SMBus
by Paul Menzel (Code Review) 19 Mar '20

19 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39401 ) Change subject: soc/intel/tigerlake: add support to read SPD data from SMBus ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Mar 2020 14:02:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2020