coreboot-gerrit March 2020

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Change in coreboot[master]: nb/intel/sandybridge: Use loops on DMI register groups
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39631 ) Change subject: nb/intel/sandybridge: Use loops on DMI register groups ...................................................................... nb/intel/sandybridge: Use loops on DMI register groups The DMI link consists of four lanes, grouped in two bundles. Therefore, some DMI registers may be organized as "per-lane" or "per-bundle". This can be seen in the DMI initialization sequence as series of equidistant offsets being programmed with the same value. Make this more obvious by factoring out the register groups using loops. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c 1 file changed, 141 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39631/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 99705bb..99ed2d6 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -20,179 +20,183 @@ { int i; - DMIBAR32(0x0914) |= 0x80000000; - DMIBAR32(0x0934) |= 0x80000000; + DMIBAR32(0x0914) |= 1 << 31; + DMIBAR32(0x0934) |= 1 << 31; for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; - DMIBAR32(0x0a04 + (i << 4)) |= 0x800; + DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000; + DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11); } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30); for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; - DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; + DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000; + DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; } - DMIBAR32(0x090c) &= 0xfe1fffff; - DMIBAR32(0x092c) &= 0xfe1fffff; - DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x7a1842ec; - DMIBAR32(0x090c); // !!! = 0x00000208 - DMIBAR32(0x090c) = 0x00000128; - DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x7a1842ec; - DMIBAR32(0x092c); // !!! = 0x00000208 - DMIBAR32(0x092c) = 0x00000128; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; + for (i = 0; i < 2; i++) { + DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec; + DMIBAR32(0x090c + (i << 5)); // !!! = 0x00000208 + DMIBAR32(0x090c + (i << 5)) = 0x00000128; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + } + DMIBAR32(0x0c04); // !!! = 0x2e680008 DMIBAR32(0x0c04) = 0x2e680008; - DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x3a1842ec; - DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x3a1842ec; - DMIBAR32(0x0910); // !!! = 0x00006300 - DMIBAR32(0x0910) = 0x00004300; - DMIBAR32(0x0930); // !!! = 0x00006300 - DMIBAR32(0x0930) = 0x00004300; - DMIBAR32(0x0a00); // !!! = 0x03042010 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042010 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042010 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042010 - DMIBAR32(0x0a30) = 0x03042018; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0910 + (i << 5)); // !!! = 0x00006300 + DMIBAR32(0x0910 + (i << 5)) = 0x00004300; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042010 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - DMIBAR32(0x0a04); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04) = 0x0c0718f0; - DMIBAR32(0x0a14); // !!! = 0x0c0708f0 - DMIBAR32(0x0a14) = 0x0c0718f0; - DMIBAR32(0x0a24); // !!! = 0x0c0708f0 - DMIBAR32(0x0a24) = 0x0c0718f0; - DMIBAR32(0x0a34); // !!! = 0x0c0708f0 - DMIBAR32(0x0a34) = 0x0c0718f0; - DMIBAR32(0x0900); // !!! = 0x50000000 - DMIBAR32(0x0900) = 0x50000000; - DMIBAR32(0x0920); // !!! = 0x50000000 - DMIBAR32(0x0920) = 0x50000000; - DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - DMIBAR32(0x0904); // !!! = 0x3a1842ec - DMIBAR32(0x0904) = 0x3a1846ec; - DMIBAR32(0x0924); // !!! = 0x3a1842ec - DMIBAR32(0x0924) = 0x3a1846ec; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0900 + (i << 5)); // !!! = 0x50000000 + DMIBAR32(0x0900 + (i << 5)) = 0x50000000; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff + DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1842ec + DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff + DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + } + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; + DMIBAR32(0x0c0c); // !!! = 0x16063400 DMIBAR32(0x0c0c) = 0x00063400; - DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46339008; - DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46339008; - DMIBAR32(0x0700); // !!! = 0x46339008 - DMIBAR32(0x0700) = 0x45339008; - DMIBAR32(0x0720); // !!! = 0x46339008 - DMIBAR32(0x0720) = 0x45339008; - DMIBAR32(0x0700); // !!! = 0x45339008 - DMIBAR32(0x0700) = 0x453b9008; - DMIBAR32(0x0720); // !!! = 0x45339008 - DMIBAR32(0x0720) = 0x453b9008; - DMIBAR32(0x0700); // !!! = 0x453b9008 - DMIBAR32(0x0700) = 0x45bb9008; - DMIBAR32(0x0720); // !!! = 0x453b9008 - DMIBAR32(0x0720) = 0x45bb9008; - DMIBAR32(0x0700); // !!! = 0x45bb9008 - DMIBAR32(0x0700) = 0x45fb9008; - DMIBAR32(0x0720); // !!! = 0x45bb9008 - DMIBAR32(0x0720) = 0x45fb9008; - DMIBAR32(0x0914); // !!! = 0x9021a080 - DMIBAR32(0x0914) = 0x9021a280; - DMIBAR32(0x0934); // !!! = 0x9021a080 - DMIBAR32(0x0934) = 0x9021a280; - DMIBAR32(0x0914); // !!! = 0x9021a280 - DMIBAR32(0x0914) = 0x9821a280; - DMIBAR32(0x0934); // !!! = 0x9021a280 - DMIBAR32(0x0934) = 0x9821a280; - DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03242018; - DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03242018; - DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03242018; - DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03242018; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 + DMIBAR32(0x0700 + (i << 5)) = 0x46339008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46339008 + DMIBAR32(0x0700 + (i << 5)) = 0x45339008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45339008 + DMIBAR32(0x0700 + (i << 5)) = 0x453b9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x453b9008 + DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45bb9008 + DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 + DMIBAR32(0x0914 + (i << 5)) = 0x9021a280; + } + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 + DMIBAR32(0x0914 + (i << 5)) = 0x9821a280; + } + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 + DMIBAR32(0x0a00 + (i << 4)) = 0x03242018; + } + DMIBAR32(0x0258); // !!! = 0x40000600 DMIBAR32(0x0258) = 0x60000600; - DMIBAR32(0x0904); // !!! = 0x3a1846ec - DMIBAR32(0x0904) = 0x2a1846ec; - DMIBAR32(0x0914); // !!! = 0x9821a280 - DMIBAR32(0x0914) = 0x98200280; - DMIBAR32(0x0924); // !!! = 0x3a1846ec - DMIBAR32(0x0924) = 0x2a1846ec; - DMIBAR32(0x0934); // !!! = 0x9821a280 - DMIBAR32(0x0934) = 0x98200280; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1846ec + DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec; + DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9821a280 + DMIBAR32(0x0914 + (i << 5)) = 0x98200280; + } + DMIBAR32(0x022c); // !!! = 0x00c26460 DMIBAR32(0x022c) = 0x00c2403c; early_pch_init_native_dmi_pre(); - /* Write once settings. */ + /* Write once settings */ DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | - (2 << 0) | // 5GT/s - (2 << 12) | // L0s 128 ns to less than 256 ns - (2 << 15); // L1 2 us to less than 4 us + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us - DMIBAR8(DMILCTL) |= 0x20; // Retrain link + DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link while (DMIBAR16(DMILSTS) & TXTRN) ; - DMIBAR8(DMILCTL) |= 0x20; // Retrain link + DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link while (DMIBAR16(DMILSTS) & TXTRN) ; - const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; - const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500; printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* * Virtual Channel resources must match settings in RCBA! * - * Channel Vp and Vm are documented in - * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel - * Pentium Processor Family, and Desktop Intel Celeron Processor Family - * Vol. 2" + * Channel Vp and Vm are documented in: + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium + * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */ /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3 Gerrit-Change-Number: 39631 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: mb/asrock: add Asrock B85M Pro4
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36770 ) Change subject: mb/asrock: add Asrock B85M Pro4 ...................................................................... mb/asrock: add Asrock B85M Pro4 Does not boot... Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/b85m_pro4/Kconfig A src/mainboard/asrock/b85m_pro4/Kconfig.name A src/mainboard/asrock/b85m_pro4/Makefile.inc A src/mainboard/asrock/b85m_pro4/acpi/ec.asl A src/mainboard/asrock/b85m_pro4/acpi/platform.asl A src/mainboard/asrock/b85m_pro4/acpi/superio.asl A src/mainboard/asrock/b85m_pro4/acpi_tables.c A src/mainboard/asrock/b85m_pro4/board_info.txt A src/mainboard/asrock/b85m_pro4/bootblock.c A src/mainboard/asrock/b85m_pro4/cmos.default A src/mainboard/asrock/b85m_pro4/cmos.layout A src/mainboard/asrock/b85m_pro4/data.vbt A src/mainboard/asrock/b85m_pro4/devicetree.cb A src/mainboard/asrock/b85m_pro4/dsdt.asl A src/mainboard/asrock/b85m_pro4/gma-mainboard.ads A src/mainboard/asrock/b85m_pro4/gpio.c A src/mainboard/asrock/b85m_pro4/hda_verb.c A src/mainboard/asrock/b85m_pro4/romstage.c 18 files changed, 837 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36770/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig new file mode 100644 index 0000000..53e95ca --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASROCK_B85M_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + +config MAINBOARD_DIR + string + default asrock/b85m_pro4 + +config MAINBOARD_PART_NUMBER + string + default "B85M Pro4" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig.name b/src/mainboard/asrock/b85m_pro4/Kconfig.name new file mode 100644 index 0000000..4bb4dfd --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B85M_PRO4 + bool "B85M Pro4" diff --git a/src/mainboard/asrock/b85m_pro4/Makefile.inc b/src/mainboard/asrock/b85m_pro4/Makefile.inc new file mode 100644 index 0000000..d9a8d18 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/b85m_pro4/acpi/ec.asl b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl diff --git a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl new file mode 100644 index 0000000..f3b1492 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS,1) +{ +} + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c new file mode 100644 index 0000000..10e5f94 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/b85m_pro4/board_info.txt b/src/mainboard/asrock/b85m_pro4/board_info.txt new file mode 100644 index 0000000..21b2cd3 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/ FIXME +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c new file mode 100644 index 0000000..8e66bed --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout new file mode 100644 index 0000000..4926a45 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asrock/b85m_pro4/data.vbt b/src/mainboard/asrock/b85m_pro4/data.vbt new file mode 100644 index 0000000..93b2418 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb new file mode 100644 index 0000000..3f10a01 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -0,0 +1,130 @@ +chip northbridge/intel/haswell + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0x0 on + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x83" + + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on # xHCI controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # Management Engine interface 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # EHCI controller #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # HD audio controller + subsystemid 0x1849 0x7662 + end + + device pci 1c.0 on end + device pci 1c.1 on end + device pci 1c.2 on end + device pci 1c.3 on end + device pci 1c.4 on end + device pci 1c.5 on end + device pci 1c.6 on end + device pci 1c.7 on end + + device pci 1d.0 on # EHCI controller #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c5c + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 # Keyboard + irq 0x72 = 0x0c # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA controller 1 + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl new file mode 100644 index 0000000..91fe40b --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads new file mode 100644 index 0000000..a5b705e --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b85m_pro4/gpio.c b/src/mainboard/asrock/b85m_pro4/gpio.c new file mode 100644 index 0000000..4400451 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gpio.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c new file mode 100644 index 0000000..7345ad0 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1849c892, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x1849c892), + + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0x0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x21, 0x0221102f), + + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1458a002, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x41c46060), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c new file mode 100644 index 0000000..de1fea4 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + .dimm_channel0_disabled = 0, /* Everything enabled. */ + .dimm_channel1_disabled = 0, /* Everything enabled. */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Gerrit-Change-Number: 36770 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/drivers/nvram: Add function to write RTC
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23585 ) Change subject: libpayload/drivers/nvram: Add function to write RTC ...................................................................... Patch Set 7: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/23585/7/payloads/libpayload/driver… File payloads/libpayload/drivers/nvram.c: https://review.coreboot.org/c/coreboot/+/23585/7/payloads/libpayload/driver… PS7, Line 185: !(statusB & NVRAM_RTC_FORMAT_BINARY) > The encoding is more complicated than "always wrap in bcd coding". […] How about making two helpers: rtc_write_byte(u8 val, u8 addr, u8 statusB); rtc_write_hours(u8 val, u8 addr, u8 statusB); In any case, this can be dealt with in a follow-up. The complementary read function should also be updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/23585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17b4c1ee0dcc649738ac6a7400b087d07213eaf0 Gerrit-Change-Number: 23585 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Mar 2020 12:19:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: add support to read SPD data from SMBus
by Patrick Georgi (Code Review) 19 Mar '20

19 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39401 ) Change subject: soc/intel/tigerlake: add support to read SPD data from SMBus ...................................................................... soc/intel/tigerlake: add support to read SPD data from SMBus Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD data. So, add support to read SPD data from SMBUS. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/include/soc/meminit_jsl.h M src/soc/intel/tigerlake/meminit_jsl.c 2 files changed, 25 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h index b828ae1..421e31d 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -27,6 +27,9 @@ /* Number of DQ byte mappings */ #define DDR_NUM_BYTE_MAPPINGS 6 +/* Number of memory DIMM slots available on Jasper Lake */ +#define NUM_DIMM_SLOT 4 + /* 64-bit Channel identification */ enum { DDR_CH0, @@ -40,17 +43,21 @@ }; enum mem_info_read_type { - READ_SPD_CBFS, /* Find spd file in CBFS. */ - READ_SPD_MEMPTR /* Find spd data from pointer. */ + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SMBUS, /* Read on-module SPD by SMBUS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ }; struct spd_info { enum mem_info_read_type read_type; union spd_data_by { - /* To identify spd file when read_type is READ_SPD_CBFS. */ + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ int spd_index; - /* To find spd data when read_type is READ_SPD_MEMPTR. */ + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; }; diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c index 3247357..c68d210 100644 --- a/src/soc/intel/tigerlake/meminit_jsl.c +++ b/src/soc/intel/tigerlake/meminit_jsl.c @@ -102,15 +102,22 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, const struct spd_info *spd_info, bool half_populated) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); - get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); - print_spd_info((unsigned char *)spd_data_ptr); + if (spd_info->read_type == READ_SMBUS) { + for (int i = 0; i < NUM_DIMM_SLOT; i++) + mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + } else { + uintptr_t spd_data_ptr = 0; + size_t spd_data_len = 0; + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + } /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/tigerlake: Update header to avoid compilation issue
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39630 ) Change subject: soc/intel/tigerlake: Update header to avoid compilation issue ...................................................................... soc/intel/tigerlake: Update header to avoid compilation issue We were including stddefs.h and stdint.h but compilation fails when we use 'bool' type in file. Removing stddef.h and stdint.h and including 'types.h' which includes all data types BUG=None BRANCH=None TEST=Check if compilation passes when bool is used Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/include/soc/meminit_jsl.h 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39630/1 diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h index 588ad5c..66050b2 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h @@ -16,8 +16,7 @@ #ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ #define _SOC_JASPERLAKE_MEMCFG_INIT_H_ -#include <stddef.h> -#include <stdint.h> +#include <types.h> #include <fsp/soc_binding.h> /* Number of dq bits controlled per dqs */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee Gerrit-Change-Number: 39630 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: util/bincfg: Add DDR4 SPD spec
by Felix Held (Code Review) 19 Mar '20

19 Mar '20

Hello Martin Roth, Paul Fagerburg, Rob Barnes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39621 to review the following change. Change subject: util/bincfg: Add DDR4 SPD spec ...................................................................... util/bincfg: Add DDR4 SPD spec Additionally provide a simple script for decoding spd hex files using bincfg. BUG=b:148561711 TEST=Decoded spd files in zork BRANCH=None Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/2067697 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- A util/bincfg/ddr4_registered_spd_512.spec A util/bincfg/ddr4_unbuffered_spd_512.spec A util/scripts/decode_spd.sh M util/scripts/description.md 4 files changed, 776 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39621/1 diff --git a/util/bincfg/ddr4_registered_spd_512.spec b/util/bincfg/ddr4_registered_spd_512.spec new file mode 100644 index 0000000..36f9659 --- /dev/null +++ b/util/bincfg/ddr4_registered_spd_512.spec @@ -0,0 +1,362 @@ +# 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.12.3 – 1 +# Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules +# DDR4 SPD Document Release 3 +# UDIMM Revision 1.1 +# RDIMM Revision 1.1 +# LRDIMM Revision 1.1 +# NVDIMM Revision 1.0 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Base_Module_Type" : 4, + "Hybrid_Media" : 3, + "Is_Hybrid" : 1, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 2, + "Bank_Group_Bits" : 2, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: SDRAM Package Type + "Signal_Loading" : 2, + "Byte_6_reserved" : 2, + "Die_Count" : 3, + "SDRAM_Package_Type" : 1, + + # Byte 7: SDRAM Optional Features + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_7_reserved" : 2, + + # Byte 8: SDRAM Thermal and Refresh Options + "Byte_8_reserved" : 8, + + # Byte 9: Other SDRAM Optional Features + "Byte_9_reserved" : 5, + "Soft_PPR" : 1, + "Post_Package_Repair" : 2, + + # Byte 10: Secondary SDRAM Package Type + "Secondary_Signal_Loading" : 2, + "Secondary_DRAM_Densityt_Ratio" : 2, + "Secondary_Die_Count" : 3, + "Secondary_SDRAM_Package_Type" : 1, + + # Byte 11: Module Nominal Voltage, VDD + "DRAM_VDD_1_2_V" : 2, + "Byte_11_reserved" : 6, + + # Byte 12: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Package_Ranks_per_DIMM" : 3, + "Rank_Mix" : 1, + "Byte_12_reserved" : 1, + + # Byte 13: Module Memory Bus Width + "Primary_bus_width_in_bits" : 3, + "Bus_width_extension_in_bits" : 2, + "Byte_13_reserved" : 3, + + # Byte 14: Module Thermal Sensor + "Byte_14_reserved" : 7, + "Thermal_Sensor" : 1, + + # Byte 15: Extended Module Type + "Extended_Base_Module_Type" : 4, + "Byte_15_reserved" : 4, + + # Byte 16: Reserved + "Byte_16_reserved" : 8, + + # Byte 17: Timebases + "Fine_Timebase" : 2, + "Medium_Timebase" : 2, + "Byte_17_reserved" : 4, + + # Byte 18: SDRAM Minimum Cycle Time (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 19: SDRAM Maximum Cycle Time (tCKAVGmax) + "tCKAVGmax" : 8, + + # Bytes 20 - 23: CAS Latencies Supported + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "CL_19_Supported" : 1, + "CL_20_Supported" : 1, + "CL_21_Supported" : 1, + "CL_22_Supported" : 1, + + "CL_23_Supported" : 1, + "CL_24_Supported" : 1, + "CL_25_Supported" : 1, + "CL_26_Supported" : 1, + "CL_27_Supported" : 1, + "CL_28_Supported" : 1, + "CL_29_Supported" : 1, + "CL_30_Supported" : 1, + + "CL_31_Supported" : 1, + "CL_32_Supported" : 1, + "CL_33_Supported" : 1, + "CL_34_Supported" : 1, + "CL_35_Supported" : 1, + "CL_36_Supported" : 1, + "Byte_23_reserved" : 1, + "CL_range" : 1, + + # Byte 24: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 25: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 26: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_MSN" : 4, + "tRCmin_MSN" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min) + "tRFC1min_LSB" : 8, + "tRFC1min_MSB" : 8, + + # Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min) + "tRFC2min_LSB" : 8, + "tRFC2min_MSB" : 8, + + # Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min) + "tRFC4min_LSB" : 8, + "tRFC4min_MSB" : 8, + + # Byte 36 - 37: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin_MSN" : 4, + "Byte_36_reserved" : 4, + "tFAWmin_LSB" : 8, + + # Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin), + # different bank group + "tRRD_Smin" : 8, + + # Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin), + # same bank group + "tRRD_Lmin" : 8, + + # Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank + # group + "tCCD_Lmin" : 8, + + # Byte 41 - 42: Minimum Write Recovery Time (tWRmin) + "tWRmin_MSN" : 4, + "Byte_41_reserved" : 4, + "tWRmin_MSB" : 8, + + # Byte 43-45: Minimum Write to Read Time (tWTR_Smin), + # different bank group / Minimum Write to Read Time + # (tWTR_Lmin), same bank group + "tWTR_Smin_MSN" : 4, + "tWTR_Lmin_MSN" : 4, + "tWTR_Smin_LSB" : 8, + "tWTR_Lmin_LSB" : 8, + + # Byte 46~59: Reserved, Base Configuration Section + "Byte_46_59_reserved" [14] : 8, + + # Byte 60: Connector to SDRAM Bit Mapping (DQ0-3) + "DQ0_3" : 8, + # Byte 61: Connector to SDRAM Bit Mapping (DQ4-7) + "DQ4_7" : 8, + + # Byte 62: Connector to SDRAM Bit Mapping (DQ8-11) + "DQ8_11" : 8, + + # Byte 63: Connector to SDRAM Bit Mapping (DQ12-15) + "DQ12_15" : 8, + + # Byte 64: Connector to SDRAM Bit Mapping (DQ16-19) + "DQ16_19" : 8, + + # Byte 65: Connector to SDRAM Bit Mapping (DQ20-23) + "DQ20_23" : 8, + + # Byte 66: Connector to SDRAM Bit Mapping (DQ24-27) + "DQ24_27" : 8, + + # Byte 67: Connector to SDRAM Bit Mapping (DQ28-31) + "DQ28_31" : 8, + + # Byte 68: Connector to SDRAM Bit Mapping (CB0-3) + "CB0_3" : 8, + + # Byte 69: Connector to SDRAM Bit Mapping (CB4-7) + "CB4_7" : 8, + + # Byte 70: Connector to SDRAM Bit Mapping (DQ32-35) + "DQ32_35" : 8, + + # Byte 71: Connector to SDRAM Bit Mapping (DQ36-39) + "DQ36_39" : 8, + + # Byte 72: Connector to SDRAM Bit Mapping (DQ40-43) + "DQ40_43" : 8, + + # Byte 73: Connector to SDRAM Bit Mapping (DQ44-47) + "DQ44_47" : 8, + + # Byte 74: Connector to SDRAM Bit Mapping (DQ48-51) + "DQ48_51" : 8, + + # Byte 75: Connector to SDRAM Bit Mapping (DQ52-55) + "DQ52_55" : 8, + + # Byte 76: Connector to SDRAM Bit Mapping (DQ56-59) + "DQ56_59" : 8, + + # Byte 77: Connector to SDRAM Bit Mapping (DQ60-63) + "DQ60_63" : 8, + + # Bytes 78~116: Reserved, Base Configuration Section + # Must be coded as 0x00 + "Byte_78_116_reserved" [39] : 8, + + # Byte 117: Fine Offset for Minimum CAS to CAS Delay Time + # (tCCD_Lmin), same bank group + "tCCD_Lmin" : 8, + + # Byte 118: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Lmin), same bank group + "tRRD_Lmin" : 8, + + # Byte 119: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Smin), different bank group + "tRRD_Smin" : 8, + + # Byte 120: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin" : 8, + + # Byte 121: Fine Offset for Minimum Row Precharge Delay + # Time (tRPmin) + "tRPmin" : 8, + + # Byte 122: Fine Offset for Minimum RAS to CAS Delay + # Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 124: Fine Offset for SDRAM Maximum Cycle Time + # (tCKAVGmax) + "tCKAVGmax" : 8, + + # Byte 125: Fine Offset for SDRAM Minimum Cycle Time + # (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 126 - 127: Cyclical Redundancy Code (CRC) for + # Base Configuration Section + "CRC_Base_Configuration" : 16, + +# Standard Module Parameters - Overlay Bytes 128~191 +# Module Specific Bytes for Registered Memory Module Types + + # Byte 128: Raw Card Extension, Module Nominal Height + "Module_Nominal_Height_Max" : 5, + "Raw_Card_Extension" : 3, + + # Byte 129: Module Maximum Thickness + "Module_Maximum_Thickness_Front" : 4, + "Module_Maximum_Thickness_Back" : 4, + + # Byte 130: Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 131: DIMM Attributes + "Number_of_Registers_used_on_RDIMM" : 2, + "Number_of_DRAMS_on_RDIMM" : 2, + "Register_Type" : 4, + + # Byte 132: RDIMM Thermal Heat Spreader Solution + "Heat_Spreader_Thermal_Characteristics" : 7, + "Heat_Spreader_Solution" : 1, + + # Byte 133 - 134: Register Manufacturer ID Code + "Register_Manufacturer_ID_Code" : 16, + + # Byte 135: Register Revision Number + "Register_Revision_Number" : 8, + + # Byte 136: Address Mapping from Register to DRAM + "Rank_1_Mapping" : 1, + "Byte_136_Reserved" : 7, + + # Byte 137: Register Output Drive Strength for + # Control and Command/Address + "Register_Output_Drive_CKE" : 2, + "Register_Output_Drive_ODT" : 2, + "Register_Output_Drive_Command_Address" : 2, + "Register_Output_Drive_Chip_Select" : 2, + + # Byte 138: Register Output Drive Strength for Clock + "Register_Output_Drive_Strength_Clock_Y0_Y2" : 2, + "Register_Output_Drive_Strength_Clock_Y1_Y3" : 2, + "Byte_138_reserved" : 4, + + # Byte 139 - 191: Reserved + "Byte_139_191" [53] : 8, + +# Unused + # Byte 192 - 253: Unused + "Byte_192_255_unused" [62] : 8, + + # Byte 254 - 255: CRC for SPD Block 1 + "CRC_SPD_Block_1" : 16, + +# Reserved + # Byte 256 - 319: Reserved + "Byte_256_319_reserved" [64] : 8, + +# End User Programmable + # Byte 384 - 511 + "End_User_Programmable" [128] : 8 +} \ No newline at end of file diff --git a/util/bincfg/ddr4_unbuffered_spd_512.spec b/util/bincfg/ddr4_unbuffered_spd_512.spec new file mode 100644 index 0000000..3226435 --- /dev/null +++ b/util/bincfg/ddr4_unbuffered_spd_512.spec @@ -0,0 +1,335 @@ +# 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf +# +# JEDEC Standard No. 21-C +# Page 4.1.2.12.3 – 1 +# Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules +# DDR4 SPD Document Release 3 +# UDIMM Revision 1.1 +# RDIMM Revision 1.1 +# LRDIMM Revision 1.1 +# NVDIMM Revision 1.0 + +{ + # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / + # CRC Coverage + "SPD_Bytes_Used" : 4, + "SPD_Bytes_Total" : 3, + "CRC_Coverage" : 1, + + # Byte 1: SPD Revision + "SPD_Revision" : 8, + + # Byte 2: Key Byte / DRAM Device Type + "DRAM_Device_Type" : 8, + + # Byte 3: Key Byte / Module Type + "Base_Module_Type" : 4, + "Hybrid_Media" : 3, + "Is_Hybrid" : 1, + + # Byte 4: SDRAM Density and Banks + "SDRAM_Capacity" : 4, + "Bank_Address_Bits" : 2, + "Bank_Group_Bits" : 2, + + # Byte 5: SDRAM Addressing + "Column_Address_Bits" : 3, + "Row_Address_Bits" : 3, + "Byte_5_reserved" : 2, + + # Byte 6: SDRAM Package Type + "Signal_Loading" : 2, + "Byte_6_reserved" : 2, + "Die_Count" : 3, + "SDRAM_Package_Type" : 1, + + # Byte 7: SDRAM Optional Features + "Maximum_Activate_Count" : 4, + "Maximum_Activate_Window" : 2, + "Byte_7_reserved" : 2, + + # Byte 8: SDRAM Thermal and Refresh Options + "Byte_8_reserved" : 8, + + # Byte 9: Other SDRAM Optional Features + "Byte_9_reserved" : 5, + "Soft_PPR" : 1, + "Post_Package_Repair" : 2, + + # Byte 10: Secondary SDRAM Package Type + "Secondary_Signal_Loading" : 2, + "Secondary_DRAM_Densityt_Ratio" : 2, + "Secondary_Die_Count" : 3, + "Secondary_SDRAM_Package_Type" : 1, + + # Byte 11: Module Nominal Voltage, VDD + "DRAM_VDD_1_2_V" : 2, + "Byte_11_reserved" : 6, + + # Byte 12: Module Organization + "SDRAM_Device_Width" : 3, + "Number_of_Package_Ranks_per_DIMM" : 3, + "Rank_Mix" : 1, + "Byte_12_reserved" : 1, + + # Byte 13: Module Memory Bus Width + "Primary_bus_width_in_bits" : 3, + "Bus_width_extension_in_bits" : 2, + "Byte_13_reserved" : 3, + + # Byte 14: Module Thermal Sensor + "Byte_14_reserved" : 7, + "Thermal_Sensor" : 1, + + # Byte 15: Extended Module Type + "Extended_Base_Module_Type" : 4, + "Byte_15_reserved" : 4, + + # Byte 16: Reserved + "Byte_16_reserved" : 8, + + # Byte 17: Timebases + "Fine_Timebase" : 2, + "Medium_Timebase" : 2, + "Byte_17_reserved" : 4, + + # Byte 18: SDRAM Minimum Cycle Time (tCKAVGmin) + "tCKAVGmin" : 8, + + # Byte 19: SDRAM Maximum Cycle Time (tCKAVGmax) + "tCKAVGmax" : 8, + + # Bytes 20 - 23: CAS Latencies Supported + "CL_7_Supported" : 1, + "CL_8_Supported" : 1, + "CL_9_Supported" : 1, + "CL_10_Supported" : 1, + "CL_11_Supported" : 1, + "CL_12_Supported" : 1, + "CL_13_Supported" : 1, + "CL_14_Supported" : 1, + + "CL_15_Supported" : 1, + "CL_16_Supported" : 1, + "CL_17_Supported" : 1, + "CL_18_Supported" : 1, + "CL_19_Supported" : 1, + "CL_20_Supported" : 1, + "CL_21_Supported" : 1, + "CL_22_Supported" : 1, + + "CL_23_Supported" : 1, + "CL_24_Supported" : 1, + "CL_25_Supported" : 1, + "CL_26_Supported" : 1, + "CL_27_Supported" : 1, + "CL_28_Supported" : 1, + "CL_29_Supported" : 1, + "CL_30_Supported" : 1, + + "CL_31_Supported" : 1, + "CL_32_Supported" : 1, + "CL_33_Supported" : 1, + "CL_34_Supported" : 1, + "CL_35_Supported" : 1, + "CL_36_Supported" : 1, + "Byte_23_reserved" : 1, + "CL_range" : 1, + + # Byte 24: Minimum CAS Latency Time (tAAmin) + "tAAmin" : 8, + + # Byte 25: Minimum RAS to CAS Delay Time (tRCDmin) + "tRCDmin" : 8, + + # Byte 26: Minimum Row Precharge Delay Time (tRPmin) + "tRPmin" : 8, + + # Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin) + # / Minimum Active to Active/Refresh Delay Time + # (tRCmin) + "tRASmin_MSN" : 4, + "tRCmin_MSN" : 4, + "tRASmin_LSB" : 8, + "tRCmin_LSB" : 8, + + # Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min) + "tRFC1min_LSB" : 8, + "tRFC1min_MSB" : 8, + + # Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min) + "tRFC2min_LSB" : 8, + "tRFC2min_MSB" : 8, + + # Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min) + "tRFC4min_LSB" : 8, + "tRFC4min_MSB" : 8, + + # Byte 36 - 37: Minimum Four Activate Window Delay Time + # (tFAWmin) + "tFAWmin_MSN" : 4, + "Byte_36_reserved" : 4, + "tFAWmin_LSB" : 8, + + # Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin), + # different bank group + "tRRD_Smin" : 8, + + # Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin), + # same bank group + "tRRD_Lmin" : 8, + + # Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank + # group + "tCCD_Lmin" : 8, + + # Byte 41 - 42: Minimum Write Recovery Time (tWRmin) + "tWRmin_MSN" : 4, + "Byte_41_reserved" : 4, + "tWRmin_MSB" : 8, + + # Byte 43-45: Minimum Write to Read Time (tWTR_Smin), + # different bank group / Minimum Write to Read Time + # (tWTR_Lmin), same bank group + "tWTR_Smin_MSN" : 4, + "tWTR_Lmin_MSN" : 4, + "tWTR_Smin_LSB" : 8, + "tWTR_Lmin_LSB" : 8, + + # Byte 46~59: Reserved, Base Configuration Section + "Byte_46_59_reserved" [14] : 8, + + # Byte 60: Connector to SDRAM Bit Mapping (DQ0-3) + "DQ0_3" : 8, + # Byte 61: Connector to SDRAM Bit Mapping (DQ4-7) + "DQ4_7" : 8, + + # Byte 62: Connector to SDRAM Bit Mapping (DQ8-11) + "DQ8_11" : 8, + + # Byte 63: Connector to SDRAM Bit Mapping (DQ12-15) + "DQ12_15" : 8, + + # Byte 64: Connector to SDRAM Bit Mapping (DQ16-19) + "DQ16_19" : 8, + + # Byte 65: Connector to SDRAM Bit Mapping (DQ20-23) + "DQ20_23" : 8, + + # Byte 66: Connector to SDRAM Bit Mapping (DQ24-27) + "DQ24_27" : 8, + + # Byte 67: Connector to SDRAM Bit Mapping (DQ28-31) + "DQ28_31" : 8, + + # Byte 68: Connector to SDRAM Bit Mapping (CB0-3) + "CB0_3" : 8, + + # Byte 69: Connector to SDRAM Bit Mapping (CB4-7) + "CB4_7" : 8, + + # Byte 70: Connector to SDRAM Bit Mapping (DQ32-35) + "DQ32_35" : 8, + + # Byte 71: Connector to SDRAM Bit Mapping (DQ36-39) + "DQ36_39" : 8, + + # Byte 72: Connector to SDRAM Bit Mapping (DQ40-43) + "DQ40_43" : 8, + + # Byte 73: Connector to SDRAM Bit Mapping (DQ44-47) + "DQ44_47" : 8, + + # Byte 74: Connector to SDRAM Bit Mapping (DQ48-51) + "DQ48_51" : 8, + + # Byte 75: Connector to SDRAM Bit Mapping (DQ52-55) + "DQ52_55" : 8, + + # Byte 76: Connector to SDRAM Bit Mapping (DQ56-59) + "DQ56_59" : 8, + + # Byte 77: Connector to SDRAM Bit Mapping (DQ60-63) + "DQ60_63" : 8, + + # Bytes 78~116: Reserved, Base Configuration Section + # Must be coded as 0x00 + "Byte_78_116_reserved" [39] : 8, + + # Byte 117: Fine Offset for Minimum CAS to CAS Delay Time + # (tCCD_Lmin), same bank group + "tCCD_Lmin_Fine_Offset" : 8, + + # Byte 118: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Lmin), same bank group + "tRRD_Lmin_Fine_Offset" : 8, + + # Byte 119: Fine Offset for Minimum Activate to Activate Delay + # Time (tRRD_Smin), different bank group + "tRRD_Smin_Fine_Offset" : 8, + + # Byte 120: Fine Offset for Minimum Active to Active/Refresh + # Delay Time (tRCmin) + "tRCmin_Fine_Offset" : 8, + + # Byte 121: Fine Offset for Minimum Row Precharge Delay + # Time (tRPmin) + "tRPmin_Fine_Offset" : 8, + + # Byte 122: Fine Offset for Minimum RAS to CAS Delay + # Time (tRCDmin) + "tRCDmin_Fine_Offset" : 8, + + # Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin) + "tAAmin_Fine_Offset" : 8, + + # Byte 124: Fine Offset for SDRAM Maximum Cycle Time + # (tCKAVGmax) + "tCKAVGmax_Fine_Offset" : 8, + + # Byte 125: Fine Offset for SDRAM Minimum Cycle Time + # (tCKAVGmin) + "tCKAVGmin_Fine_Offset" : 8, + + # Byte 126 - 127: Cyclical Redundancy Code (CRC) for + # Base Configuration Section + "CRC_Base_Configuration" : 16, + +# Standard Module Parameters - Overlay Bytes 128~191 +# Module Specific Bytes for Unbuffered Memory Module Types + + # Byte 128: Raw Card Extension, Module Nominal Height + "Module_Nominal_Height_Max" : 5, + "Raw_Card_Extension" : 3, + + # Byte 129: Module Maximum Thickness + "Module_Maximum_Thickness_Front" : 4, + "Module_Maximum_Thickness_Back" : 4, + + # Byte 130: Reference Raw Card Used + "Reference_Raw_Card" : 5, + "Reference_Raw_Card_Revision" : 2, + "Reference_Raw_Card_Extension" : 1, + + # Byte 131: Address Mapping from Edge Connector to DRAM + "Rank_1_Mapping" : 1, + "Byte_131_reserved" : 7, + + # Byte 132 - 191: Reserved + "Byte_132_191_reserved" [60] : 8, + +# Unused + # Byte 192 - 253: Unused + "Byte_192_255_unused" [62] : 8, + + # Byte 254 - 255: CRC for SPD Block 1 + "CRC_SPD_Block_1" : 16, + +# Reserved + # Byte 256 - 319: Reserved + "Byte_256_319_reserved" [64] : 8, + +# End User Programmable + # Byte 384 - 511 + "End_User_Programmable" [128] : 8 +} \ No newline at end of file diff --git a/util/scripts/decode_spd.sh b/util/scripts/decode_spd.sh new file mode 100755 index 0000000..8f5a73c --- /dev/null +++ b/util/scripts/decode_spd.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# Parses spd hex files and outputs the contents in various formats +# +# Usage: decode_spd.sh [SPD_HEX_FILE] +# +# Outputs csv, set, and json in same folder as SPD_HEX_FILE +# +# Example: +# decode_spd.sh ../../src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex +# +# Outputs ../../src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.{json|csv|set} +# +# TODO: This script assumes bincfg binary is at ../bincfg/bincfg (which is the +# result of running the bincfg make), and the specs are at +# ../bincfg/*.spec. This dependency should be made more resilliant and +# configurable. + +set -e + +function read8 () { + echo $(( 16#$(xxd -s "${2}" -l 1 -p "${1}") )) +} + +for file in "$@" +do + bintmp=$(mktemp) + outfile="${file%.hex}.set" + + echo "Decoding ${file}, outputing to ${outfile}" + + grep -v '^#' "${file}" | xxd -r -p - "${bintmp}" + dram_type=$(read8 "${bintmp}" 2) + if [ ! "${dram_type}" -eq 12 ] + then + #TODO: Handle other dram types + printf "Error: Expecting dram4 (12), got %d\n" "${dram_type}" + continue + fi + + revision=$(read8 "${bintmp}" 1) + if [ ! "${revision}" -eq $((0x13)) ] + then + printf "Warning: Expecting revision 0x13, got 0x%x.\n" "${revision}" + fi + + module_type=$(read8 "${bintmp}" 3) + case "${module_type}" in + 1) # RDIMM + spec="../bincfg/ddr4_registered_spd_512.spec" + ;; + 2 | 3) #UDIMM | SO-DIMM + spec="../bincfg/ddr4_unbuffered_spd_512.spec" + ;; + * ) + printf "Error: Unhandled module type %d.\n" "${module_type}" + ;; + esac + + ../bincfg/bincfg -d "${spec}" "${bintmp}" "${outfile}" + grep -v '^#' "${outfile}" | sed -e 's/ = $[^,]\+$/: "\1"/g' \ + > "${file%.hex}.json" + grep -v -e '^#' -e '^{' -e '^}' "${outfile}" | sed -e 's/=/,/g' \ + > "${file%.hex}.csv" +done diff --git a/util/scripts/description.md b/util/scripts/description.md index 1f4e7df..32cfd70 100644 --- a/util/scripts/description.md +++ b/util/scripts/description.md @@ -3,6 +3,8 @@ line `Bash` * _cross-repo-cherrypick_ - Pull in patches from another tree from a gerrit repository. `Shell` + * _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files into + various human readiable formats. * _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an fmaptool compatible .fmd format `Bash` * _find-unused-kconfig-symbols.sh_ - Points out Kconfig variables -- To view, visit https://review.coreboot.org/c/coreboot/+/39621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499 Gerrit-Change-Number: 39621 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP] ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 6 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Mar 2020 09:40:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Roja Rani Yarubandi (Code Review) 19 Mar '20

19 Mar '20

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 44: (5 comments) Please review the changes https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… File src/soc/qualcomm/sc7180/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 22: size_t fw_size; > You don't need this, so you can just pass NULL to cbfs_boot_map_with_leak(). Done https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 31: switch (protocol) { > How about just […] Done https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 51: assert(protocol < SE_PROTOCOL_MAX); > will do the changes and update patch Done https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 53: > One more thing I just noticed, it would be good to have *some* kind of sanity checking here to make […] Done https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/q… PS40, Line 75: /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ > nit: QcLib really shouldn't reconfigure any UART registers to begin with when being called from core […] Checking with QcLib team -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 44 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-CC: Taniya Das <tdas(a)codeaurora.org> Gerrit-Comment-Date: Thu, 19 Mar 2020 09:20:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 19 Mar '20

19 Mar '20

Maulik V Vaghela has uploaded a new patch set (#23) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/board_id.c M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c 8 files changed, 200 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 23 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Aamir Bohra (Code Review) 18 Mar '20

18 Mar '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/22/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/board_id.c: https://review.coreboot.org/c/coreboot/+/39195/22/src/mainboard/intel/jaspe… PS22, Line 50: id = (buffer[0] << 8) | buffer[1]; id = (buffer[0] << 8) | buffer[1] & 0x1F? if 5 bits only apply for EC_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 22 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Mar 2020 05:55:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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