coreboot-gerrit March 2020

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by build bot (Jenkins) (Code Review) 20 Mar '20

20 Mar '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 29: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/29/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/29/src/mainboard/intel/jaspe… PS29, Line 43: } trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 29 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Mar 2020 11:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 20 Mar '20

20 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 28: (3 comments) https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/board_id.c: https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 55: 1F > its not done yet […] Done https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 43: > not done Done https://review.coreboot.org/c/coreboot/+/39195/23/src/mainboard/intel/jaspe… PS23, Line 44: } else { : die("Unsupported Board id : 0x%x\n", board_id); : } > not done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 28 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Mar 2020 10:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by build bot (Jenkins) (Code Review) 20 Mar '20

20 Mar '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... Patch Set 28: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/28/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/28/src/mainboard/intel/jaspe… PS28, Line 43: } trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 28 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Mar 2020 10:52:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
by Maulik V Vaghela (Code Review) 20 Mar '20

20 Mar '20

Maulik V Vaghela has uploaded a new patch set (#28) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/board_id.c M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c 7 files changed, 197 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 28 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/dedede: Add Audio support
by Varshit B Pandya (Code Review) 20 Mar '20

20 Mar '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39285 ) Change subject: mb/intel/dedede: Add Audio support ...................................................................... mb/intel/dedede: Add Audio support 1. Configure Audio GPIOs. 2. Set i2c4 configuration. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39285/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e4750ec..4b372b2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -150,7 +150,13 @@ device pci 16.4 off end # HECI 3 device pci 16.5 off end # HECI 4 device pci 17.0 off end # SATA - device pci 19.0 on end # I2C 4 + device pci 19.0 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # I2C #4 device pci 19.1 off end # I2C 5 device pci 19.2 on end # UART 2 device pci 1a.0 on end # eMMC diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8049040..169772b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,6 +13,19 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* R0 : I2S_HP_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S_HP_LRCK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S_HP_AUDIO */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* R3 : I2S_HP_MIC */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R6 : I2S_SPK_LRCK */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : I2S_SPK_AUDIO */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ /* A1 : ESPI_IO1 */ @@ -72,6 +85,13 @@ /* C23 : UART2_CTS_N */ PAD_NC(GPP_C23, DN_20K), + /* D16 : HP_INT_ODL*/ + AD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), + /* D17 : EN_SPK */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D18 : I2S_MCLK */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -126,6 +146,8 @@ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* H9 : AP_I2C_AUDIO_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H15 : I2S_SPK_BCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Gerrit-Change-Number: 39285 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: jasperlake_rvp: UART config for JSLRVP
by Maulik V Vaghela (Code Review) 20 Mar '20

20 Mar '20

Maulik V Vaghela has uploaded a new patch set (#12) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: UART config for JSLRVP ...................................................................... jasperlake_rvp: UART config for JSLRVP Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/39196/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nightfury: Update overridetree.cb
by shkim (Code Review) 20 Mar '20

20 Mar '20

Hello SH Kim, Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39602 to review the following change. Change subject: mb/google/nightfury: Update overridetree.cb ...................................................................... mb/google/nightfury: Update overridetree.cb Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury BUG=none BRANCH=firmware-hatch-12672.B TEST=built and verified touchpad and touchscreen worked Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 --- M src/mainboard/google/hatch/variants/nightfury/overridetree.cb 1 file changed, 21 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39602/1 diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 0cf18e7..6dc3d9f 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -199,47 +199,30 @@ end device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "generic.probed" = "1" - register "generic.wake" = "GPE0_DW0_21" - register "hid_desc_reg_offset" = "0x20" - device i2c 0x20 on end - end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "probed" = "1" + register "wake" = "GPE0_DW0_21" + device i2c 0x15 on end + end end # I2C 0 device pci 15.1 on - chip drivers/i2c/generic - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""atmel,maxtouch"" - register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "91" # 90.5 ms - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" - register "enable_delay_ms" = "1" # 90 ns - register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" - register "probed" = "1" - device i2c 4b on end - end - - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" - register "enable_delay_ms" = "10" - register "enable_off_delay_ms" = "100" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "20" - register "reset_off_delay_ms" = "2" - register "has_power_resource" = "1" - device i2c 10 on end - end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN902C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 Gerrit-Change-Number: 39602 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/generic/max98357a: Add hid check
by Varshit B Pandya (Code Review) 20 Mar '20

20 Mar '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39286 ) Change subject: drivers/generic/max98357a: Add hid check ...................................................................... drivers/generic/max98357a: Add hid check It's possible to re-use the driver for MAX98360A/B/C/D. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 --- M src/drivers/generic/max98357a/max98357a.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39286/1 diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 2b0ec3b..f5a66f1 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -42,7 +42,10 @@ /* Device */ acpigen_write_scope(scope); acpigen_write_device(name); - acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + if (!config->hid) + acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + else + acpigen_write_name_string("_HID", config->hid); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); -- To view, visit https://review.coreboot.org/c/coreboot/+/39286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Gerrit-Change-Number: 39286 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Enable GPIO functions in verstage
by Patrick Georgi (Code Review) 20 Mar '20

20 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39501 ) Change subject: soc/intel: Enable GPIO functions in verstage ...................................................................... soc/intel: Enable GPIO functions in verstage Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9d8fa6f..e7169cf 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -58,6 +58,7 @@ smm-y += smihandler.c smm-y += uart.c +verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c CPPFLAGS_common += -I$(src)/soc/intel/tigerlake CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include -- To view, visit https://review.coreboot.org/c/coreboot/+/39501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Gerrit-Change-Number: 39501 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: don't put empty block in SSDT
by Matt DeVillier (Code Review) 20 Mar '20

20 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39665 ) Change subject: ec/google/chromeec: don't put empty block in SSDT ...................................................................... ec/google/chromeec: don't put empty block in SSDT Check that there are actually USB-PD ports for which to add data to SSDT, before actually generating SSDT data. This prevents and empty scope from being generated on devices without any SB-PD ports, which was breaking parsing/decompilation on some older platforms (eg, Braswell). Test: build/boot google/edgar, verify SSDT table able to be parsed via iasl after dumping. Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39665/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 4dfd44b..47d60d5 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -177,19 +177,14 @@ } } -static void fill_ssdt_typec_device(struct device *dev) +static void fill_ssdt_typec_device(int num_ports) { struct usb_pd_port_caps port_caps; char con_name[] = "CONx"; struct acpi_dp *dsd; - int num_ports; int rv; int i; - rv = google_chromeec_get_num_pd_ports(&num_ports); - if (rv) - return; - acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME); acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID); acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " @@ -220,8 +215,12 @@ void google_chromeec_fill_ssdt_generator(struct device *dev) { + int num_ports; + if (google_chromeec_get_num_pd_ports(&num_ports)) + return; + /* Reference the existing device's scope */ acpigen_write_scope(acpi_device_path(dev)); - fill_ssdt_typec_device(dev); + fill_ssdt_typec_device(num_ports); acpigen_pop_len(); /* Scope */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/39665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e Gerrit-Change-Number: 39665 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020