coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/tglrvp: Update Audio AIC settings for Tiger Lake
by Wonkyu Kim (Code Review) 20 Mar '20

20 Mar '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39466 ) Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/39466/6/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c: https://review.coreboot.org/c/coreboot/+/39466/6/src/mainboard/intel/tglrvp… PS6, Line 84: PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ : PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ : : PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ : PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA * Can you group DMIC0 an DMIC1 like below? PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Gerrit-Change-Number: 39466 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:55:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/tglrvp: Update Audio AIC settings for Tiger Lake
by Wonkyu Kim (Code Review) 20 Mar '20

20 Mar '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39466 ) Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/39466/6/src/mainboard/intel/tglrvp… File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c: https://review.coreboot.org/c/coreboot/+/39466/6/src/mainboard/intel/tglrvp… PS6, Line 87: PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ : PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ : : PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ : PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA * Can you group DMIC0 and DMIC1 like below? PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Gerrit-Change-Number: 39466 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:55:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping SMBus registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39519 ) Change subject: util/inteltool: add code for dumping SMBus registers ...................................................................... Patch Set 12: Code-Review+1 (1 comment) looks good to me; haven't checked the register offsets and names though https://review.coreboot.org/c/coreboot/+/39519/12/util/inteltool/smbus.c File util/inteltool/smbus.c: https://review.coreboot.org/c/coreboot/+/39519/12/util/inteltool/smbus.c@86 PS12, Line 86: size_t i, registers_size = 0, cfg_registers_size = 0, tco_registers_size = 0; one line per 0-initialized variable? -- To view, visit https://review.coreboot.org/c/coreboot/+/39519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f1e1544ceccfa538bb9b0a8c21e10fc42bedb6 Gerrit-Change-Number: 39519 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/tglrvp: Update Audio AIC settings for Tiger Lake
by Srinidhi N Kaushik (Code Review) 20 Mar '20

20 Mar '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39466 ) Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Gerrit-Change-Number: 39466 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:48:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code to dump I2C registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39518 ) Change subject: util/inteltool: add code to dump I2C registers ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/39518/10/util/inteltool/i2c.c File util/inteltool/i2c.c: https://review.coreboot.org/c/coreboot/+/39518/10/util/inteltool/i2c.c@4 PS10, Line 4: * Copyright (C) 2008-2010 by coresystems GmbH : * written by Stefan Reinauer <stepan(a)coresystems.de> : * Copyright (C) 2017 secunet Security Networks AG : * Copyright (C) 2020 Michael Niewöhner <foss(a)mniewoehner.de> since the copyright lines are moved to the AUTHORS file, please remove and add yourself to the authors file if you aren't in there already. probably same for the later patches in this patch train https://review.coreboot.org/c/coreboot/+/39518/10/util/inteltool/i2c.c@146 PS10, Line 146: size_t i, i2c_cfg_registers_size = 0, i2c_registers_size = 0; i'd prefer the two initializations with 0 on separate lines; at least for me this would slightly improve the readability https://review.coreboot.org/c/coreboot/+/39518/10/util/inteltool/i2c.c@152 PS10, Line 152: 4 is the number of i2c buses always 4 on all platforms? i'd expect that this also depends on the chipset generation -- To view, visit https://review.coreboot.org/c/coreboot/+/39518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f97d4fe1695750458920d3c14b35cd51c334225 Gerrit-Change-Number: 39518 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:47:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: gpio: initialize register size variables
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39514 ) Change subject: util/inteltool: gpio: initialize register size variables ...................................................................... Patch Set 6: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/39514/6/util/inteltool/gpio.c File util/inteltool/gpio.c: https://review.coreboot.org/c/coreboot/+/39514/6/util/inteltool/gpio.c@841 PS6, Line 841: int i, j, size = 0, defaults_size = 0; i'd prefer all initializations with a value on a separate line -- To view, visit https://review.coreboot.org/c/coreboot/+/39514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I074a4de7f05a984e78bd7e02e0aa67e28c264340 Gerrit-Change-Number: 39514 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 20:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/tglrvp: Update Audio AIC settings for Tiger Lake
by Srinidhi N Kaushik (Code Review) 20 Mar '20

20 Mar '20

Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Nick Vaccaro, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39466 to look at the new patch set (#6). Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake ...................................................................... mb/tglrvp: Update Audio AIC settings for Tiger Lake Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 28 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39466/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/39466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Gerrit-Change-Number: 39466 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: powermgt: add code for dumping config registers
by Michael Niewöhner (Code Review) 20 Mar '20

20 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39509 ) Change subject: util/inteltool: powermgt: add code for dumping config registers ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/39509/8/util/inteltool/powermgt.c File util/inteltool/powermgt.c: https://review.coreboot.org/c/coreboot/+/39509/8/util/inteltool/powermgt.c@… PS8, Line 899: if (acpi) : pci_free_dev(acpi); > > i'd move this to line 867 after the switch case statement and before the for loop, since the for l […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Gerrit-Change-Number: 39509 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 18:47:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/lenovo/h8: Add a config to indicate whether dock init is needed
by Bill XIE (Code Review) 20 Mar '20

20 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36385 ) Change subject: ec/lenovo/h8: Add a config to indicate whether dock init is needed ...................................................................... ec/lenovo/h8: Add a config to indicate whether dock init is needed Discussed in CB:36093, in the past many lenovo boards need to declare empty h8_mainboard_init_dock() to satisfy h8.c. Since H8_DOCK_EARLY_INIT has a different meaning, it had better add another config to indicate whether dock init is needed, thus eliminating the necessity to declare empty h8_mainboard_init_dock() in the future. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430/mainboard.c M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc D src/mainboard/lenovo/x200/variants/x301/dock.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/Kconfig 21 files changed, 16 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36385/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f3df56a..5cc26d6 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,7 +44,14 @@ bool default n -endif +config H8_NEED_DOCK_INIT + bool "Dock init during boot is necessary" + +if H8_NEED_DOCK_INIT config H8_DOCK_EARLY_INIT bool + +endif # H8_NEED_DOCK_INIT + +endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3a99b52..679b96c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -354,7 +354,7 @@ h8_set_audio_mute(0); -#if !CONFIG(H8_DOCK_EARLY_INIT) +#if CONFIG(H8_NEED_DOCK_INIT) && !CONFIG(H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif } diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index db695b1..88c7884 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2caf1d3..171cb29 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -10,6 +10,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..600b8a6 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -21,6 +21,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select MAINBOARD_HAS_LIBGFXINIT config VBOOT diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index 99a5bd8..a86a90e 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -17,10 +17,6 @@ #include <drivers/intel/gma/int15.h> #include <ec/lenovo/h8/h8.h> -void h8_mainboard_init_dock (void) -{ -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a..6825b6b 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -28,10 +28,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bc8fa29..86351c8 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT select I945_LVDS diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..50b4de1 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -24,10 +24,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index 64cc15b..bc6dcb1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -29,8 +29,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -/* TODO: this device doesnt have a dock */ -void h8_mainboard_init_dock (void) -{ -} diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index fab8a88..8cab040 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -23,6 +23,7 @@ select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select H8_NEED_DOCK_INIT if BOARD_LENOVO_X200 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index f6c2c0c..7e38a78 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -ramstage-y += variants/$(VARIANT_DIR)/dock.c +ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c deleted file mode 100644 index f8a2dc4..0000000 --- a/src/mainboard/lenovo/x200/variants/x301/dock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/h8.h> - -void h8_mainboard_init_dock(void) -{ -} diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index e40c0d3..21edec79 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e3aabf3..27c953b 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select I945_LVDS -- To view, visit https://review.coreboot.org/c/coreboot/+/36385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Gerrit-Change-Number: 36385 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: nb/intel/sandybridge: Deduplicate report_memory_config
by Angel Pons (Code Review) 20 Mar '20

20 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39622 ) Change subject: nb/intel/sandybridge: Deduplicate report_memory_config ...................................................................... nb/intel/sandybridge: Deduplicate report_memory_config Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c A src/northbridge/intel/sandybridge/raminit_shared.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 70 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39622/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 5fb9fdb..7718bf9 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -29,6 +29,7 @@ romstage-y += common.c smm-y += common.c +romstage-y += raminit_shared.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index ca78eb3..34fb499 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -38,13 +38,6 @@ /* FIXME: no ECC support */ /* FIXME: no support for 3-channel chipsets */ -static const char *ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - static void wait_txt_clear(void) { struct cpuid_result cp = cpuid_ext(1, 0); @@ -90,49 +83,6 @@ } } -#define ON_OFF(val) (((val) & 1) ? "on" : "off") - -/* Print the memory controller configuration as read from the memory controller registers. */ -static void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i; - - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - - const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; - - printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); - printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -#undef ON_OFF - /* Return CRC16 match for all SPDs */ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 5b4b46c..6d00afa 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -126,53 +126,6 @@ pei_data->mrc_input_len); } -static const char *ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - -#define ON_OFF(val) (((val) & 1) ? "on" : "off") - -/* Print the memory controller configuration as read from the memory controller registers. */ -static void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); - printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} -#undef ON_OFF - /** * Find PEI executable in coreboot filesystem and execute it. * diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c new file mode 100644 index 0000000..6162544 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_shared.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/mmio.h> +#include <types.h> + +#include "sandybridge.h" + +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + +#define ON_OFF(val) (((val) & 1) ? "on" : "off") + +/* Print the memory controller configuration as read from the memory controller registers. */ +void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + + const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + + printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + (addr_decoder_common >> 0) & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22)); + printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21)); + printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} +#undef ON_OFF diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 07d7904..8fb72cc 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -236,6 +236,7 @@ void mainboard_early_init(int s3resume); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); +void report_memory_config(void); enum platform_type get_platform_type(void); #include <device/device.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/39622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Gerrit-Change-Number: 39622 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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