Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39466 )
Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake
......................................................................
Patch Set 5: Code-Review+1
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Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39466 )
Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake
......................................................................
Patch Set 5:
(1 comment)
> Patch Set 4:
>
> (1 comment)
https://review.coreboot.org/c/coreboot/+/39466/4/src/mainboard/intel/tglrvp…
File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39466/4/src/mainboard/intel/tglrvp…
PS4, Line 7: # GPE configuration
: # Note that GPE events called out in ASL code rely on this
: # route. i.e. If this route changes then the affected GPE
: # offset bits also need to be changed.
: register "pmc_gpe0_dw0" = "GPP_B"
: register "pmc_gpe0_dw1" = "GPP_D"
: register "pmc_gpe0_dw2" = "GPP_E"
> Is it related to Audio?
Not related to Audio. Moved it out
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Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39466
to look at the new patch set (#5).
Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake
......................................................................
mb/tglrvp: Update Audio AIC settings for Tiger Lake
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
4 files changed, 24 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39466/5
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38829 )
Change subject: Documentation: Add new GSoC projects
......................................................................
Documentation: Add new GSoC projects
Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/contributing/project_ideas.md
1 file changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38829/1
diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
index 90164a2..4090e9e 100644
--- a/Documentation/contributing/project_ideas.md
+++ b/Documentation/contributing/project_ideas.md
@@ -179,3 +179,54 @@
### Mentors
* Ron Minnich <rminnich(a)google.com>
+
+## Complete the automatic FMAP generation
+Improve automatically generated FMAPs in coreboot.
+
+FMAPs describe the flash layout, seperating the flash chip into regions
+and sub-regions. coreboot is placed in one or multiple of this regions,
+but usually additional ones are required (Intel ME, MRC cache, ...).
+
+Currently the FMAP needs to manually generated on non-x86 devices or if
+VBOOT is to be used. It would be useful to extend the current tools
+to automatically generated FMAPs based on selected architecture and
+SoC.
+
+### Requirements
+* coreboot knowledge: Have a general concept of the build system
+* other knowledge: Experience with C and bash
+* hardware requirements: Nothing special
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph(a)9elements.com>
+* Christian Walter <christian.walter(a)9elements.com>
+
+## Boardstatus replacement
+The [Board status page](https://coreboot.org/status/board-status.html) allows
+to see last working commit of a board. The page is generated by a cron job
+that runs on a huge git reposity.
+
+Build an open source replacement using exisiting tools and libraries,
+consisting out of a backend, a frontend and client side scripts.
+The backend should connect to an SQL database with can be controlled using
+a REST API / gRPC / XMLRPC connection.
+
+The frontend should use React to display the current board status.
+
+Provide a script that allows to:
+1. Push mainboard details from coreboot master CI
+2. Push mainboard test results from authenticated users containing
+ * commit hash
+ * bootlog
+ * dmesg
+ * timestamps
+ * coreboot config
+
+### Requirements
+* coreboot knowledge: Not required
+* software knowledge: You must be able to implement a nice website with
+ client/server model using an SQL database, authentication and RPC interfaces.
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph(a)9elements.com>
+* Christian Walter <christian.walter(a)9elements.com>
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39698 )
Change subject: acpi: correct the processor devices scope
......................................................................
Patch Set 4:
Okay, NVM. Managed to patch the tables and seems to work well. Just test on other AMD platforms please.
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39397 )
Change subject: util/scripts/gerrit-rebase: Fix shell invocation
......................................................................
util/scripts/gerrit-rebase: Fix shell invocation
The single apostrophe confuses the shell that's calling the command.
Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/scripts/gerrit-rebase
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/39397/1
diff --git a/util/scripts/gerrit-rebase b/util/scripts/gerrit-rebase
index d051103..27ee3c7 100755
--- a/util/scripts/gerrit-rebase
+++ b/util/scripts/gerrit-rebase
@@ -71,7 +71,7 @@
cut -d: -f2-)"
# start rebase process, but fail immediately by enforcing an invalid todo
-GIT_SEQUENCE_EDITOR="echo Ignore this error, it's intentional>" \
+GIT_SEQUENCE_EDITOR="echo 'Ignore this error, it works around a git-rebase limitation'>" \
git rebase -i --onto ${to} ${from} ${to} 2>/dev/null
# write new rebase todo
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39196 )
Change subject: jasperlake_rvp: UART config for JSLRVP
......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe…
File src/mainboard/intel/jasperlake_rvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe…
PS11, Line 14: BOARD_INTEL_JASPERLAKE_RVP
> @Maulik, i don't think this assumption is valid even inside chrome team? […]
@Subrata. It was to differentiate between 2 variants. JSLRVP would use legacy UART while External EC boards would use LPSS.
Both UART won't get selected in single build. Sorry for confusion, I have handled in cleanly in my patch here:
https://review.coreboot.org/c/coreboot/+/39584https://review.coreboot.org/c/coreboot/+/39196/11/src/mainboard/intel/jaspe…
PS11, Line 53: default 0 if !INTEL_LPSS_UART_FOR_CONSOLE
> this is good idea to support both UART is same build bt technically its not possible […]
@Subrata, we use 8250IO in case of jasper Lake RVP boards. We can remove this patch itself since I have corrected it in my another patch.
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Maulik V Vaghela has uploaded a new patch set (#30) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 )
Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
......................................................................
mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
Add memory initialization parameters for Jasper Lake RVP boards
Jasper Lake RVP supports two variants, one with memory LPDDR4
and another with DDR4
Based on board id, mainboard will pass correct memory parameters
to the fsp.
BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.
Change-Id: Idc92363a2148990df16c2068c7986013d015f604
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/intel/jasperlake_rvp/board_id.c
M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex
M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
7 files changed, 197 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/30
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