coreboot-gerrit March 2020

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Change in coreboot[master]: sb/ibexpeak: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 20 Mar '20

20 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37116 ) Change subject: sb/ibexpeak: Use macros instead of hard-coded IDs ...................................................................... sb/ibexpeak: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c 8 files changed, 50 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37116/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..d1d26fe 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,19 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */ +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57 0x3b07 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55 0x3b09 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1 0x3b28 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI 0x3b29 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2 0x3b2e +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1 0x3b34 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2 0x3b3c +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO 0x3b56 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1 0x3b64 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL 0x3b32 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea7..c36ef5e 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -326,7 +326,12 @@ .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c20, + 0x1e20, + PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..c6a73b2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -779,7 +779,11 @@ }; -static const unsigned short pci_device_ids[] = { 0x3b07, 0x3b09, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57, + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..e9dc908 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -615,8 +615,11 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c3a, + PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1, + 0 +}; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..4c00e8e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -247,7 +247,12 @@ .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2, + 0 +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index dd3abfe..589b349 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -98,7 +98,12 @@ .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c22, + 0x1e22, + PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 597d388..540eb6f 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -57,7 +57,10 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL, + 0 +}; static const struct pci_driver pch_thermal __pci_driver = { .ops = &thermal_ops, diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index d31fd70..9e8d19c 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -98,7 +98,11 @@ .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/37116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Gerrit-Change-Number: 37116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/tglrvp: Update Audio AIC settings for Tiger Lake
by Srinidhi N Kaushik (Code Review) 20 Mar '20

20 Mar '20

Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Nick Vaccaro, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39466 to look at the new patch set (#7). Change subject: mb/tglrvp: Update Audio AIC settings for Tiger Lake ...................................................................... mb/tglrvp: Update Audio AIC settings for Tiger Lake Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 34 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39466/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/39466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Gerrit-Change-Number: 39466 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Bora Guvendik (Code Review) 20 Mar '20

20 Mar '20

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 22: GPP_E2 > GPP_C22, H1_FLASH_WP For Deltaur is H1_FLASH_WP is GPP_E2 isn't it. For Deltan it is CPP_C22, -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kevin Chowski <chowski(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-CC: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Comment-Date: Fri, 20 Mar 2020 22:40:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Tim Wawrzynczak (Code Review) 20 Mar '20

20 Mar '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 7: (12 comments) Sorry to be a pain with the SPDX headers, but we'll get used to it 😊 https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/dsdt.asl: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 29: /* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 40: #include <vendorcode/google/chromeos/acpi/vpd.asl> https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 49: Should we hold off on DPTF for now? https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltan/Makefile.inc: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: ## SPDX format please https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltan/gpio.c: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltaur/Makefile.inc: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: ## SPDX https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltaur/gpio.c: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… File src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 1: /* /* * This file is part of the coreboot project. * * Copyright 2020 The coreboot project Authors. * * SPDX-License-Identifier: GPL-2.0-or-later */ https://review.coreboot.org/c/coreboot/+/39502/7/src/mainboard/google/delta… PS7, Line 22: GPP_E2 GPP_C22, H1_FLASH_WP -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kevin Chowski <chowski(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-CC: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Comment-Date: Fri, 20 Mar 2020 22:33:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/siemens/field_pg_m6: Add new mainboard
by Felix Singer (Code Review) 20 Mar '20

20 Mar '20

Hello Nico Huber, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39717 to review the following change. Change subject: [WIP] mb/siemens/field_pg_m6: Add new mainboard ...................................................................... [WIP] mb/siemens/field_pg_m6: Add new mainboard Change-Id: I996d3af330bc7a88951576b2b7793ef42dc7f5c1 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- A src/mainboard/siemens/field_pg_m6/Kconfig A src/mainboard/siemens/field_pg_m6/Kconfig.name A src/mainboard/siemens/field_pg_m6/Makefile.inc A src/mainboard/siemens/field_pg_m6/acpi_tables.c A src/mainboard/siemens/field_pg_m6/board_info.txt A src/mainboard/siemens/field_pg_m6/dsdt.asl A src/mainboard/siemens/field_pg_m6/gma-mainboard.ads A src/mainboard/siemens/field_pg_m6/mainboard.c A src/mainboard/siemens/field_pg_m6/romstage.c A src/mainboard/siemens/field_pg_m6/variant.h A src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc A src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt A src/mainboard/siemens/field_pg_m6/variants/base/data.vbt A src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb A src/mainboard/siemens/field_pg_m6/variants/base/gpio.c 15 files changed, 511 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39717/1 diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig b/src/mainboard/siemens/field_pg_m6/Kconfig new file mode 100644 index 0000000..a944da1 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig @@ -0,0 +1,51 @@ +if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_UART_8250IO + select FSP_USE_REPO + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + +config MAINBOARD_DIR + string + default "siemens/field_pg_m6" + +config VARIANT_DIR + string + default "base" if BOARD_SIEMENS_FIELD_PG_M6_BASE + +config MAINBOARD_VENDOR + string + default "Siemens" + +config MAINBOARD_FAMILY + string + default "Field PG M6" + +config MAINBOARD_PART_NUMBER + string + default "Field PG M6" + +config MAX_CPUS + default 12 + +config DEVICETREE + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" + +config DIMM_SPD_SIZE + default 512 + +endif diff --git a/src/mainboard/siemens/field_pg_m6/Kconfig.name b/src/mainboard/siemens/field_pg_m6/Kconfig.name new file mode 100644 index 0000000..7c9fe21 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Kconfig.name @@ -0,0 +1,4 @@ +comment "Field PG M6" + +config BOARD_SIEMENS_FIELD_PG_M6_BASE + bool "-> Basic port" diff --git a/src/mainboard/siemens/field_pg_m6/Makefile.inc b/src/mainboard/siemens/field_pg_m6/Makefile.inc new file mode 100644 index 0000000..f676410 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/field_pg_m6/acpi_tables.c b/src/mainboard/siemens/field_pg_m6/acpi_tables.c new file mode 100644 index 0000000..3b44754 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/acpi_tables.c @@ -0,0 +1 @@ +/* Nothing here */ diff --git a/src/mainboard/siemens/field_pg_m6/board_info.txt b/src/mainboard/siemens/field_pg_m6/board_info.txt new file mode 100644 index 0000000..cb5b428 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/siemens/field_pg_m6/dsdt.asl b/src/mainboard/siemens/field_pg_m6/dsdt.asl new file mode 100644 index 0000000..daddd97 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/cannonlake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/cannonlake/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/cannonlake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads new file mode 100644 index 0000000..66ce273 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/gma-mainboard.ads @@ -0,0 +1,36 @@ +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; version 2 of +-- the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely + -- have a high-resolution display attached first, `Internal` last. + + ports : constant Port_List := + (DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/field_pg_m6/mainboard.c b/src/mainboard/siemens/field_pg_m6/mainboard.c new file mode 100644 index 0000000..2624291 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <soc/gpio.h> +#include "variant.h" + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/field_pg_m6/romstage.c b/src/mainboard/siemens/field_pg_m6/romstage.c new file mode 100644 index 0000000..91c4f66 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/romstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct cnl_mb_cfg cfg = { + .spd = { + [0] = { READ_SMBUS, { 0x50 << 1 }}, + [2] = { READ_SMBUS, { 0x52 << 1 }}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, + }; + cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); + memupd->FspmConfig.EccSupport = 1; + memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; +} diff --git a/src/mainboard/siemens/field_pg_m6/variant.h b/src/mainboard/siemens/field_pg_m6/variant.h new file mode 100644 index 0000000..b51c9df --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variant.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _VARIANT_H_ +#define _VARIANT_H_ + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc new file mode 100644 index 0000000..c291d45 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt new file mode 100644 index 0000000..199a44e --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Field PG M6 diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt new file mode 100644 index 0000000..f79a6005 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/data.vbt Binary files differ diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb new file mode 100644 index 0000000..2966da3 --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/devicetree.cb @@ -0,0 +1,125 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # TODO + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[16]" = "1" + + register "PcieClkSrcUsage[2]" = "0" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[13]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[14]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[15]" = "PCIE_CLK_NOTUSED" + + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[7]" = "7" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 x4 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c new file mode 100644 index 0000000..dbcdd4d --- /dev/null +++ b/src/mainboard/siemens/field_pg_m6/variants/base/gpio.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO 0x0000003444000200 */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO 0x0000003544000300 */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO 0x0000003644000300 */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO 0x0000003a44000300 */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO 0x0000003b44000201 */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO 0x0000005044000300 */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO 0x0000005144000300 */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA 0x0000005884800402 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO 0x0000007544000201 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO 0x0000007644800100 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO 0x0000006d84000201 */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO 0x0000006e84800102 */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* GPIO_RSVD_9 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_9, NONE), +/* GPIO_RSVD_10 GPIO 0x0000000040000300 */ PAD_NC(GPIO_RSVD_10, NONE), +/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO 0x00000067c4000200 */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO 0x0000001c04000201 */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO 0x0000001d04000201 */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO 0x0000004884000102 */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO 0x0000005244800102 */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO 0x0000005744000201 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO 0x0000005944000201 */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO 0x0000002484000201 */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO 0x0000003584000201 */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO 0x0000003844800000 */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO 0x0000003944000200 */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK 0x0000004644000700 */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA 0x0000004744000702 */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP 0x0000003344000702 */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996d3af330bc7a88951576b2b7793ef42dc7f5c1 Gerrit-Change-Number: 39717 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: powermgt: add Sunrise Point config registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39510 ) Change subject: util/inteltool: powermgt: add Sunrise Point config registers ...................................................................... Patch Set 10: Code-Review+1 haven't checked the register offsets/names; looks good to me though -- To view, visit https://review.coreboot.org/c/coreboot/+/39510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b00a102b739a3d364ecc881279212a860dac40 Gerrit-Change-Number: 39510 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 21:07:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: powermgt: add code for dumping config registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39509 ) Change subject: util/inteltool: powermgt: add code for dumping config registers ...................................................................... util/inteltool: powermgt: add code for dumping config registers This adds the code required to dump config registers. Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/inteltool/powermgt.c 1 file changed, 39 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 70f8c48..125c739 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -670,12 +670,14 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { size_t i, pm_registers_size = 0; + size_t pm_cfg_registers_size = 0; uint16_t pmbase; const io_register_t *pm_registers; + const io_register_t *pm_cfg_registers; uint64_t pwrmbase_phys = 0; - struct pci_dev *acpi; + struct pci_dev *acpi = NULL; - printf("\n========== PMBASE/ABASE =========\n\n"); + printf("\n========== ACPI/PMC =========\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_3400: @@ -813,7 +815,6 @@ return 1; } pmbase = pci_read_word(acpi, 0x40) & 0xfffc; - pci_free_dev(acpi); pm_registers = i82371xx_pm_registers; pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers); @@ -855,7 +856,6 @@ } pmbase = pci_read_word(acpi, 0x40) & ~0xff; pwrmbase_phys = pci_read_long(acpi, 0x48) & ~0xfff; - pci_free_dev(acpi); pm_registers = sunrise_pm_registers; pm_registers_size = ARRAY_SIZE(sunrise_pm_registers); @@ -865,6 +865,41 @@ return 1; } + for (i = 0; i < pm_cfg_registers_size; i++) { + switch (pm_cfg_registers[i].size) { + case 8: + printf("0x%04x: 0x%08x (%s)\n" + " 0x%08x\n", + pm_cfg_registers[i].addr, + pci_read_long(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name, + pci_read_long(acpi, pm_cfg_registers[i].addr+4)); + break; + case 4: + printf("0x%04x: 0x%08x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_long(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_word(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + pm_cfg_registers[i].addr, + pci_read_byte(acpi, pm_cfg_registers[i].addr), + pm_cfg_registers[i].name); + break; + } + } + + if (acpi) + pci_free_dev(acpi); + + printf("\n========== ABASE/PMBASE =========\n\n"); printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i = 0; i < pm_registers_size; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/39509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Gerrit-Change-Number: 39509 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: powermgt: add code for dumping config registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39509 ) Change subject: util/inteltool: powermgt: add code for dumping config registers ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/39509/8/util/inteltool/powermgt.c File util/inteltool/powermgt.c: https://review.coreboot.org/c/coreboot/+/39509/8/util/inteltool/powermgt.c@… PS8, Line 899: if (acpi) : pci_free_dev(acpi); > Done oh, didn't spot that. yeah, you're right -- To view, visit https://review.coreboot.org/c/coreboot/+/39509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Gerrit-Change-Number: 39509 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 21:05:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: powermgt: add code for dumping config registers
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39509 ) Change subject: util/inteltool: powermgt: add code for dumping config registers ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Gerrit-Change-Number: 39509 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 21:04:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: spi: make Sunrise Point dumping work
by Felix Held (Code Review) 20 Mar '20

20 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39564 ) Change subject: util/inteltool: spi: make Sunrise Point dumping work ...................................................................... Patch Set 3: Code-Review-1 (2 comments) haven't checked the register offsets/names and found a bug; the rest looks good https://review.coreboot.org/c/coreboot/+/39564/3/util/inteltool/spi.c File util/inteltool/spi.c: https://review.coreboot.org/c/coreboot/+/39564/3/util/inteltool/spi.c@260 PS3, Line 260: static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) { moving this line one down seems to be a bug to me https://review.coreboot.org/c/coreboot/+/39564/3/util/inteltool/spi.c@428 PS3, Line 428: *(uint8_t *) those could be replaced in some follow-up patch. maybe that patch even exists; wasn't in this patch train though -- To view, visit https://review.coreboot.org/c/coreboot/+/39564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d4dae07d493414d6c7a0c4593ff28dd5b60faa Gerrit-Change-Number: 39564 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Mar 2020 21:00:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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