coreboot-gerrit February 2020

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Change in coreboot[master]: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
by James (Code Review) 06 Feb '21

06 Feb '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39074 ) Change subject: sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable ...................................................................... sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable If the Management Engine is in an inoperable mode, e.g. if me_cleaner is used, hide the Management Engine Interface device so the OS doesn't try to access it. Enable the MEI in device trees of Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/ibexpeak/me.c 11 files changed, 18 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39074/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index b03e2f9..3c0d278 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -54,7 +54,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e057..fb2876f 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -74,7 +74,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 53bd16f..222825b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index c91b04e..314ca43 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index ee612cd..7483c46 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -75,7 +75,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 2d15d87..510fa9e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -71,7 +71,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 5ae1427..7e9d9bb 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171..97674d8 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,7 +66,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 15f99cd..280dcb0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -692,6 +692,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -717,9 +719,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..88558e3 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -681,6 +681,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -721,9 +723,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..aa1c002 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -577,6 +577,8 @@ switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_ERROR_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: intel_me_hide(dev); break; @@ -595,9 +597,7 @@ */ break; - case ME_ERROR_BIOS_PATH: case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Gerrit-Change-Number: 39074 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

6 19

Change in ...coreboot[master]: mb/apple/macbookair4_2: ACPI support for EC
by Evgeny Zinoviev (Code Review) 05 Feb '21

05 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33103 Change subject: mb/apple/macbookair4_2: ACPI support for EC ...................................................................... mb/apple/macbookair4_2: ACPI support for EC Added ACPI support for battery, AC and LID. I don't have MacBook Air 4,2 to test, but: - I tested it on 5,2; - I found decompiled DSDT for 4,2 and compared registers and bits, they are the same as on 5,2. So it should work. Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/acpi/ec.asl 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33103/1 diff --git a/src/mainboard/apple/macbookair4_2/acpi/ec.asl b/src/mainboard/apple/macbookair4_2/acpi/ec.asl index f70cb3d..cd74865 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/ec.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/ec.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,10 +13,6 @@ * GNU General Public License for more details. */ -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - Name (_GPE, 23) -/* FIXME: EC support */ -} +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac_60.asl> +#include <ec/apple/acpi/lid_60.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/33103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Gerrit-Change-Number: 33103 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: ec/apple: ACPI code for Apple MacBooks
by Evgeny Zinoviev (Code Review) 05 Feb '21

05 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33102 Change subject: ec/apple: ACPI code for Apple MacBooks ...................................................................... ec/apple: ACPI code for Apple MacBooks Move ACPI code for Apple MacBooks to a separate directory to avoid it's duplication in mainboards. AC and LID implementation files are named by EC register that's used in them. Older generations (macbook2,1) use 0x01 while newer generations like 2011-2012 Airs use 0x60. Battery registers seem to be the same. Tested on MacBook Air 5,2. Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/ec/apple/acpi/ac_01.asl A src/ec/apple/acpi/ac_60.asl A src/ec/apple/acpi/battery.asl A src/ec/apple/acpi/ec.asl A src/ec/apple/acpi/lid_01.asl A src/ec/apple/acpi/lid_60.asl 6 files changed, 405 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33102/1 diff --git a/src/ec/apple/acpi/ac_01.asl b/src/ec/apple/acpi/ac_01.asl new file mode 100644 index 0000000..86966ae8 --- /dev/null +++ b/src/ec/apple/acpi/ac_01.asl @@ -0,0 +1,42 @@ + + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + 1, + HPAC, 1, /* AC status */ + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } +} diff --git a/src/ec/apple/acpi/ac_60.asl b/src/ec/apple/acpi/ac_60.asl new file mode 100644 index 0000000..76adea1 --- /dev/null +++ b/src/ec/apple/acpi/ac_60.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x60), + , 1, + HPAC, 1, /* AC status */ + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } +} diff --git a/src/ec/apple/acpi/battery.asl b/src/ec/apple/acpi/battery.asl new file mode 100644 index 0000000..f1706be --- /dev/null +++ b/src/ec/apple/acpi/battery.asl @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, +} + +Field(ERAM, ByteAcc, Lock, Preserve) +{ + Offset(0x24), + SBDW, 16, +} + +Method(SBPC, 0, NotSerialized) +{ + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } +} + +Method(SBRW, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) +} + +Method(SBRB, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) +} + +Device(BAT0) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } +} diff --git a/src/ec/apple/acpi/ec.asl b/src/ec/apple/acpi/ec.asl new file mode 100644 index 0000000..982011c --- /dev/null +++ b/src/ec/apple/acpi/ec.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_PRW, 0, NotSerialized) + { + return (Package () { 0x23, 0x04 }) + } + + Method(_INI, 0, NotSerialized) + { + } + +#include "battery.asl" +} diff --git a/src/ec/apple/acpi/lid_01.asl b/src/ec/apple/acpi/lid_01.asl new file mode 100644 index 0000000..88ad045 --- /dev/null +++ b/src/ec/apple/acpi/lid_01.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + + Offset(0x02), + WKLD, 1, /* Lid wake */ + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x1d, 0x03 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } + } +} diff --git a/src/ec/apple/acpi/lid_60.asl b/src/ec/apple/acpi/lid_60.asl new file mode 100644 index 0000000..e0836b6 --- /dev/null +++ b/src/ec/apple/acpi/lid_60.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x60), + LIDS, 1, /* Lid status */ + + Offset(0x68), + WKLD, 1, /* Lid wake */ + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + + Method(_PRW, 0, NotSerialized) + { + Return (Package() { 0x23, 0x04 }) + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + Store(1, WKLD) + } else { + Store(0, WKLD) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Gerrit-Change-Number: 33102 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

8 45

Change in coreboot[master]: [WIP]lib/edid_fill_fb: Support multiple framebuffers
by Patrick Rudolph (Code Review) 13 Jan '21

13 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39002 ) Change subject: [WIP]lib/edid_fill_fb: Support multiple framebuffers ...................................................................... [WIP]lib/edid_fill_fb: Support multiple framebuffers Add an implementation that supports multiple framebuffers. This will allow to compile in multiple graphic drivers and select at runtime which one to choose. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/edid.h A src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/kukui/mainboard.c 4 files changed, 174 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39002/1 diff --git a/src/include/edid.h b/src/include/edid.h index a97b99b..7c3e9c8 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -104,11 +104,12 @@ EDID_ABSENT, }; +struct edid_fb_info; /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); +struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h new file mode 100644 index 0000000..6d2f9a6 --- /dev/null +++ b/src/include/framebuffer_info.h @@ -0,0 +1,45 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FRAMEBUFFER_INFO_H_ +#define __FRAMEBUFFER_INFO_H_ + +#include <stdint.h> +#include <stdbool.h> +#include <commonlib/coreboot_tables.h> + +struct edid_fb_info; +struct edid_fb_info *fb_new_framebuffer_info(void); + +bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel, uint8_t reserved_mask_pos, + uint8_t reserved_mask_size, uint8_t red_mask_pos, + uint8_t red_mask_size, uint8_t green_mask_pos, + uint8_t green_mask_size, uint8_t blue_mask_pos, + uint8_t blue_mask_size); + +bool fb_fill_framebuffer_info(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel); + +void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, + enum lb_fb_orientation orientation); + +#endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 1b38ead..3abcdd0 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -23,75 +23,137 @@ #include <console/console.h> #include <edid.h> #include <boot/coreboot_tables.h> +#include <framebuffer_info.h> +#include <string.h> +#include <stdlib.h> -static int fb_valid; -static struct lb_framebuffer edid_fb; +struct edid_fb_info { + bool valid; + struct lb_framebuffer edid_fb; + struct edid_fb_info *next; +}; +static struct edid_fb_info *list; + +/* + * Allocate a new framebuffer info struct on heap. + * Returns NULL on error. + */ +struct edid_fb_info *fb_new_framebuffer_info(void) +{ + struct edid_fb_info *ret; + ret = malloc(sizeof(struct edid_fb_info)); + if (ret) { + memset(ret, 0, sizeof(struct edid_fb_info)); + ret->next = list; + list = ret; + } + return ret; +} + +/* + * Fills a provided framebuffer info struct and sets the valid bit to true. + * Returns false on error. + */ +bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel, uint8_t reserved_mask_pos, + uint8_t reserved_mask_size, uint8_t red_mask_pos, + uint8_t red_mask_size, uint8_t green_mask_pos, + uint8_t green_mask_size, uint8_t blue_mask_pos, + uint8_t blue_mask_size) +{ + /* Validate */ + if (!info) + return false; + + if (!x_resolution || !y_resolution || !bytes_per_line || !bits_per_pixel) { + printk(BIOS_ERR, "%s: Invalid framebuffer data provided\n", __func__); + return false; + } + + printk(BIOS_INFO, "framebuffer_info: bytes_per_line: %d, bits_per_pixel: %d\n " + " x_res x y_res: %d x %d, size: %d at %p\n", + bytes_per_line, bits_per_pixel, x_resolution, + y_resolution, (bytes_per_line * y_resolution), + (void *)fb_addr); + + /* Update */ + info->edid_fb.physical_address = fb_addr; + info->edid_fb.x_resolution = x_resolution; + info->edid_fb.y_resolution = y_resolution; + info->edid_fb.bytes_per_line = bytes_per_line; + info->edid_fb.bits_per_pixel = bits_per_pixel; + info->edid_fb.reserved_mask_pos = reserved_mask_pos; + info->edid_fb.reserved_mask_size = reserved_mask_size; + info->edid_fb.red_mask_pos = red_mask_pos; + info->edid_fb.red_mask_size = red_mask_size; + info->edid_fb.green_mask_pos = green_mask_pos; + info->edid_fb.green_mask_size = green_mask_size; + info->edid_fb.blue_mask_pos = blue_mask_pos; + info->edid_fb.blue_mask_size = blue_mask_size; + info->valid = true; + + return true; +} + +/* Fills a framebuffer into struct with common values for 32/24/16bpp framebuffers */ +bool fb_fill_framebuffer_info(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel) +{ + if (!info) + return false; + + switch (bits_per_pixel) { + case 32: + case 24: + /* packed into 4-byte words */ + return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, + bytes_per_line, bits_per_pixel, 24, 8, 16, 8, 8, 8, 0, 8); + break; + case 16: + /* packed into 2-byte words */ + return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, + bytes_per_line, bits_per_pixel, 0, 0, 11, 5, 5, 6, 0, 5); + break; + default: + printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, bits_per_pixel); + return false; + } + return true; +} + +void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, + enum lb_fb_orientation orientation) +{ + if (!info) + return; + + info->edid_fb.orientation = orientation; +} /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) { - edid_fb.physical_address = fb_addr; - edid_fb.x_resolution = edid->x_resolution; - edid_fb.y_resolution = edid->y_resolution; - edid_fb.bytes_per_line = edid->bytes_per_line; - /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention - * nowadays seems to be to round it up to the nearest reasonable - * boundary, because otherwise the byte-packing is hideous. - * So, for example, in RGB with no alpha, the bytes are still - * packed into 32-bit words, the so-called 32bpp-no-alpha mode. - * Or, in 5:6:5 mode, the bytes are also packed into 32-bit words, - * and in 4:4:4 mode, they are packed into 16-bit words. - * Good call on the hardware guys part. - * It's not clear we're covering all cases here, but - * I'm not sure with grahpics you ever can. - */ - edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel; - edid_fb.reserved_mask_pos = 0; - edid_fb.reserved_mask_size = 0; - switch (edid->framebuffer_bits_per_pixel) { - case 32: - case 24: - /* packed into 4-byte words */ - edid_fb.reserved_mask_pos = 24; - edid_fb.reserved_mask_size = 8; - edid_fb.red_mask_pos = 16; - edid_fb.red_mask_size = 8; - edid_fb.green_mask_pos = 8; - edid_fb.green_mask_size = 8; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - edid_fb.red_mask_pos = 11; - edid_fb.red_mask_size = 5; - edid_fb.green_mask_pos = 5; - edid_fb.green_mask_size = 6; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - edid->framebuffer_bits_per_pixel); - return; - } - - fb_valid = 1; -} - -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation) -{ - edid_fb.orientation = orientation; + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return NULL; + fb_fill_framebuffer_info(info, fb_addr, edid->x_resolution, edid->y_resolution, + edid->bytes_per_line, edid->framebuffer_bits_per_pixel); + return info; } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { - if (!fb_valid) - return -1; - - *framebuffer = edid_fb; - - return 0; + for (struct edid_fb_info *i = list; i != NULL; i = i->next) { + if (i->valid) { + *framebuffer = i->edid_fb; + return 0; + } + } + return -1; } diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d..4033d51 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -172,8 +172,10 @@ return false; } mtk_ddp_mode_set(edid); - set_vbe_mode_info_valid(edid, 0); - set_vbe_framebuffer_orientation(panel->s->orientation); + struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0); + if (info) + fb_fill_framebuffer_set_orientation(info, panel->s->orientation); + return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Gerrit-Change-Number: 39002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 86

Change in coreboot[master]: arch/x86/car: Remove runtime stack alignment enforcing
by Arthur Heymans (Code Review) 05 Jan '21

05 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37368 ) Change subject: arch/x86/car: Remove runtime stack alignment enforcing ...................................................................... arch/x86/car: Remove runtime stack alignment enforcing This is now checked at buildtime. Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 6 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37368/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 73618d9..be96633 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -173,7 +173,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..6c78ddb 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -219,7 +219,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 5262b18..8c3009a 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -161,7 +161,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fdeb0af..8fd240d 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -372,7 +372,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ - andl $0xfffffff0, %esp subl $4, %esp /* push TSC and BIST to stack */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..c1fe52d 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -37,8 +37,6 @@ movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ - and $0xfffffff0, %esp - /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85..5d7eafa 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -174,7 +174,6 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ - andl $0xfffffff0, %esp sub $8, %esp /* push TSC value to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136 Gerrit-Change-Number: 37368 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned
by Arthur Heymans (Code Review) 05 Jan '21

05 Jan '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37367 ) Change subject: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned ...................................................................... arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned This can be used to avoid aligning the stack at runtime. Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37367/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908..2d1723e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -124,3 +124,4 @@ #if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif +_bogus4 = ASSERT(_ecar_stack == ((_ecar_stack + 0xf) & ~0xf), "_ecar_stack must be 16 aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7 Gerrit-Change-Number: 37367 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [WIP]drivers: Get rid of set_vbe_mode_info_valid
by Patrick Rudolph (Code Review) 04 Jan '21

04 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39006 ) Change subject: [WIP]drivers: Get rid of set_vbe_mode_info_valid ...................................................................... [WIP]drivers: Get rid of set_vbe_mode_info_valid Replace set_vbe_mode_info_valid with fb_new_framebuffer_info_from_edid and migrate to new header, that's independend of VBE. Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/northbridge/intel/i945/gma.c M src/soc/nvidia/tegra124/display.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3399/display.c 12 files changed, 21 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39006/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index fed7754..2fa1a58 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -221,7 +221,7 @@ return ret; } - /* Updated edid for set_vbe_mode_info_valid */ + /* Updated edid for fb_fill_framebuffer_info */ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; diff --git a/src/include/edid.h b/src/include/edid.h index 7c3e9c8..f61a71e 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -109,8 +109,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 6d2f9a6..a2f2b39 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -42,4 +42,7 @@ void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, enum lb_fb_orientation orientation); +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr); + #endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 1928335..d387802 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -139,7 +139,8 @@ /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct edid_fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid, + uintptr_t fb_addr) { struct edid_fb_info *info = fb_new_framebuffer_info(); if (!info) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805..0d50953 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -32,6 +32,7 @@ #include <soc/usb.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> #include "exynos5250.h" @@ -277,7 +278,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); lcd_vdd(); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 57014b4..8b4668e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -173,7 +173,7 @@ return false; } mtk_ddp_mode_set(edid); - struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0); + struct edid_fb_info *info = fb_new_framebuffer_info_from_edid(edid, 0); if (info) fb_fill_framebuffer_set_orientation(info, panel->s->orientation); diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..cc583fe 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -32,6 +32,7 @@ #include <soc/pll.h> #include <soc/usb.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <framebuffer_info.h> enum { CODEC_I2C_BUS = 0, @@ -238,7 +239,7 @@ } mtk_ddp_mode_set(&edid); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2ad..40947e2 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -36,6 +36,7 @@ #include <string.h> #include <symbols.h> #include <vbe.h> +#include <framebuffer_info.h> /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) @@ -416,7 +417,7 @@ sdmmc_vdd(); - set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)fb_addr); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 98e30e7..eff0b9b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -34,6 +34,7 @@ #include <cbmem.h> #include <southbridge/intel/i82801gx/nvs.h> #include <types.h> +#include <framebuffer_info.h> #include "i945.h" #include "chip.h" @@ -386,7 +387,7 @@ (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); - set_vbe_mode_info_valid(&edid, pgfx); + fb_new_framebuffer_info_from_edid(&edid, pgfx); } else { vga_misc_write(0x67); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 6fa3bdf..e4fd183 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -27,6 +27,7 @@ #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> #include <string.h> +#include <framebuffer_info.h> #include "chip.h" @@ -330,5 +331,5 @@ edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, config->framebuffer_bits_per_pixel, 32); - set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..fd85f8f 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -31,6 +31,7 @@ #include <soc/grf.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -138,5 +139,5 @@ break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)lcdbase); } diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..f76fe22 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -32,6 +32,7 @@ #include <soc/mipi.h> #include <soc/soc.h> #include <soc/vop.h> +#include <framebuffer_info.h> #include "chip.h" @@ -174,7 +175,7 @@ break; } mainboard_power_on_backlight(); - set_vbe_mode_info_valid(&edid, (uintptr_t)0); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c145ebcf33ae0e4ff8489d4d0bc1e46869912f3 Gerrit-Change-Number: 39006 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: romcc: cleanup leftovers
by Idwer Vollering (Code Review) 31 Dec '20

31 Dec '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37968 ) Change subject: romcc: cleanup leftovers ...................................................................... romcc: cleanup leftovers Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M .gitignore M util/README.md M util/abuild/abuild.1 M util/lint/check_lint_tests M util/lint/lint-000-license-headers M util/lint/lint-014-qualified-types M util/lint/lint-extended-015-final-newlines M util/lint/lint-stable-010-asm-syntax 8 files changed, 2 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37968/1 diff --git a/.gitignore b/.gitignore index 0cc6ae2..86ddd19 100644 --- a/.gitignore +++ b/.gitignore @@ -115,7 +115,6 @@ util/nvramtool/nvramtool util/optionlist/Options.wiki util/pmh7tool/pmh7tool -util/romcc/build util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios diff --git a/util/README.md b/util/README.md index 55bcaab..66438a9 100644 --- a/util/README.md +++ b/util/README.md @@ -86,8 +86,6 @@ * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` * __rockchip__ - Generate Rockchip idblock bootloader. `Python2` -* __romcc__ - Compile a C source file generating a binary that does not -implicitly use RAM. `C` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1 index 2eee84b..ccdfff6 100644 --- a/util/abuild/abuild.1 +++ b/util/abuild/abuild.1 @@ -78,7 +78,6 @@ .B abuild is covered by the GNU General Public License (GPL), version 2 or later. .SH SEE ALSO -.BR romcc (1), .BR flashrom (1). .SH COPYRIGHT 2004 Stefan Reinauer diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6b1860f..20d49a7 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -35,11 +35,6 @@ sed -i "s/for more details./for more details.\n \* You${SPACE}should${SPACE}have received a copy of the GNU General Public License\n \* along with this program; if not, write to the Free Software\n \* Foundation, Inc./" ${TESTFILE009} git add ${TESTFILE009} -#lint-stable-010-asm-syntax -TESTFILE010=src/arch/x86/bootblock_romcc.S -sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" ${TESTFILE010} -git add ${TESTFILE010} - #lint-stable-012-executable-bit TESTFILE012=src/lib/libgcc.c chmod +x ${TESTFILE012} diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 9b3553b..5adbc7c 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -24,8 +24,6 @@ ^util/amdtools/example_input/|\ ^util/cbfstool/lzma/|\ ^util/kconfig/|\ -^util/romcc/tests|\ -^util/romcc/results|\ Kconfig|\ \<COPYING\>|\ \<LICENSE\>|\ diff --git a/util/lint/lint-014-qualified-types b/util/lint/lint-014-qualified-types index 98679ea..976748f 100755 --- a/util/lint/lint-014-qualified-types +++ b/util/lint/lint-014-qualified-types @@ -17,7 +17,7 @@ LC_ALL=C export LC_ALL INCLUDED_DIRS='^src/\|^util/\|payloads/libpayload\|payloads/coreinfo' -EXCLUDED_DIRS='^src/vendorcode\|^util/romcc\|cbfstool/lzma\|cbfstool/lz4' +EXCLUDED_DIRS='^src/vendorcode\|^util/cbfstool/lzma\|cbfstool/lz4' INCLUDED_FILES='\.[ch]:' # Use git grep if the code is in a git repo, otherwise use grep. diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index b5a503f..15462d6 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -18,7 +18,7 @@ PIDS="" INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc' -EXCLUDED_DIRS='src/vendorcode/\|util/romcc/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' +EXCLUDED_DIRS='src/vendorcode/\|util/cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' EXCLUDED_FILES='\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$' # Use git ls-files if the code is in a git repo, otherwise use find. diff --git a/util/lint/lint-stable-010-asm-syntax b/util/lint/lint-stable-010-asm-syntax index a102a77..e69de29 100755 --- a/util/lint/lint-stable-010-asm-syntax +++ b/util/lint/lint-stable-010-asm-syntax @@ -1,18 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright 2016 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# DESCR: Check that we use a single assembler syntax - -LC_ALL=C export LC_ALL -git grep -n "\.$att\|intel$_syntax\>" | grep -v '\.patch:' -- To view, visit https://review.coreboot.org/c/coreboot/+/37968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8 Gerrit-Change-Number: 37968 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

6 10

Change in ...coreboot[master]: superio/ite: Add and use it8528e
by Patrick Rudolph (Code Review) 26 Dec '20

26 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30957 Change subject: superio/ite: Add and use it8528e ...................................................................... superio/ite: Add and use it8528e * Add SuperIO ITE8528E * Use ITE8528E to configure serial on wedge100s TODO: Add support for accessing EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb M src/superio/ite/Makefile.inc A src/superio/ite/it8528e/Kconfig A src/superio/ite/it8528e/Makefile.inc A src/superio/ite/it8528e/chip.h A src/superio/ite/it8528e/it8528e.h A src/superio/ite/it8528e/superio.c 8 files changed, 226 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30957/1 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index ce9c097..6224340 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO + select SUPERIO_ITE_IT8528E config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index 3d66d0d..fc6dccc 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -11,6 +11,58 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end + chip superio/ite/it8528e + # COM1, routed to COM-e header + device pnp 6e.1 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + # COM2, routed to COM-e header + device pnp 6e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 6e.4 off end + device pnp 6e.5 off end + device pnp 6e.6 off end + device pnp 6e.a off end + device pnp 6e.f off end + device pnp 6e.10 off + io 0x60 = 0x70 + io 0x62 = 0x72 + irq 0x70 = 8 + end + device pnp 6e.11 off + io 0x60 = 0x620 + io 0x62 = 0x660 + irq 0x70 = 1 + end + device pnp 6e.12 off + io 0x60 = 0x680 + io 0x62 = 0x6c0 + irq 0x70 = 1 + end + device pnp 6e.13 off + io 0x60 = 0x300 + irq 0x70 = 2 + end + device pnp 6e.14 off end + device pnp 6e.17 off + io 0x60 = 0x6a0 + io 0x62 = 0x6e0 + irq 0x70 = 1 + end + device pnp 6e.18 off + io 0x60 = 0x740 + io 0x62 = 0x780 + irq 0x70 = 1 + end + device pnp 6e.19 off + io 0x60 = 0x7a0 + io 0x62 = 0x7c0 + irq 0x70 = 1 + end + end #superio/ite/it8528e end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index e73fd71..551abe9 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -20,6 +20,7 @@ ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c +subdirs-y += it8528e subdirs-y += it8623e subdirs-y += it8671f subdirs-y += it8712f diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig new file mode 100644 index 0000000..3815c28 --- /dev/null +++ b/src/superio/ite/it8528e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8528E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc new file mode 100644 index 0000000..def04e5 --- /dev/null +++ b/src/superio/ite/it8528e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c diff --git a/src/superio/ite/it8528e/chip.h b/src/superio/ite/it8528e/chip.h new file mode 100644 index 0000000..ef7e14f --- /dev/null +++ b/src/superio/ite/it8528e/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8528E_CHIP_H +#define SUPERIO_ITE_IT8528E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8528e_config { + // FIXME: Add support for EC +}; + +#endif /* SUPERIO_ITE_IT8528E_CHIP_H */ diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h new file mode 100644 index 0000000..7b19349 --- /dev/null +++ b/src/superio/ite/it8528e/it8528e.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8528E_H +#define SUPERIO_ITE_IT8528E_H + +#define IT8528E_SP1 0x01 /* Com1 */ +#define IT8528E_SP2 0x02 /* Com2 */ +#define IT8528E_SWUC 0x04 /* System Wake-Up */ +#define IT8528E_KBCM 0x05 /* PS/2 mouse */ +#define IT8528E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8528E_IR 0x0a /* Consumer IR */ +#define IT8528E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8528E_RTCT 0x10 /* RTC-like Timer */ +#define IT8528E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8528E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */ +#define IT8528E_PECI 0x14 /* Platform EC Interface */ +#define IT8528E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8528E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8528E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8528E_H */ diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c new file mode 100644 index 0000000..ae2a8e9 --- /dev/null +++ b/src/superio/ite/it8528e/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <arch/io.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "chip.h" +#include "it8528e.h" + +static void it8528e_init(struct device *dev) +{ + // FIXME: Init EC +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8528e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8528E_KBCM, PNP_IRQ0, }, + /* Documentation: Programm io0 = 0x60 and io1 = 0x64 */ + { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Programm io0 = 0x70 and io1 = 0x272 */ + { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + /* Documentation: Programm io0 = 0x62 and io1 = 0x66 */ + { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 , 0x07fc, + 0x07fc, 0xfff0 }, + /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */ + { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8528E_PECI, PNP_IO0 , 0xfff8 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8528e_ops = { + CHIP_NAME("ITE IT8528E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/30957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Gerrit-Change-Number: 30957 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 22

Change in coreboot[master]: drivers/ipmi: Add Supermicro OEM commands
by Patrick Rudolph (Code Review) 25 Dec '20

25 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38002 ) Change subject: drivers/ipmi: Add Supermicro OEM commands ...................................................................... drivers/ipmi: Add Supermicro OEM commands Add a new driver for OEM commands an select if from x11-lga1151-series. The driver communicates the BIOS version and date to the BMC using OEM commands. The command should be supported on all X11 series, but might work with older BMC, too. Tested on X11SSH-TF: The BIOS version strings are updated on boot and are visible in the BMC web UI. Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ipmi_kcs_ops.c A src/drivers/ipmi/ipmi_supermicro_oem.h A src/drivers/ipmi/supermicro_oem.c M src/mainboard/supermicro/x11-lga1151-series/Kconfig 6 files changed, 121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38002/1 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 0f7152d..e098bc8 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -8,3 +8,14 @@ depends on IPMI_KCS help KCS status and command register IO port address spacing + +config DRIVER_SUPERMICRO_IPMI_OEM + bool "Supermicro IPMI OEM BMC support" + depends on IPMI_KCS + default n + help + Tested on X11SSH only. Different BMCs might have different OEM + commands. + The following features are implemented: + * Communicates the BIOS version to the BMC + * Communicates the BIOS date to the BMC diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 9d5b3d4..9fccccf 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c +ramstage-$(CONFIG_DRIVER_SUPERMICRO_IPMI_OEM) += supermicro_oem.c diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 5cb8995..ba8487f 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -34,6 +34,7 @@ #include <delay.h> #include <timer.h> #include "ipmi_kcs.h" +#include "ipmi_supermicro_oem.h" #include "chip.h" /* 4 bit encoding */ @@ -170,6 +171,12 @@ /* Don't write tables if communication failed */ dev->enabled = 0; } + + if (!dev->enabled) + return; + + if (CONFIG(DRIVER_SUPERMICRO_IPMI_OEM)) + supermicro_ipmi_oem(dev->path.pnp.port); } #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/ipmi/ipmi_supermicro_oem.h b/src/drivers/ipmi/ipmi_supermicro_oem.h new file mode 100644 index 0000000..742b97d --- /dev/null +++ b/src/drivers/ipmi/ipmi_supermicro_oem.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IPMI_SUPERMICRO_OEM_H +#define __IPMI_SUPERMICRO_OEM_H + +void supermicro_ipmi_oem(const uint16_t kcs_port); + +#endif /* __IPMI_SUPERMICRO_OEM_H */ diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c new file mode 100644 index 0000000..ea01fef --- /dev/null +++ b/src/drivers/ipmi/supermicro_oem.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <string.h> +#include <build.h> +#include "ipmi_supermicro_oem.h" + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_LUN0_AC_SET_BIOS_VER 0x100 +#define IPMI_LUN0_AC_SET_BIOS_DATE 0x101 +#define IPMI_LUN0_SET_BIOS_STRING 0xac + +struct ipmi_oem_set_bios_str { + uint16_t ver; + char str[16]; // NULL terminated string +} __packed; + +static void set_coreboot_ver(const uint16_t kcs_port) +{ + const char *coreboot_ver = COREBOOT_VERSION; + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + size_t i; + + /* Only 8 charactars are visible in UI. Cut of on first dash */ + for (i = 0; i < 15; i++) { + if (coreboot_ver[i] == '-') + break; + bios_ver.str[i] = coreboot_ver[i]; + } + bios_ver.str[i] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +static void set_coreboot_date(const uint16_t kcs_port) +{ + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + + strncpy(bios_ver.str, COREBOOT_DMI_DATE, 15); + bios_ver.str[15] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +void supermicro_ipmi_oem(const uint16_t kcs_port) +{ + set_coreboot_ver(kcs_port); + set_coreboot_date(kcs_port); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 5a99f7a..53ae398 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -12,6 +12,7 @@ select SUPERIO_ASPEED_AST2400 select GENERATE_SMBIOS_TABLES select IPMI_KCS + select DRIVER_SUPERMICRO_IPMI_OEM select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 -- To view, visit https://review.coreboot.org/c/coreboot/+/38002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Gerrit-Change-Number: 38002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

10 22

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