coreboot-gerrit February 2020

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Change in coreboot[master]: util/kconfig: Uprev to Linux 5.3's kconfig
by Patrick Georgi (Code Review) 13 Jul '21

13 Jul '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37152 ) Change subject: util/kconfig: Uprev to Linux 5.3's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.3's kconfig This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc - one to copy in Linux 5.3's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. TODO: - more commits that bring back our modifications, both directly in the code and as a diff in a patches/ subdirectory. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/kconfig/Makefile M util/kconfig/Makefile.inc D util/kconfig/POTFILES.in D util/kconfig/check.sh M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/expr.h A util/kconfig/gconf-cfg.sh M util/kconfig/gconf.c M util/kconfig/images.c A util/kconfig/images.h D util/kconfig/kxgettext.c A util/kconfig/lexer.l M util/kconfig/list.h M util/kconfig/lkc.h M util/kconfig/lkc_proto.h D util/kconfig/lxdialog/.gitignore M util/kconfig/lxdialog/BIG.FAT.WARNING D util/kconfig/lxdialog/check-lxdialog.sh M util/kconfig/lxdialog/checklist.c M util/kconfig/lxdialog/dialog.h M util/kconfig/lxdialog/inputbox.c M util/kconfig/lxdialog/menubox.c M util/kconfig/lxdialog/textbox.c M util/kconfig/lxdialog/util.c M util/kconfig/lxdialog/yesno.c A util/kconfig/mconf-cfg.sh M util/kconfig/mconf.c M util/kconfig/menu.c A util/kconfig/merge_config.sh A util/kconfig/nconf-cfg.sh M util/kconfig/nconf.c M util/kconfig/nconf.gui.c M util/kconfig/nconf.h R util/kconfig/parser.y A util/kconfig/preprocess.c A util/kconfig/qconf-cfg.sh M util/kconfig/qconf.cc M util/kconfig/qconf.h A util/kconfig/streamline_config.pl M util/kconfig/symbol.c M util/kconfig/util.c D util/kconfig/zconf.gperf D util/kconfig/zconf.hash.c_shipped D util/kconfig/zconf.l D util/kconfig/zconf.lex.c_shipped D util/kconfig/zconf.tab.c_shipped 48 files changed, 4,250 insertions(+), 8,203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37152/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Gerrit-Change-Number: 37152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 46

Change in coreboot[master]: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Inte...
by Lean Sheng Tan (Code Review) 25 Jun '21

25 Jun '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34159 ) Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ...................................................................... mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree. This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialisation, which was not sufficient during FSP initialisation which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree. TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..aa009bb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -593,6 +593,19 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + + /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + + /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + + /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + #endif }; diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9648ac3..40da8eb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 126cab0..6ee52a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "0" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 429d5da..e824ac9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "0" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C/D/F -- To view, visit https://review.coreboot.org/c/coreboot/+/34159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c Gerrit-Change-Number: 34159 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/car: Add support for bootguard CAR
by Arthur Heymans (Code Review) 23 Jun '21

23 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36682 ) Change subject: [WIP]soc/intel/car: Add support for bootguard CAR ...................................................................... [WIP]soc/intel/car: Add support for bootguard CAR Bootguard sets up CAR on its own so the only thing needed is to find a free MTRR for our own CAR region. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36682/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d5f5081..3ae4829 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,11 +23,20 @@ #include <rules.h> #include <intelblocks/msr.h> +#define BOOTGUARD_MSR 0x13a + .global bootblock_pre_c_entry bootblock_pre_c_entry: post_code(0x20) +/* Bootguard setups up it's own CAR and needs separate handling */ +check_boot_guard: + movl $BOOTGUARD_MSR, %ecx + rdmsr + andl $1, %eax + jnz bootguard_car_setup + movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ @@ -456,3 +465,60 @@ jmp car_init_done #endif + +bootguard_car_setup: + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + */ + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +test_is_free_mtrr: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz found_free_mtrr + addl $2, %ecx + dec %ebx + jnz test_is_free_mtrr + + jmp .halt_forever + +found_free_mtrr: + /* Assume one MTRR is enough for now */ + decl %ecx /* MTRR_PHYS_BASE */ + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Configure the MTRR mask for the size region */ + incl %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + decl %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + +clear_cache_region: + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + jmp car_init_done -- To view, visit https://review.coreboot.org/c/coreboot/+/36682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Gerrit-Change-Number: 36682 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

12 62

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to clear CAR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37191 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to clear CAR Add a macro to clear CAR which is replicated 3 times in this code. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d1ae6ca..6a0728d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -48,6 +48,17 @@ 3: .endm + .macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + .endm + + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -256,13 +267,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -353,13 +358,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -462,12 +461,8 @@ xorl %edx, %edx wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car + /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37190 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR This adds a macro to find an available MTRR(s) to set up CAR. This added complexity is not required on bootpaths without bootguard but with bootguard MTRR's have already been set up by the ACM so we need to figure out at runtime which ones are available. Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 43 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85..d1ae6ca 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,6 +23,31 @@ #include <rules.h> #include <intelblocks/msr.h> + /* puts 1 to eax if not found, 0 if found */ + .macro find_free_mtrr + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +1: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz 2f + addl $2, %ecx + dec %ebx + jnz 1b + + movl $1, %eax + jmp 3f +2: + movl $0, %eax + decl %ecx +3: + .endm + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -93,15 +118,19 @@ post_code(0x24) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov $MTRR_PHYS_MASK(0), %ecx + inc %ecx mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax @@ -109,14 +138,18 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr #elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(0), %ecx + incl %ecx mov $(512 * KiB), %eax /* size mask */ dec %eax not %eax @@ -124,13 +157,17 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr - mov $MTRR_PHYS_BASE(1), %ecx + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(1), %ecx + incl %ecx mov $(256 * KiB), %eax /* size mask */ dec %eax not %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/37190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Gerrit-Change-Number: 37190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP, HACK] broadwell: make uart support build again
by Angel Pons (Code Review) 14 Jun '21

14 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37553 ) Change subject: [WIP, HACK] broadwell: make uart support build again ...................................................................... [WIP, HACK] broadwell: make uart support build again @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ @ @ DO NOT MERGE AS-IS! @ @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ I am fully aware this is an atrociously hideous kludge. Moreover, this change won't be properly build-tested by Mr. Jenkins, and it has not been tested on real hardware either. It only exists for backup purposes. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/serialio.c 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..61b62c8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += romstage/uart.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c @@ -16,6 +17,9 @@ bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S +postcar-y += romstage/uart.c +ramstage-y += romstage/uart.c + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b6..43c62a9 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,13 +14,15 @@ */ #include <device/pci_def.h> +#include <console/uart.h> #include <reg_script.h> #include <stdint.h> -#include <uart8250.h> #include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { +const struct reg_script uart_init_script[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ @@ -41,6 +43,11 @@ REG_SCRIPT_END }; +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_TTYS0_BASE; +} + void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ @@ -72,11 +79,11 @@ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + reg_script_run_on_dev(dev, uart_init_script); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + uart_init(0); } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c875..50daa3f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -282,7 +282,8 @@ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - uartmem_setbaseaddr(res->base); + printk(BIOS_ERR, "UART base address changed\n"); + //uartmem_setbaseaddr(res->base); } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/37553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Gerrit-Change-Number: 37553 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: mb/lenovo/x220/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Jun '21

09 Jun '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37297 ) Change subject: mb/lenovo/x220/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 15 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37297/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4..5ae1427 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Gerrit-Change-Number: 37297 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 04 Jun '21

04 Jun '21

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231 Change subject: Add KASAN stubs to coreboot. ...................................................................... Add KASAN stubs to coreboot. Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN. Remove lint errors and warnings from kasan.c. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Changes to be committed: modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 --- M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..96e746e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..3f482e9 --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,29 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); + + +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 Gerrit-Change-Number: 32231 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35645 ) Change subject: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE ...................................................................... vboot: Fix wrong algorithm in TCPA log for BOOT_MODE The hash algorithm for VBOOTs BOOT_MODE is fixed to sha1 but TCPA log uses sha256 as the name for the algorithm. This leads to an log entry with 20 bytes (sha1) while the algorithm is set to sha256 (which needs 32 bytes of hash). Fix it by using the matching algorithm name for BOOT_MODE. Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/tpm_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35645/1 diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 0a211c5..1db7189 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -46,7 +46,7 @@ switch (which_digest) { /* SHA1 of (devmode|recmode|keyblock) bits */ case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size, + return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, TPM_PCR_BOOT_MODE); /* SHA256 of HWID */ case HWID_DIGEST_PCR: -- To view, visit https://review.coreboot.org/c/coreboot/+/35645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Gerrit-Change-Number: 35645 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: src/soc/intel/skylake: Add ucode for SKL/CLX SP
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35761 ) Change subject: src/soc/intel/skylake: Add ucode for SKL/CLX SP ...................................................................... src/soc/intel/skylake: Add ucode for SKL/CLX SP Adds ucode for Family 6 Model 85 Stepping 4,7 CPUs. Corresponds to the latest changes in the intel repository: github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/commit/5ada2f3 Change-Id: I2c63d9944b2b74ffdf7e2753d0a826ce8c1fedec Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Makefile.inc 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35761/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..b86ee88 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -83,7 +83,12 @@ postcar-y += i2c.c postcar-y += uart.c -ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) +ifeq ($(WELISBURG_SOC_PCH_H),y) +# Cascade Lake B1 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-07 +# Skylake H0, M0, U0 && Skylake D M1 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 +else ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 # Kabylake H B0 S0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c63d9944b2b74ffdf7e2753d0a826ce8c1fedec Gerrit-Change-Number: 35761 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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