coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4
by Nico Huber (Code Review) 14 Feb '20

14 Feb '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38817 ) Change subject: mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4 ...................................................................... mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4 SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Thus drop the remaining settings. Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38817 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 3d46fe0..f481c77 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -114,14 +114,8 @@ end device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO - device pnp 2e.b off # SUART3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.c off # SUART4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 device pnp 2e.d on end # iLPC2AHB device pnp 2e.e on # Mailbox io 0x60 = 0xa40 -- To view, visit https://review.coreboot.org/c/coreboot/+/38817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Gerrit-Change-Number: 38817 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add bootblock common stage file
by Usha P (Code Review) 14 Feb '20

14 Feb '20

Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 ) Change subject: soc/intel/common: Add bootblock common stage file ...................................................................... Patch Set 38: (1 comment) https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/base… File src/soc/intel/common/basecode/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/base… PS37, Line 39: bootblock_soc_early_init(void) > Great, then it should really make use of the build-time approach :) Hi Patrick, i have decided to drop the usage of function pointers to reduce the code complexity. So I will re-design the common code implementation accordingly and update.Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/18457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Gerrit-Change-Number: 18457 Gerrit-PatchSet: 38 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Feb 2020 10:42:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/{block, pch}: Move smihandler common functions into ...
by Aamir Bohra (Code Review) 14 Feb '20

14 Feb '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26138 ) Change subject: soc/intel/common/{block, pch}: Move smihandler common functions into common code ...................................................................... Patch Set 38: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/26138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Gerrit-Change-Number: 26138 Gerrit-PatchSet: 38 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Feb 2020 10:31:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/analogix: Remove pixel clock adjustment
by Yu-Ping Wu (Code Review) 14 Feb '20

14 Feb '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38812 ) Change subject: drivers/analogix: Remove pixel clock adjustment ...................................................................... drivers/analogix: Remove pixel clock adjustment Since CB:38400, the phy timing initialization sequence has been corrected. Therefore, remove pixel clock adjustment from the analogix driver. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=Screen did not scroll in recovery UI Change-Id: Iabab79ee5d0c494f80510cd67ff6dff8a638b6ee Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/38812/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 293cc1c..9387a83b 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -273,7 +273,7 @@ return 1; } - *m = (unsigned long long)pixelclock * 599 / 600; + *m = pixelclock; *n = XTAL_FRQ / post_divider; *pd = post_divider; -- To view, visit https://review.coreboot.org/c/coreboot/+/38812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabab79ee5d0c494f80510cd67ff6dff8a638b6ee Gerrit-Change-Number: 38812 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: fix up some includes
by Joel Kitching (Code Review) 14 Feb '20

14 Feb '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38884 ) Change subject: vboot: fix up some includes ...................................................................... vboot: fix up some includes These header files need to make use of vb2_shared_data. Remove the last vestiges of vboot1 in coreboot. BUG=b:124141368, chromium:1038260 TEST=Build locally with CL:2054269 TEST=make clean && make test-abuild BRANCH=none Change-Id: I61b27e33751c11aac9f8af261a75d83b003b5f92 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/misc.h M src/security/vboot/vboot_common.h 2 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/38884/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 2d5b084..324af5c 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -18,9 +18,7 @@ #include <assert.h> #include <security/vboot/vboot_common.h> - -struct vb2_context; -struct vb2_shared_data; +#include <vb2_api.h> /* * Source: security/vboot/common.c diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 976c26a..57f3475 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -17,8 +17,7 @@ #include <commonlib/region.h> #include <stdint.h> -#include <vboot_api.h> -#include <vboot_struct.h> +#include <vb2_api.h> /* * Function to check if there is a request to enter recovery mode. Returns -- To view, visit https://review.coreboot.org/c/coreboot/+/38884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61b27e33751c11aac9f8af261a75d83b003b5f92 Gerrit-Change-Number: 38884 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 13 Feb '20

13 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37975 ) Change subject: mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK ...................................................................... mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I34e84cd0efde37d2df2403928b8127c2f2947139 --- M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig.name M src/mainboard/bap/ode_e20XX/Makefile.inc A src/mainboard/bap/ode_e20XX/bootblock.c D src/mainboard/bap/ode_e20XX/romstage.c 5 files changed, 31 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37975/1 diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72deb..e59147f 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index 54ddcac..a482846 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ODE_E20XX -# bool"ODE_e20xx" +config BOARD_ODE_E20XX + bool "ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 4d8eb8d..8747d2f 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e20XX/bootblock.c b/src/mainboard/bap/ode_e20XX/bootblock.c new file mode 100644 index 0000000..8744547 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c deleted file mode 100644 index 505de38..0000000 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/37975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e84cd0efde37d2df2403928b8127c2f2947139 Gerrit-Change-Number: 37975 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 13 Feb '20

13 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37869 ) Change subject: gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK ...................................................................... gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK Following the examples of change CB:37719 (fc749b2) and CB:37829. Warning: Not tested on hardware, please test if you have this board. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2142f28300a7ebc36ec5a72c99bdd270283f4a45 --- M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/Kconfig.name M src/mainboard/gizmosphere/gizmo2/Makefile.inc A src/mainboard/gizmosphere/gizmo2/bootblock.c D src/mainboard/gizmosphere/gizmo2/romstage.c 5 files changed, 35 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37869/1 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 685e271..47a39b6 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_GIZMOSPHERE_GIZMO2 - def_bool n - if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name index 29688e2..a3bae57 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_GIZMOSPHERE_GIZMO2 -# bool"Gizmo2" +config BOARD_GIZMOSPHERE_GIZMO2 + bool "Gizmo2" diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 8a24bea..2a7d26b 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c new file mode 100644 index 0000000..312b5cc --- /dev/null +++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> + +void bootblock_mainboard_early_init(void) +{ +#if 0 + volatile u32 i, val; + + /* LPC clock? Should happen before enable_serial. */ + + /* + * On Larne, after LpcClkDrvSth is set, it needs some time to be stable, + * because of the buffer ICS551M + */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +#endif +} diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c deleted file mode 100644 index 4676199..0000000 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); -} - -#if 0 - /* LPC clock? Should happen before enable_serial. */ - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); -#endif - -#if 0 - /* Was before copy_and_run. */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2142f28300a7ebc36ec5a72c99bdd270283f4a45 Gerrit-Change-Number: 37869 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 13 Feb '20

13 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37978 ) Change subject: mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK ...................................................................... mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I3d504397f0ade672a8cac3f072edc9e2435e3b4b --- M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/Kconfig.name M src/mainboard/amd/olivehill/Makefile.inc A src/mainboard/amd/olivehill/bootblock.c D src/mainboard/amd/olivehill/romstage.c 5 files changed, 34 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37978/1 diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f..477511f 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index d065472..fd1a713 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_OLIVEHILL -# bool"Olive Hill" +config BOARD_AMD_OLIVEHILL + bool "Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c new file mode 100644 index 0000000..50cd75f --- /dev/null +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +void bootblock_mainboard_early_init(void) +{ + int i; + u32 val; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +} diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c deleted file mode 100644 index 122bb19..0000000 --- a/src/mainboard/amd/olivehill/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - int i; - u32 val; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - val = inb(0xcd6); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/37978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d504397f0ade672a8cac3f072edc9e2435e3b4b Gerrit-Change-Number: 37978 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 13 Feb '20

13 Feb '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37977 ) Change subject: src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK ...................................................................... src/mb/hp/abm: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5464b4ce07643b83f9d948858d3a773edb817aaf --- M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/Kconfig.name M src/mainboard/hp/abm/Makefile.inc A src/mainboard/hp/abm/bootblock.c D src/mainboard/hp/abm/romstage.c 5 files changed, 49 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37977/1 diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 907c025..94cb4e1 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 27eda0c..4ace573 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_HP_ABM -# bool"ABM" +config BOARD_HP_ABM + bool "ABM" diff --git a/src/mainboard/hp/abm/Makefile.inc b/src/mainboard/hp/abm/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/hp/abm/Makefile.inc +++ b/src/mainboard/hp/abm/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/hp/abm/bootblock.c b/src/mainboard/hp/abm/bootblock.c new file mode 100644 index 0000000..f2771a2 --- /dev/null +++ b/src/mainboard/hp/abm/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) + +void bootblock_mainboard_early_init(void) +{ + u32 *addr32; + u32 t32; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + addr32 = (u32 *)0xfed80e28; + t32 = *addr32; + t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + t32 |= 0x00010000; // Set bit 16 for 25MHz + *addr32 = t32; + + /* Enable Auxiliary OSCOUT1/OSCOUT2 */ + addr32 = (u32 *)0xfed80e40; + t32 = *addr32; + t32 &= 0xffffff7b; // clear 2, 7 + *addr32 = t32; + + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c deleted file mode 100644 index d7322c9..0000000 --- a/src/mainboard/hp/abm/romstage.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> - -#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 *addr32; - u32 t32; - - /* For serial port option, plug-in card on LPC. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x01, 0xcd7); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ - /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - addr32 = (u32 *)0xfed80e28; - t32 = *addr32; - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz - *addr32 = t32; - - /* Enable Auxiliary OSCOUT1/OSCOUT2 */ - addr32 = (u32 *)0xfed80e40; - t32 = *addr32; - t32 &= 0xffffff7b; // clear 2, 7 - *addr32 = t32; - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -#if 0 - /* Was before copy_and_run. */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5464b4ce07643b83f9d948858d3a773edb817aaf Gerrit-Change-Number: 37977 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/intel/common/block: Move cse common functions into block/cse
by V Sowmya (Code Review) 13 Feb '20

13 Feb '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26133 ) Change subject: soc/intel/common/block: Move cse common functions into block/cse ...................................................................... Patch Set 37: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/26133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Gerrit-Change-Number: 26133 Gerrit-PatchSet: 37 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Feb 2020 10:52:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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