coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1796 discussions

Change in coreboot[master]: cpu: Add microcode at pre-defined address
by Angel Pons (Code Review) 15 Feb '20

15 Feb '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Add microcode at pre-defined address ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@20 PS6, Line 20: TP That's Tioga Pass, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 6 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Feb 2020 15:50:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu: Add microcode at pre-defined address
by Arthur Heymans (Code Review) 15 Feb '20

15 Feb '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 ) Change subject: cpu: Add microcode at pre-defined address ...................................................................... Patch Set 6: (2 comments) It'd be nice if the native coreboot code for microcode updates was tried over re-introducing blobs at fixed locations. https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c Coreboot has native assembly code to update microcode by parsing cbfs, removing the need for microcode at a fixed location. See cpu/intel/microcode/microcode_asm.S. https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@13 PS6, Line 13: : Also, on current version of FSP-T on Xeons microcode is not optional. This was also observed on some older FSP1.1 versions, possibly for the same reason. https://blog.aheymans.xyz/fsp1-1-braswell-tempraminit-problems/ Might prove insightful. Doing updates in coreboot and providing 'fake' microcode to FSP-T might also work for your use case as it did for FSP1.1 (see drivers/intel/fsp1_1/cache_as_ram.S) -- To view, visit https://review.coreboot.org/c/coreboot/+/38640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Gerrit-Change-Number: 38640 Gerrit-PatchSet: 6 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 15 Feb 2020 14:22:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib/edid.c: Remove trailing space from detailed mode output
by HAOUAS Elyes (Code Review) 15 Feb '20

15 Feb '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17644 ) Change subject: lib/edid.c: Remove trailing space from detailed mode output ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/17644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Gerrit-Change-Number: 17644 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 15 Feb 2020 12:04:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib/edid.c: Remove trailing space from detailed mode output
by Paul Menzel (Code Review) 15 Feb '20

15 Feb '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/17644 to look at the new patch set (#2). Change subject: lib/edid.c: Remove trailing space from detailed mode output ...................................................................... lib/edid.c: Remove trailing space from detailed mode output When the bit for interlaced mode is not set, a trailing space is added to the end. As the space is already accounted for in `" interlaced"`, remove that space. TEST=Boot on Lenovo X60t, and verify the trailing space in the detailed mode is gone. Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/lib/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/17644/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/17644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Gerrit-Change-Number: 17644 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: lib/edid.c: Remove trailing space from detailed mode output
by Paul Menzel (Code Review) 15 Feb '20

15 Feb '20

Paul Menzel has restored this change. ( https://review.coreboot.org/c/coreboot/+/17644 ) Change subject: lib/edid.c: Remove trailing space from detailed mode output ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/17644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Gerrit-Change-Number: 17644 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

1 0

Change in coreboot[master]: mb/intel/jasperlake_rvp: Update devicetree to enable only required PC...
by Usha P (Code Review) 15 Feb '20

15 Feb '20

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38679 ) Change subject: mb/intel/jasperlake_rvp: Update devicetree to enable only required PCIE root ports ...................................................................... mb/intel/jasperlake_rvp: Update devicetree to enable only required PCIE root ports This patch updates the devicetree to enable WLAN and NVME for JSL and remove the other root port configurations which are not required. Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 14 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38679/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 854df46..4b35e2a 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -48,56 +48,23 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" + # PCIe port 1 for M.2 E-key WLAN + register "PcieRpEnable[1]" = "1" + + # RP 1 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "0x01" + + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "0x01" + + # Enable Root Port 4(x4) for NVMe register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" + # RP 4 uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "0x04" - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" + # ClkReq-to-ClkSrc mapping for CLK SRC 0 + register "PcieClkSrcClkReq[0]" = "0x00" register "SataEnable" = "1" register "SataSalpSupport" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Gerrit-Change-Number: 38679 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

6 17

Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig related to JSL
by Usha P (Code Review) 15 Feb '20

15 Feb '20

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38678 ) Change subject: soc/intel/tigerlake: Update Kconfig related to JSL ...................................................................... soc/intel/tigerlake: Update Kconfig related to JSL Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38678/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..070fc89 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,7 @@ config SOC_INTEL_JASPERLAKE bool select SOC_INTEL_TIGERLAKE_BASE - select INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM help Intel Jasperlake support @@ -113,13 +113,13 @@ config MAX_ROOT_PORTS int - default 16 if SOC_INTEL_JASPERLAKE + default 8 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE config MAX_PCIE_CLOCKS int default 7 if SOC_INTEL_TIGERLAKE - default 16 if SOC_INTEL_JASPERLAKE + default 5 if SOC_INTEL_JASPERLAKE config SMM_TSEG_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/38678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Gerrit-Change-Number: 38678 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Ravi kumar (Code Review) 15 Feb '20

15 Feb '20

Ravi kumar has uploaded a new patch set (#38) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... sc7180: Add QUPv3 FW load & config UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h A src/soc/qualcomm/sc7180/qcom_qup_se.c A src/soc/qualcomm/sc7180/qupv3_config.c 7 files changed, 1,064 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 38 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sc7180: Add UART support
by Ravi kumar (Code Review) 15 Feb '20

15 Feb '20

Ravi kumar has uploaded a new patch set (#38) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... sc7180: Add UART support This implements the UART driver in SoC Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25373/78 Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/qupv3_uart.c 3 files changed, 182 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35500/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 38 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/tigerlake: Update ACPI files for JSP
by Meera Ravindranath (Code Review) 15 Feb '20

15 Feb '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38880 ) Change subject: soc/tigerlake: Update ACPI files for JSP ...................................................................... soc/tigerlake: Update ACPI files for JSP ACPI files for xhci in JSL is different from TGL. Hence, renaming xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL. Also, allowing xhci.asl to choose the correct file based on the SoC selected. BUG=None BRANCH=None TEST=Compilation for JasperLake board is working Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/acpi/xhci.asl A src/soc/intel/tigerlake/acpi/xhci_jsl.asl A src/soc/intel/tigerlake/acpi/xhci_tgl.asl 3 files changed, 132 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38880/1 diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index 312cc5a..9618cf3 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,51 +13,8 @@ * GNU General Public License for more details. */ -#include <soc/gpe.h> - -/* XHCI Controller 0:14.0 */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - - Name (_PRW, Package () { GPE0_PME_B0, 3 }) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Method (_PS0, 0, Serialized) - { - - } - - Method (_PS3, 0, Serialized) - { - - } - - /* Root Hub for Tigerlake-LP PCH */ - Device (RHUB) - { - Name (_ADR, Zero) - - /* USB2 */ - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - Device (HS09) { Name (_ADR, 9) } - Device (HS10) { Name (_ADR, 10) } - - /* USB3 */ - Device (SS01) { Name (_ADR, 13) } - Device (SS02) { Name (_ADR, 14) } - Device (SS03) { Name (_ADR, 15) } - Device (SS04) { Name (_ADR, 16) } - } -} +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "xhci_tgl.asl" +#else + #include "xhci_jsl.asl" +#endif diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl new file mode 100644 index 0000000..fe17b0d --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Jasperlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl new file mode 100644 index 0000000..312cc5a --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Gerrit-Change-Number: 38880 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

4 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020