coreboot-gerrit December 2020

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Change in coreboot[master]: sb/amd/agesa/hudson: Use common FCH HDA setup code
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46639 ) Change subject: sb/amd/agesa/hudson: Use common FCH HDA setup code ...................................................................... sb/amd/agesa/hudson: Use common FCH HDA setup code Let’s configure Azalia ourselves instead of AGESA, and use the common AMD code, where `hda.c` is basically the same. The FCH hasn’t changed in this regard, so the code can be easily used. Note, the board change, will be split out. For whatever reason, the ACPI device AZHD is not created (at least I do not see it in the disassembled SSDT). Change-Id: I368947e578a8c4c97af190103ffb42adb1f8d4e6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/Kconfig A src/mainboard/asus/f2a85-m/hda_verb.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc D src/southbridge/amd/agesa/hudson/hda.c 5 files changed, 35 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46639/1 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 27d5517..7d475c2 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -17,6 +17,7 @@ select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA + select AZALIA_PLUGIN_SUPPORT choice prompt "DDR3 memory voltage" diff --git a/src/mainboard/asus/f2a85-m/hda_verb.c b/src/mainboard/asus/f2a85-m/hda_verb.c new file mode 100644 index 0000000..0fec04e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC701 on mainboard */ + 0x10ec0892, + + AZALIA_SUBVENDOR(0, 0x10438444), // HDA Codec Subsystem ID: Subsystem: + // ASUSTeK Computer Inc. FCH Azalia Controller + + AZALIA_RESET(1), // Widget node 0x01 : + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0xff, 0xffffffff) +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e61bc85..24ddc26 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -17,6 +17,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_HDA config EHCI_BAR hex diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b8eb5b9..de9afba 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -9,7 +9,6 @@ ramstage-y += sm.c ramstage-y += ide.c ramstage-y += sata.c -ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c deleted file mode 100644 index a15b045..0000000 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#include "hudson.h" - -static void hda_init(struct device *dev) -{ -} - -static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = hda_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_HDA, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368947e578a8c4c97af190103ffb42adb1f8d4e6 Gerrit-Change-Number: 46639 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Add support for calling microcode update API
by Sugnan Prabhu S (Code Review) 07 Aug '23

07 Aug '23

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46844 ) Change subject: soc/intel/jasperlake: Add support for calling microcode update API ...................................................................... soc/intel/jasperlake: Add support for calling microcode update API This adds the entry function to call the main microcode update interface to enable microcode update for Jasperlake SoC and also implements the reboot function required. BUG=b:149547271 TEST=Build and boot JSLRVP to OS Change-Id: I49dec0f764f74fbd8caa0e15a932dcc4d4b90aaa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/ucode_update.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46844/1 diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..d32bf86 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += systemagent.c ramstage-y += sd.c ramstage-y += me.c +ramstage-$(CONFIG_INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE) += ucode_update.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/jasperlake/ucode_update.c b/src/soc/intel/jasperlake/ucode_update.c new file mode 100644 index 0000000..cfe894b --- /dev/null +++ b/src/soc/intel/jasperlake/ucode_update.c @@ -0,0 +1,50 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> +#include <console/console.h> +#include <halt.h> +#include <intelbasecode/ucode_update.h> +#include <reset.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> +#include <soc/intel/common/reset.h> +#include <vb2_api.h> + +static void update_ucode(void *unused) +{ + struct vb2_context *ctx; + + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) { + if (update_ucode_and_topswap_state()) { + /* Update failed */ + if (CONFIG(VBOOT)) { + printk(BIOS_DEBUG, "ucode: Failed to update microcode\n"); + ctx = vboot_get_context(); + if (ctx == NULL) + die("ucode: Failed to trigger recovery mode\n"); + vb2api_fail(ctx, 0x36, 0x0); + vboot_save_data(ctx); + vboot_reboot(); + } + } + } +} + +void ucode_update_reboot(void) +{ + if (CONFIG(VBOOT)) + vboot_reboot(); + else + do_board_reset(); + + die("ucode: Failed to reset the system\n"); + halt(); +} + +int ucode_update_rec_mode_enabled(void) +{ + return vboot_recovery_mode_enabled(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, update_ucode, NULL); + -- To view, visit https://review.coreboot.org/c/coreboot/+/46844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49dec0f764f74fbd8caa0e15a932dcc4d4b90aaa Gerrit-Change-Number: 46844 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Add code to configure who decodes IO 0x80
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47164 ) Change subject: sb/intel/common: Add code to configure who decodes IO 0x80 ...................................................................... sb/intel/common: Add code to configure who decodes IO 0x80 Change-Id: Ieb973c369c0061867320c255df5ae85fb5101276 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/post.c A src/southbridge/intel/common/post.h 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47164/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25..74f0252 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -105,3 +105,6 @@ hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS default 0x400 + +config SOUTHBRIDGE_INTEL_COMMON_POST + def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1ededd2..50dda9b 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -3,6 +3,8 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_POST) += post.c + all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c diff --git a/src/southbridge/intel/common/post.c b/src/southbridge/intel/common/post.c new file mode 100644 index 0000000..96155d1 --- /dev/null +++ b/src/southbridge/intel/common/post.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> + +#include "rcba.h" + +#define GCS 0x3410 +#define RPR (1 << 2) + +void configure_port80(void) +{ + if (CONFIG(POST_DEVICE_LPC)) + RCBA32_AND_OR(GCS, ~RPR, 0); + else if (CONFIG(POST_DEVICE_PCI_PCIE)) + RCBA32_AND_OR(GCS, RPR, RPR); +} diff --git a/src/southbridge/intel/common/post.h b/src/southbridge/intel/common/post.h new file mode 100644 index 0000000..f64fce5 --- /dev/null +++ b/src/southbridge/intel/common/post.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_POST_H +#define SOUTHBRIDGE_INTEL_COMMON_POST_H + +/* Configure where IO port 0x80 writes (POST) get forwarded (PCI/LPC). + * Note that port 0x90 writes which aliases port 0x80 always get forwarded + * to LPC. + */ +void configure_port80(void); + +#endif + -- To view, visit https://review.coreboot.org/c/coreboot/+/47164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb973c369c0061867320c255df5ae85fb5101276 Gerrit-Change-Number: 47164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33107 Change subject: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 ...................................................................... [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 BOOT_MEDIA_PARAMS2 exposes the boot media MMIO address if it's memory mapped in addition to various regions inside the bootmedia. That information can be used by payloads to: * Support VBOOT on SeaBIOS, as it otherwise uses the RO CBFS only * Support Intel Apollolake and platforms that don't map the end of the BIOS region to the end of the address space * Support fwupd and flashrom finding the FMAP in memory Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 2 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33107/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 198ad27..a854e44 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -392,6 +392,81 @@ struct mac_address mac_addrs[0]; }; +/** + * coreboot boot media params2 + * + * The coreboot 'boot media params2' contain information about the + * bootmedia layout, allowing a payload to read the boot media + * without the need to parse (platform specific) layout files. + * + * It extends 'boot media params' by MMIO addresses and a second CBFS + * pointer. + * + * If the boot media is memory mapped, as it's usually done on x86 platforms, + * the FMAP and CBFS can be easily accessed by any software without the need + * for platform specific drivers. + * + * If the boot media is not memory mapped, the `mmap_mmio_address` is set + * to ~0ULL. In that case the software must use platform specific drivers + * to access the boot media (like flashrom or Linux's MTD). + * + * The memory mapped area is `mmap_size` bytes in size, starting `mmap_offset` + * bytes from `mmap_mmio_address`. + * The memory mapped area might be smaller than `boot_media_size` bytes, + * which gives the total size in bytes as seen by an external programmer. + * + * Software utilizing the coreboot boot media params2 shall check if the + * region to be access falls completely within the memory mapped region, + * before trying to access them. + * In addition it should not assume that the whole boot media is memory mapped. + * + * Example on Intel Apollolake: + * + * physical memory boot media + * +-----------+ + * | | + * | | + * +-----------+ MMAP MMIO address +-----------------+ -------- + * | ~UNAVAIL~ | | | IFD | | | | | + * | | MMAP offset | | | | | | + * | | | | | | | | | + * +-----------+ --- <<< +-----------------+ | | | | + * | BIOS REG | | | BIOS | | | | | + * | | | | | | | | | + * | | | |+---------------+| --+-+-+-+CBFS offset + * | | | || CBFS Active || | | | + * | | MMAP size |+---------------+| --+-+-+FMAP offset + * | | | || FMAP || | | + * | | | |+---------------+| --+-+CBFS legacy offset + * | | | || COREBOOT(CBFS)|| | + * +-----------+ --- <<< |+---------------+| | + * | TXE SRAM | || BIOS UNUSABLE || | + * | | |+---------------+| | + * +-----------+ +-----------------+ | + * |DEVICE EXTENSION | | + * | | | + * +-----------------+ -+Boot media size + */ + +#define LB_TAG_BOOT_MEDIA_PARAMS2 0x0036 +struct lb_boot_media_params2 { + uint32_t tag; + uint32_t size; + /* offsets are relative to start of boot media */ + uint64_t fmap_offset; + uint64_t cbfs_offset; + uint64_t cbfs_legacy_offset; + uint64_t mmap_offset; + /* Size is in bytes */ + uint64_t cbfs_size; + uint64_t fmap_size; + uint64_t boot_media_size; + uint64_t cbfs_legacy_size; + uint64_t mmap_size; + /* MMIO address of MMAPed boot media, ~0ULL if not MMAPed.*/ + uint64_t mmap_mmio_address; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d..c5807fd 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -261,8 +261,10 @@ static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; + struct lb_boot_media_params2 *bmp2; struct cbfs_props props; const struct region_device *boot_dev; + struct region ar; struct region_device fmrd; boot_device_init(); @@ -285,6 +287,47 @@ bmp->fmap_offset = ~(uint64_t)0; if (find_fmap_directory(&fmrd) == 0) bmp->fmap_offset = region_device_offset(&fmrd); + + /* LB_TAG_BOOT_MEDIA_PARAMS2 exposes additional parameters: + * - MMAPed boot media address + * - legacy CBFS position (RO partition in case of VBOOT) + */ + bmp2 = (struct lb_boot_media_params2 *)lb_new_record(header); + bmp2->tag = LB_TAG_BOOT_MEDIA_PARAMS2; + bmp2->size = sizeof(*bmp2); + + bmp2->cbfs_offset = bmp->cbfs_offset; + bmp2->cbfs_size = bmp->cbfs_size; + bmp2->boot_media_size = bmp->boot_media_size; + bmp2->fmap_offset = bmp->fmap_offset; + + if (find_fmap_directory(&fmrd) == 0) + bmp2->fmap_size = region_device_size(&fmrd); + + if (fmap_locate_area("COREBOOT", &ar)) { + printk(BIOS_INFO, "Can't find 'COREBOOT' area in FMAP\n"); + bmp2->cbfs_legacy_offset = ~(uint64_t)0; + bmp2->cbfs_legacy_size = 0; + } else { + bmp2->cbfs_legacy_offset = ar.offset; + bmp2->cbfs_legacy_size = ar.size; + } + + if (CONFIG(COMMON_CBFS_SPI_WRAPPER)) { + /* rdev_mmap will return a pointer to _postram_cbfs_cache */ + bmp2->mmap_offset = ~(uint64_t)0; + bmp2->mmap_size = 0; + bmp2->mmap_mmio_address = ~(uint64_t)0; + } else { + /* FIXME: Introduce API to set correct values here */ + bmp2->mmap_offset = 0; + bmp2->mmap_size = bmp2->boot_media_size; + /* Get address to MMAP boot media */ + uintptr_t off = (uintptr_t)rdev_mmap(boot_dev, 0, + bmp2->mmap_size); + bmp2->mmap_mmio_address = off; + rdev_munmap(boot_dev, (void *)off); + } } static void lb_ram_code(struct lb_header *header) -- To view, visit https://review.coreboot.org/c/coreboot/+/33107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Gerrit-Change-Number: 33107 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86: Prevent Kconfig errors resulting in a brick
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34709 ) Change subject: x86: Prevent Kconfig errors resulting in a brick ...................................................................... x86: Prevent Kconfig errors resulting in a brick Always select USE_LEGACY_8254_TIMER if we know we have to. Fixes boot failure (Linux kernel/GRUB2 hangs with no console output) on X11SSH-TF using SeaBIOS as payload. Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/GRUB2/Kconfig.name M payloads/external/SeaBIOS/Kconfig.name M src/device/Kconfig M src/soc/intel/common/block/timer/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34709/1 diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name index fe60d76..40629ad 100644 --- a/payloads/external/GRUB2/Kconfig.name +++ b/payloads/external/GRUB2/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_GRUB2 bool "GRUB2" depends on ARCH_X86 || ARCH_ARM + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name index bb1f30c..8f92997 100644 --- a/payloads/external/SeaBIOS/Kconfig.name +++ b/payloads/external/SeaBIOS/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_SEABIOS bool "SeaBIOS" depends on ARCH_X86 + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..ebf6bfb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -86,6 +86,7 @@ bool "Run VGA Option ROMs" depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef0..66bf9cf 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,7 +5,6 @@ config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN default n help This sets the FSP UPD to enable Legacy 8254 clock gating. As per -- To view, visit https://review.coreboot.org/c/coreboot/+/34709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Gerrit-Change-Number: 34709 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Add AHCI code
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37137 ) Change subject: sb/intel/common: Add AHCI code ...................................................................... sb/intel/common: Add AHCI code Implement a clean implementation based on AHCI spec 1.0-1.3 and the Intel ICH/PCH datasheets. The common implementation should combine all features of the duplicated code present in the various southbridge implementations. It compiles on x86_64, uses less magic values and detects the AHCI version at runtime. Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/include/ahci.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/ahci.c A src/southbridge/intel/common/ahci.h 5 files changed, 252 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37137/1 diff --git a/src/include/ahci.h b/src/include/ahci.h new file mode 100644 index 0000000..e7818fb --- /dev/null +++ b/src/include/ahci.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AHCI_H__ +#define __AHCI_H__ + +/* Serial ATA AHCI 1.3.1 Specification */ + +#define AHCI_CAP 0x00 +#define AHCI_CAP_NP 0x1f +#define AHCI_CAP_PSC (1u << 13) +#define AHCI_CAP_SSC (1u << 14) +#define AHCI_CAP_PMD (1u << 15) +#define AHCI_CAP_SPM (1u << 17) +#define AHCI_CAP_SAM (1u << 18) +#define AHCI_CAP_SNZO (1u << 19) +#define AHCI_CAP_ISS(x) ((x) << 20) +#define AHCI_CAP_SCLO (1u << 24) +#define AHCI_CAP_SAL (1u << 25) +#define AHCI_CAP_SALP (1u << 26) +#define AHCI_CAP_SSS (1u << 27) +#define AHCI_CAP_SIS (1u << 28) +#define AHCI_CAP_SNCQ (1u << 30) +#define AHCI_CAP_S64A (1u << 31) +/* Added in AHCI 1.1 */ +#define AHCI_CAP_SXS (1u << 5) +#define AHCI_CAP_EMS (1u << 6) +#define AHCI_CAP_CCCS (1u << 7) +/* Added in AHCI 1.2 */ +#define AHCI_CAP_SSNTF (1u << 29) + +#define AHCI_GHC 0x04 +#define AHCI_GHC_AE (1u << 31) +#define AHCI_PI 0x0c +#define AHCI_VS 0x10 +#define AHCI_VS_MAJOR(x) ((x >> 16) & 0xf) +#define AHCI_VS_MINOR(x) ((x >> 8) & 0xf) + +/* Added in AHCI 1.1 */ +#define AHCI_CCC_CTL 0x14 +#define AHCI_CCC_PORTS 0x18 +#define AHCI_EM_LOC 0x1c +#define AHCI_EM_CTL 0x20 +/* Added in AHCI 1.2 */ +#define AHCI_CAP2 0x24 +#define AHCI_CAP2_BOH (1u << 0) +/* Added in AHCI 1.3 */ +#define AHCI_CAP2_NVMP (1u << 1) +#define AHCI_CAP2_APST (1u << 2) +#define AHCI_CAP2_SDS (1u << 3) +#define AHCI_CAP2_SADM (1u << 4) +#define AHCI_CAP2_DESO (1u << 5) + +#define AHCI_BOHC 0x28 + +#define AHCI_VENDOR 0xa0 +#define AHCI_PORT 0x100 +#define AHCI_PORT_PxCMD 0x18 +#define AHCI_PORT_LEN 0x80 + + +#endif diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e..376f077 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -2,6 +2,10 @@ def_bool n select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_AHCI + def_bool n + depends on PCI + config SOUTHBRIDGE_INTEL_COMMON_RTC def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c8521e1..e87ae82 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -18,6 +18,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_AHCI) += ahci.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/ahci.c b/src/southbridge/intel/common/ahci.c new file mode 100644 index 0000000..ca20d30 --- /dev/null +++ b/src/southbridge/intel/common/ahci.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ahci.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> + +#include "ahci.h" + +/** + * Initialize the AHCI config space. + * @param port_map The ports to enable + * @param sam Set SAM bit (no legacy device support) + * @param cccs Set CCCS bit + * @param iss Limit the controller to sata gen x + * @param devslp Enable DEVSLP feature if supported + * @param clear_vnd Clear bits in vendor config space + */ +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd) +{ + u32 reg32; + u8 major, minor; + struct resource *res; + u8 *abar; + unsigned int ports; + + /* Initialize AHCI memory-mapped space */ + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + abar = res2mmio(res, 0, 0); + /* + * Set AHCI access mode. + * Spec: "No other ABAR registers should be accessed before this." + */ + reg32 = read32(abar + AHCI_GHC); + if (!(reg32 & AHCI_GHC_AE)) { + reg32 |= AHCI_GHC_AE; + write32(abar + AHCI_GHC, reg32); + } + + /* Get AHCI version */ + reg32 = read32(abar + AHCI_VS); + major = AHCI_VS_MAJOR(reg32); + minor = AHCI_VS_MINOR(reg32); + printk(BIOS_DEBUG, "AHCI: implements AHCI %d.%d\n", major, minor); + + reg32 = read32(abar + AHCI_CAP); + printk(BIOS_DEBUG, "AHCI: supports SATA Gen%d\n", (reg32 >> 20) & 0xf); + + ports = reg32 & AHCI_CAP_NP; + printk(BIOS_DEBUG, "AHCI: supports up to %d ports\n", ports); + + /* CAP (HBA Capabilities) : enable power management */ + /* Program Write-Once bits (this isn't part of the AHCI spec, but PCH). */ + if (sam) + reg32 |= AHCI_CAP_SAM; + if (cccs && major >= 1 && minor >= 1) + reg32 |= AHCI_CAP_CCCS; + if (iss) { + u8 max_iss; + if (major >= 1 && minor >= 2) + max_iss = MIN(iss, 3); + else + max_iss = MIN(iss, 2); + reg32 &= ~AHCI_CAP_ISS(0xf); + reg32 |= AHCI_CAP_ISS(max_iss); + printk(BIOS_DEBUG, "AHCI: limited to Gen%d\n", max_iss); + } + reg32 |= AHCI_CAP_PSC; + reg32 |= AHCI_CAP_SSC; + reg32 |= AHCI_CAP_SALP; + reg32 |= AHCI_CAP_SSS; + if (major >= 1 && minor >= 1) { + reg32 &= ~AHCI_CAP_SXS; + reg32 &= ~AHCI_CAP_EMS; + reg32 &= ~AHCI_CAP_SPM; + } + write32(abar + AHCI_CAP, reg32); + + if (major >= 1 && minor >= 2) { + reg32 = read32(abar + AHCI_CAP2); + /* Clear BIOS handoff support */ + reg32 &= ~AHCI_CAP2_BOH; + if (major >= 1 && minor >= 3) { + /* Configure DEVSLP support */ + if (devslp) { + reg32 |= AHCI_CAP2_APST; + reg32 |= AHCI_CAP2_SDS; + reg32 |= AHCI_CAP2_SADM; + reg32 |= AHCI_CAP2_DESO; + } else { + reg32 &= ~AHCI_CAP2_SDS; + } + /* Disable NVMHCI */ + reg32 &= ~AHCI_CAP2_NVMP; + } + write32(abar + AHCI_CAP2, reg32); + } + + if (port_map & ~((1 << ports) - 1)) + printk(BIOS_ERR, "AHCI: Invalid port map given!\n"); + + write32(abar + AHCI_PI, port_map & ((1 << ports) - 1)); + /* PCH code reads back twice, do we need it, too? */ + (void) read32(abar + AHCI_PI); /* Read back 1 */ + (void) read32(abar + AHCI_PI); /* Read back 2 */ + + /* Clear vendor specific bits */ + reg32 = read32(abar + AHCI_VENDOR); + reg32 &= ~clear_vnd; + write32(abar + AHCI_VENDOR, reg32); + + /* Lock R/WO bits in Port command registers. */ + for (size_t i = 0; i < ports; ++i) { + if (!((1 << i) & port_map)) + continue; + u8 *addr = abar + AHCI_PORT + (i * AHCI_PORT_LEN); + write32(addr, read32(addr + AHCI_PORT_PxCMD)); + } +} diff --git a/src/southbridge/intel/common/ahci.h b/src/southbridge/intel/common/ahci.h new file mode 100644 index 0000000..9d4a025 --- /dev/null +++ b/src/southbridge/intel/common/ahci.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_AHCI_H +#define SOUTHBRIDGE_INTEL_COMMON_AHCI_H + +#include <device/device.h> + +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_AHCI_H */ + -- To view, visit https://review.coreboot.org/c/coreboot/+/37137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Gerrit-Change-Number: 37137 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 13

Change in coreboot[master]: mb/google/zork/vilboz: enable LTE function
by Peichao Li (Code Review) 07 Aug '23

07 Aug '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43663 ) Change subject: mb/google/zork/vilboz: enable LTE function ...................................................................... mb/google/zork/vilboz: enable LTE function BUG=b:161736991 TEST=flash the BIOS and insure LTE function work properly Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e --- M src/mainboard/google/zork/variants/vilboz/Makefile.inc A src/mainboard/google/zork/variants/vilboz/gpio.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43663/1 diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index dc1e411..51d19fe 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += ./spd +ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c new file mode 100644 index 0000000..4d292c2 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct soc_amd_gpio lte_gpio_set_stage_ram[] = { + /* LTE POWER ENABLE */ + PAD_GPO(GPIO_32, HIGH), +}; + + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(lte_gpio_set_stage_ram); + return lte_gpio_set_stage_ram; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e Gerrit-Change-Number: 43663 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/common/gpio_defs: Remove incorrent GPO macro
by Maxim Polyakov (Code Review) 07 Aug '23

07 Aug '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44471 ) Change subject: soc/intel/common/gpio_defs: Remove incorrent GPO macro ...................................................................... soc/intel/common/gpio_defs: Remove incorrent GPO macro GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. For this reason, this patch removes the PAD_CFG_GPO_GPIO_DRIVER macro as it is not correct. This has also been removed from the pad configuration in the follow boards and this patch should be added after: [1] Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 [2] Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 [3] Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea [4] Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c Change-Id: I74c318897647836f4604a937543254f44b470433 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/getting_started/gpio.md M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44471/1 diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 13aeed5..339289b 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -92,8 +92,6 @@ #define PAD_CFG_GPO(pad, val, rst) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) - /* General purpose output, no pullup/down. */ - #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) ``` diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 3d3c831..4dcf04c 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -229,14 +229,6 @@ PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) -/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ - PAD_CFG_OWN_GPIO(DRIVER)) - /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/44471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c318897647836f4604a937543254f44b470433 Gerrit-Change-Number: 44471 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45966 ) Change subject: WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm ...................................................................... WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm This adds the ACPI entry for the ACPI AC/DC Wake Alarm. This is different than the RTC wake alarm, because it waits until the system has entered S3 before firing the wake event. This prevents race conditions between setting the alarm and suspending in time. This is WIP because the SCI map is not getting set correctly. BUG=b:157533281 BRANCH=zork TEST=On Morphius try suspending and watching the system wake up localhost /sys/devices/platform/ACPI000E:00 # tail ac_* dc_* ==> ac_alarm <== disabled ==> ac_policy <== never ==> ac_status <== 0x00 ==> dc_alarm <== disabled ==> dc_policy <== never ==> dc_status <== 0x00 localhost /sys/devices/platform/ACPI000E:00 # echo 15 > ac_alarm localhost /sys/devices/platform/ACPI000E:00 # powerd_dbus_suspend <Device Resumes> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia99aaba98405f9b6e50b33936716da9a71338f58 --- M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/acdc.c M src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/acpi/wake_alarm.asl 5 files changed, 280 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45966/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a5562..f3836ad 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -123,7 +123,6 @@ #define ACPIMMIO_GPIO1_BANK 0x1600 #define ACPIMMIO_GPIO2_BANK 0x1700 #define ACPIMMIO_XHCIPM_BANK 0x1c00 -#define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 /* FIXME: Passing host base for SMBUS is not long-term solution. */ @@ -132,4 +131,6 @@ #endif +#define ACPIMMIO_ACDCTMR_BANK 0x1d00 + #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..6048691 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -80,6 +80,7 @@ ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c +ramstage-y += acdc.c ramstage-y += dmi.c smm-y += smihandler.c diff --git a/src/soc/amd/picasso/acdc.c b/src/soc/amd/picasso/acdc.c new file mode 100644 index 0000000..08c8404 --- /dev/null +++ b/src/soc/amd/picasso/acdc.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio_banks.h> +#include <bootstate.h> +#include <soc/smi.h> +#include <soc/soc_util.h> + +static const struct sci_source acdc_sci_sources[] = { + { + .scimap = SMITYPE_ACDC_TIMER, + .gpe = GEVENT_30, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, +}; + +static void configure_acdc_sci(void *unused) +{ + gpe_configure_sci(acdc_sci_sources, ARRAY_SIZE(acdc_sci_sources)); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_acdc_sci, NULL); diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b3b036e..a92d1e0 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -14,6 +14,9 @@ /* Describe the AOAC devices */ #include "aoac.asl" +/* Describe the Wake Alarm Device devices */ +#include "wake_alarm.asl" + /* Describe the devices in the Southbridge */ #include "sb_fch.asl" diff --git a/src/soc/amd/picasso/acpi/wake_alarm.asl b/src/soc/amd/picasso/acpi/wake_alarm.asl new file mode 100644 index 0000000..e5cd866 --- /dev/null +++ b/src/soc/amd/picasso/acpi/wake_alarm.asl @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio_map.h> + +Device(AWAK) { + Name(_HID, "ACPI000E") + OperationRegion (ACDC, SystemMemory, AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ACDCTMR_BANK, 0x24) + Field (ACDC, WordAcc, NoLock, Preserve) { + /* + * AC Timer Value + * + * Writing the register with a value other than FFFF_FFFFh + * starts the AC timer. Reading this register returns the + * current value of the AC timer. + */ + ACTV, 32, + + /* + * AC Expired Timer Policy + */ + ACTP, 32, + + /* + * AC Timer Status + */ + ACST, 32, + + Offset (0x10), + /* + * DC Timer Value + * + * Writing the register with a value other than FFFF_FFFFh + * starts the DC timer. Reading this register returns the + * current value of the DC timer. + */ + DCTV, 32, + + /* + * DC Expired Timer Policy + */ + DCTP, 32, + + /* + * DC Timer Status + */ + DCST, 32, + + Offset (0x20), + BUSY, 1, + , 7, /* Reserved */ + + ACEN, 1, /* Enable AC Timer to wake up system. */ + DCEN, 1, /* Enable DC Timer to wake up system. */ + , 22, /* Reserved */ + + } + + // _PRW: Power Resources for Wake + Name (_PRW, Package () { + 0x1E, + 0x03 + }) + + /** + * Get Capability + * + * Return Value: + * 31:9 - Reserved + * 8 - 1 = Wake supported from S5 on DC + * 7 - 1 = Wake supported from S4 on DC + * 6 - 1 = Wake supported from S5 on AC + * 5 - 1 = Wake supported from S4 on AC + * 4 - 1 = _GWS returns correct values for wakes from S4/S5 caused by + * timer + * 3 - 1 = Real time accuracy in milliseconds + * 0 = Real time accuracy in seconds + * 2 - 1 = Get/Set real time features implemented + * 1 - 1 = DC wake implemented + * 0 - 1 = AC wake implemented + * Bit [9] to Bit [31] are reserved and must be 0. + */ + Name (_GCP, 0x03) + + /** + * Get Wake alarm status + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 31:2 - Reserved + * 1 - 1 = Timer caused a platform wake + * 0 - 1 = Timer expired + */ + Method(_GWS, 1) { + If (Arg0) { + Return (DCST) + } Else { + Return (ACST) + } + } + + /** + * Clear Wake alarm status + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_CWS, 1) { + If (Arg0) { + DCST = 0x3 + } Else { + ACST = 0x3 + } + Return(0) + } + + /** + * Set Expired Timer Wake Policy + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Args1: Expired Timer Wake Policy + * 0 = The timer will wake up the system instantly after the power + * source changes. + * 1 - 0xFFFFFFFE = Time between the power source changes and the + * timer wakes up the system (in units of second). + * 0xFFFFFFFF = The timer will never wake up the system after the + * power source changes. + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_STP, 2) { + If (Arg0) { + DCTP = Arg1 + } Else { + ACTP = Arg1 + } + Return(0) + } + + /** + * Get Expired Timer Wake Policy + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 0 = The timer will wake up the system instantly after the power + * source changes. + * 1 - 0xFFFFFFFE = Time between the power source changes and the + * timer wakes up the system (in units of second). + * 0xFFFFFFFF = The timer will never wake up the system after the + * power source changes. + */ + Method(_TIP, 1) { + If (Arg0) { + Return (DCTP) + } Else { + Return (ACTP) + } + } + + /** + * Set Timer Value + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Args1: Timer Value + * + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_STV, 2, Serialized) { + If (Arg0) { + DCEN = 1 + While (BUSY) { + Printf ("Waiting for DC Timer") + Stall (100) + } + DCTV = Arg1 + While (BUSY) { + Printf ("Waiting for DC Timer to initialize") + Stall (100) + } + } Else { + ACEN = 1 + While (BUSY) { + Printf ("Waiting for AC Timer") + Stall (100) + } + ACTV = Arg1 + While (BUSY) { + Printf ("Waiting for AC Timer to initialize") + Stall (100) + } + } + Return(0) + } + + /** + * Get Timer Value + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 0 - 0xFFFFFFFE = The current timer value. + * 0xFFFFFFFF = The timer is disabled. + */ + Method(_TIV, 1) { + If (Arg0) { + Return (DCTV) + } Else { + Return (ACTV) + } + } +} + + +Scope(\_GPE) { + Method(_L30, 0, Serialized) { + Local0 = 0 + If (\_SB.AWAK._GWS(1) & 0x2) { /* DC timer caused wake */ + \_SB.AWAK._CWS(1) /* Clear DC timer wake */ + Local0 = 1 + } + + If (\_SB.AWAK._GWS(0) & 0x2) { /* AC timer caused wake */ + \_SB.AWAK._CWS(0) /* Clear AC timer wake */ + Local0 = 1 + } + + If (Local0) { + Notify(\_SB.AWAK, 0x2) //notify the OSPM of device wake + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia99aaba98405f9b6e50b33936716da9a71338f58 Gerrit-Change-Number: 45966 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/dell/latitude_e7240: Transform into variant
by Pablo Stebler (Code Review) 07 Aug '23

07 Aug '23

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46539 ) Change subject: mb/dell/latitude_e7240: Transform into variant ...................................................................... mb/dell/latitude_e7240: Transform into variant In preparation for E7440 support. Untested for now. Something like "hsw_bdw_laptops" could be a better name from a git history POV if other boards like E5450 or M4800 are subsequently added. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I95a9d72a285f296309f4c0d11ec0de6079ac383d --- D src/mainboard/dell/latitude_e7240/Kconfig.name D src/mainboard/dell/latitude_e7240/Makefile.inc D src/mainboard/dell/latitude_e7240/board_info.txt R src/mainboard/dell/latitude_e7x40/Kconfig A src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/Makefile.inc R src/mainboard/dell/latitude_e7x40/acpi/ec.asl R src/mainboard/dell/latitude_e7x40/acpi/platform.asl R src/mainboard/dell/latitude_e7x40/acpi/superio.asl R src/mainboard/dell/latitude_e7x40/acpi_tables.c A src/mainboard/dell/latitude_e7x40/board_info.txt R src/mainboard/dell/latitude_e7x40/bootblock.c R src/mainboard/dell/latitude_e7x40/devicetree.cb R src/mainboard/dell/latitude_e7x40/dsdt.asl R src/mainboard/dell/latitude_e7x40/gma-mainboard.ads R src/mainboard/dell/latitude_e7x40/mainboard.c R src/mainboard/dell/latitude_e7x40/romstage.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt R src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c R src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb 21 files changed, 39 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46539/1 diff --git a/src/mainboard/dell/latitude_e7240/Kconfig.name b/src/mainboard/dell/latitude_e7240/Kconfig.name deleted file mode 100644 index 83ab935..0000000 --- a/src/mainboard/dell/latitude_e7240/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_DELL_LATITUDE_E7240 - bool "Latitude E7240" diff --git a/src/mainboard/dell/latitude_e7240/Makefile.inc b/src/mainboard/dell/latitude_e7240/Makefile.inc deleted file mode 100644 index ec8ca22..0000000 --- a/src/mainboard/dell/latitude_e7240/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -bootblock-y += bootblock.c -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/board_info.txt b/src/mainboard/dell/latitude_e7240/board_info.txt deleted file mode 100644 index 46e950a..0000000 --- a/src/mainboard/dell/latitude_e7240/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: laptop -Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… -ROM protocol: SPI -ROM package: SOIC-8 -ROM socketed: n -Flashrom support: n -Release year: 2013 diff --git a/src/mainboard/dell/latitude_e7240/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig similarity index 65% rename from src/mainboard/dell/latitude_e7240/Kconfig rename to src/mainboard/dell/latitude_e7x40/Kconfig index 2e3b4b4..05ed643 100644 --- a/src/mainboard/dell/latitude_e7240/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -1,7 +1,7 @@ -if BOARD_DELL_LATITUDE_E7240 +## SPDX-License-Identifier: GPL-2.0-only -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_DELL_LATITUDE_E7x40 + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_DELL_MEC5055 select HAVE_ACPI_RESUME @@ -14,13 +14,19 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP +if BOARD_DELL_LATITUDE_E7x40 + config MAINBOARD_DIR string - default "dell/latitude_e7240" + default "dell/latitude_e7x40" + +config VARIANT_DIR + string + default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 config MAINBOARD_PART_NUMBER string - default "Latitude E7240" + default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name new file mode 100644 index 0000000..5eefdf7 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_LATITUDE_E7240 + bool "Latitude E7240" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/Makefile.inc b/src/mainboard/dell/latitude_e7x40/Makefile.inc new file mode 100644 index 0000000..eb2cc792 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/acpi/ec.asl b/src/mainboard/dell/latitude_e7x40/acpi/ec.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/ec.asl rename to src/mainboard/dell/latitude_e7x40/acpi/ec.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi/platform.asl b/src/mainboard/dell/latitude_e7x40/acpi/platform.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/platform.asl rename to src/mainboard/dell/latitude_e7x40/acpi/platform.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi/superio.asl b/src/mainboard/dell/latitude_e7x40/acpi/superio.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/superio.asl rename to src/mainboard/dell/latitude_e7x40/acpi/superio.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi_tables.c b/src/mainboard/dell/latitude_e7x40/acpi_tables.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi_tables.c rename to src/mainboard/dell/latitude_e7x40/acpi_tables.c diff --git a/src/mainboard/dell/latitude_e7x40/board_info.txt b/src/mainboard/dell/latitude_e7x40/board_info.txt new file mode 100644 index 0000000..6ad3641 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/dell/latitude_e7240/bootblock.c b/src/mainboard/dell/latitude_e7x40/bootblock.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/bootblock.c rename to src/mainboard/dell/latitude_e7x40/bootblock.c diff --git a/src/mainboard/dell/latitude_e7240/devicetree.cb b/src/mainboard/dell/latitude_e7x40/devicetree.cb similarity index 98% rename from src/mainboard/dell/latitude_e7240/devicetree.cb rename to src/mainboard/dell/latitude_e7x40/devicetree.cb index 345d504..ce7ef7a 100644 --- a/src/mainboard/dell/latitude_e7240/devicetree.cb +++ b/src/mainboard/dell/latitude_e7x40/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip northbridge/intel/haswell register "ec_present" = "true" register "gfx" = "GMA_STATIC_DISPLAYS(0)" @@ -24,8 +26,6 @@ end end device domain 0x0 on - subsystemid 0x1028 0x05ca inherit - device pci 00.0 on end # Host bridge Host bridge device pci 02.0 on end # Internal graphics VGA controller device pci 03.0 on end # Mini-HD audio diff --git a/src/mainboard/dell/latitude_e7240/dsdt.asl b/src/mainboard/dell/latitude_e7x40/dsdt.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/dsdt.asl rename to src/mainboard/dell/latitude_e7x40/dsdt.asl diff --git a/src/mainboard/dell/latitude_e7240/gma-mainboard.ads b/src/mainboard/dell/latitude_e7x40/gma-mainboard.ads similarity index 100% rename from src/mainboard/dell/latitude_e7240/gma-mainboard.ads rename to src/mainboard/dell/latitude_e7x40/gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/mainboard.c b/src/mainboard/dell/latitude_e7x40/mainboard.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/mainboard.c rename to src/mainboard/dell/latitude_e7x40/mainboard.c diff --git a/src/mainboard/dell/latitude_e7240/romstage.c b/src/mainboard/dell/latitude_e7x40/romstage.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/romstage.c rename to src/mainboard/dell/latitude_e7x40/romstage.c diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt new file mode 100644 index 0000000..cacaa17 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7240/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/gpio.c rename to src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c diff --git a/src/mainboard/dell/latitude_e7240/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/hda_verb.c rename to src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb new file mode 100644 index 0000000..416e09e --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05ca inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9d72a285f296309f4c0d11ec0de6079ac383d Gerrit-Change-Number: 46539 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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