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Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only
by Patrick Rudolph (Code Review) 04 Nov '22

04 Nov '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40830 ) Change subject: [WIP]security/intel: Add option to eanble SMM flash access only ...................................................................... [WIP]security/intel: Add option to eanble SMM flash access only On platforms where the boot media can be updated externally, for e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps the SMMSTORE working for the use in payloads. UNTESTED. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 8 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40830/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index d24c5e5..dbe6840 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -99,3 +99,13 @@ possible. This option prevents using write protecting facilities in ramstage, like the MRC cache for example. Use this option if you don't trust code running after verstage. + +config BOOTMEDIA_SMM_BWP + bool "Boot media only writable in SMM" + depends on ARCH_X86 + depends on HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE if SOC_INTEL_COMMON_BLOCK + help + Enable flash writes in SMM only. Select this if you want to secure + the SMM_STORE and don't need to update coreboot using the + internal controller. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index a00e5c0..768c4cd 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -62,6 +62,12 @@ /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + /* BIOS Lock */ fast_spi_set_lock_enable(); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 278e90a..78bfb39 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -416,16 +416,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -579,8 +569,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 5e967af..253d33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,6 +35,10 @@ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) +#define BIOS_CNTL 0xdc +#define LPC_BC_WE (1 << 0) /* WE */ +#define LPC_BC_LE (1 << 1) /* LE */ +#define LPC_BC_EISS (1 << 5) /* EISS */ static int spi_is_multichip(void); @@ -293,7 +297,6 @@ void spi_init(void) { - uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; uint16_t hsfs; @@ -345,10 +348,7 @@ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + spi_smm_only_flashing(0); } } @@ -1108,12 +1108,35 @@ writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } writew_(optype, cntlr.optype); + + spi_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { } +void spi_smm_only_flashing(bool enable) +{ + pci_devfn_t dev = PCI_DEV(0, 31, 0); + u8 reg8 = pci_read_config8(dev, BIOS_CNTL); + + if (reg8 & LPC_BC_LE) + return; + + if (enable) { + reg8 |= LPC_BC_EISS; + reg8 &= ~LPC_BC_WE; + } else { + reg8 &= ~LPC_BC_EISS; + reg8 |= LPC_BC_WE; + } + pci_write_config8(dev, BIOS_CNTL, reg8); + + printk(BIOS_SPEW, "BIOS updates outside of SMM %s\n", + enable ? "enabled" : "disabled"); +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..ad1cb27 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,7 @@ struct intel_spi_op ops[8]; }; +void spi_smm_only_flashing(bool enable); void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 395919e..67c03fa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -420,16 +420,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { /* @@ -482,8 +472,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d9ef5cc..dafb901 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -481,16 +481,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -549,8 +539,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..82e96f3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -40,6 +40,8 @@ void smm_southbridge_enable_smi(void) { + u32 mask; + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ enable_pm1(PWRBTN_EN | GBL_EN); @@ -49,11 +51,14 @@ * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on TCO events * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + mask = APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS; + if (CONFIG(BOOTMEDIA_SMM_BWP)) + mask |= TCO_EN; + enable_smi(mask); } static void __unused southbridge_trigger_smi(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Gerrit-Change-Number: 40830 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 48

Change in coreboot[master]: [TEST] Add support for link time optimization
by Jacob Garber (Code Review) 02 Nov '22

02 Nov '22

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38989 ) Change subject: [TEST] Add support for link time optimization ...................................................................... [TEST] Add support for link time optimization - Code generation is not done until after linking, so the compiler must be invoked at all linking stages instead of the linker. As a consequence all linker arguments must be prefixed with -Wl. - Partial linking is not supported. Instead, object files are collected into thin archives that are linked instead. - The dead_code() macro causes linking errors, since dead functions aren't optimized out until after linking has begun. This macro could be replaced with the preprocessor if necessary, or just disabled for LTO builds. - Wrapping libgcc functions causes a symbol mismatch when using LTO. Wrapping these functions was originally done to support alternate regparam values, though AFAICT this isn't used anywhere. Using LTO leads to a ~10% decrease in stage size for QEMU and ~18% for the Thinkpad T500, and both targets boot successfully. Change-Id: I48c31ea8b1b57276125cffdac44c7c16642547ac Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile.inc M src/Kconfig M src/arch/x86/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/include/assert.h M src/lib/Makefile.inc M src/lib/gcc.c M toolchain.inc M util/xcompile/xcompile 9 files changed, 42 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/38989/1 diff --git a/Makefile.inc b/Makefile.inc index 1f18726..b85c11b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -434,6 +434,10 @@ endif endif +ifeq ($(CONFIG_LTO),y) +CFLAGS_common += -flto -fuse-linker-plugin -fno-fat-lto-objects +endif + ADAFLAGS_common += -gnatp ADAFLAGS_common += -Wuninitialized -Wall -Werror ADAFLAGS_common += -pipe -g -nostdinc @@ -478,7 +482,7 @@ # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +LDFLAGS_common := -nostdlib -nostartfiles -static -Wl,--emit-relocs,--gc-sections ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror diff --git a/src/Kconfig b/src/Kconfig index f75f942..4b81818 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,6 +116,15 @@ For details see https://ccache.samba.org. +config LTO + bool "Use link time optimization" + # Enable now for testing + default y + depends on COMPILER_GCC + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 534f2ce..75f96d2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -80,7 +80,7 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) --oformat $(2) + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) -Wl,--whole-archive,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) -Wl,--oformat=$(2) -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 if [ -z "$$$$($$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders 2>&1 | grep 'no symbols')" ];then \ echo "Forbidden global variables in $(1):"; \ @@ -212,11 +212,11 @@ postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c -LDFLAGS_postcar += -Map $(objcbfs)/postcar.map +LDFLAGS_postcar += -Wl,-Map,$(objcbfs)/postcar.map $(objcbfs)/postcar.debug: $$(postcar-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) -Wl,--whole-archive,--start-group $(filter-out %.ld,$^) -Wl,--no-whole-archive $(COMPILER_RT_postcar) -Wl,--end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ @@ -309,18 +309,20 @@ endif -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) - @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +LDFLAGS_ramstage += -Wl,-m,elf_i386 else - $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +LDFLAGS_ramstage += -Wl,-m,elf_x86_64 endif +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.a $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) $(COMPILER_RT_FLAGS_ramstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $< -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + +$(objgenerated)/ramstage.a: $$(ramstage-objs) $$(ramstage-libs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_ramstage) rcT $@ $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) + endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..f582a31 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -25,8 +25,8 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) -$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group +$(obj)/smm/smm.a: $$(smm-objs) + $(AR_smm) rcT $@ $^ # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -53,7 +53,7 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) - $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) -Wl,--whole-archive,--start-group $(smmstub-objs) -Wl,--no-whole-archive $(COMPILER_RT_smmstub) -Wl,--end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,9 +72,9 @@ # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) else -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod @@ -82,8 +82,8 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +$(obj)/smm/smm: $(obj)/smm/smm.a $(src)/cpu/x86/smm/smm.ld + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld -Wl,--whole-archive,--start-group $(obj)/smm/smm.a -Wl,--no-whole-archive $(COMPILER_RT_smm) --end-group $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/include/assert.h b/src/include/assert.h index e0db0bc..6901953 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -61,7 +61,8 @@ dead_code_assertion_failed_at_line_##line(); \ } while (0) #define _dead_code(line) __dead_code(line) -#define dead_code() _dead_code(__LINE__) +//#define dead_code() _dead_code(__LINE__) +#define dead_code() /* This can be used in the context of an expression of type 'type'. */ #define dead_code_t(type) ({ \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64..ac6d624 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -291,7 +291,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--no-whole-archive $$(COMPILER_RT_rmodules_$(4)) -Wl,--end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map endef diff --git a/src/lib/gcc.c b/src/lib/gcc.c index 5a93f45..66a7788 100644 --- a/src/lib/gcc.c +++ b/src/lib/gcc.c @@ -24,6 +24,7 @@ /* TODO: maybe this code should move to arch/x86 as architecture * specific implementations may vary */ +#if 0 #define WRAP_LIBGCC_CALL(type, name) \ asmlinkage type __real_##name(type a, type b); \ type __wrap_##name(type a, type b); \ @@ -33,3 +34,4 @@ WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) WRAP_LIBGCC_CALL(long long, __moddi3) WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) +#endif diff --git a/toolchain.inc b/toolchain.inc index 865227b..f52a518 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -117,7 +117,7 @@ $(error Check your .config file for CONFIG_ARCH_$(1)_* settings)) CC_$(1) := $(CC_$(2)) GCC_$(1) := $(GCC_CC_$(2)) -LD_$(1) := $(LD_$(2)) +LD_$(1) := $(CC_$(2)) NM_$(1) := $(NM_$(2)) AR_$(1) := $(AR_$(2)) GNATBIND_$(1) := $(GNATBIND_$(2)) @@ -130,7 +130,7 @@ CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) -D__ARCH_$(2)__ COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) -LDFLAGS_$(1) = $$(LDFLAGS_common) $$(LDFLAGS_$(2)) +LDFLAGS_$(1) = $$(CFLAGS_$(1)) $$(LDFLAGS_common) $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3203d71..8515813 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -363,7 +363,7 @@ TCLIST="i386 x86_64" TWIDTH="32" TABI="elf" - CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3" + #CC_RT_EXTRA_GCC="-Wl,--wrap=__divdi3,--wrap=__udivdi3,--wrap=__moddi3,--wrap=__umoddi3" } arch_config_ppc64() { -- To view, visit https://review.coreboot.org/c/coreboot/+/38989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48c31ea8b1b57276125cffdac44c7c16642547ac Gerrit-Change-Number: 38989 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: mb/{lenovo,packardbell}: Enable MEI device
by Evgeny Zinoviev (Code Review) 01 Nov '22

01 Nov '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42412 ) Change subject: mb/{lenovo,packardbell}: Enable MEI device ...................................................................... mb/{lenovo,packardbell}: Enable MEI device Enable the MEI in device trees of some Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42412/1 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e608..9107f7c 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -51,7 +51,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d..fa63971 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -56,7 +56,9 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - device pci 16.0 off end # MEI + device pci 16.0 on # MEI + subsystemid 0x17aa 0x215f + end device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..795c372 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -69,7 +69,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c3..7a2f669 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -71,7 +71,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706e..694f258 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -72,7 +72,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea..b1a1131 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -68,7 +68,7 @@ register "spi_lvscc" = "0x2005" device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da3..0c8fe79 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,7 +68,7 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f..b614e83 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -48,7 +48,9 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1025 0x0379 + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R, only management boot device pci 16.3 off end # Management Engine KT -- To view, visit https://review.coreboot.org/c/coreboot/+/42412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Gerrit-Change-Number: 42412 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37321 ) Change subject: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB ...................................................................... cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37321/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index efb5fa9..335463d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -139,9 +139,9 @@ config SMM_LAPIC_REMAP_MITIGATION bool - default y if NORTHBRIDGE_INTEL_I945 - default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ + || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ + || NORTHBRIDGE_INTEL_E7505 default n config SERIALIZED_SMM_INITIALIZATION -- To view, visit https://review.coreboot.org/c/coreboot/+/37321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Gerrit-Change-Number: 37321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: WIP: riscv/mb/qemu: fix DRAM probing
by Philipp Hug (Code Review) 25 Oct '22

25 Oct '22

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36486 ) Change subject: WIP: riscv/mb/qemu: fix DRAM probing ...................................................................... WIP: riscv/mb/qemu: fix DRAM probing Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. TEST=qemu detects RAM size correctly Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/arch/exception.h A src/arch/riscv/ramdetect.c M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S M src/lib/ramdetect.c 6 files changed, 57 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36486/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0039fab..7465a8f 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -101,6 +101,7 @@ romstage-y += stages.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c +romstage-y += ramdetect.c romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -142,6 +143,7 @@ ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c +ramstage-y += ramdetect.c ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 6fbbdf0..cdca582 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -53,7 +53,7 @@ } void redirect_trap(void); -void trap_handler(trapframe *tf); +void default_trap_handler(trapframe *tf); void handle_supervisor_call(trapframe *tf); void handle_misaligned(trapframe *tf); diff --git a/src/arch/riscv/ramdetect.c b/src/arch/riscv/ramdetect.c new file mode 100644 index 0000000..47153ab --- /dev/null +++ b/src/arch/riscv/ramdetect.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/exception.h> +#include <types.h> +#include <console/console.h> +#include <device/mmio.h> +#include <ramdetect.h> +#include <arch/smp/spinlock.h> + +static enum { + ABORT_CHECKER_NOT_TRIGGERED, + ABORT_CHECKER_TRIGGERED, +} abort_state = ABORT_CHECKER_NOT_TRIGGERED; + +extern void(*trap_handler)(trapframe *tf); + +#define insn_size 4 +static void ramcheck_trap_handler(trapframe *tf) +{ + printk(BIOS_DEBUG, "TRAP 0x%lx!!!\n", tf->epc); + abort_state = ABORT_CHECKER_TRIGGERED; + + /* + * skip read instruction. + * currenctly hardcoded to 32bit instruction size + */ + write_csr(mepc, read_csr(mepc) + insn_size); +} + +int probe_mb(const uintptr_t dram_start, const uintptr_t size) +{ + uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); + void *ptr = (void *)addr; + + abort_state = ABORT_CHECKER_NOT_TRIGGERED; + trap_handler = ramcheck_trap_handler; + barrier(); + read32(ptr); + trap_handler = default_trap_handler; + barrier(); + return abort_state == ABORT_CHECKER_NOT_TRIGGERED; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 6b39fab..1d51268 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -118,7 +118,10 @@ break; } } -void trap_handler(trapframe *tf) + +void(*trap_handler)(trapframe *tf) = default_trap_handler; + +void default_trap_handler(trapframe *tf) { write_csr(mscratch, tf); if (tf->cause & 0x8000000000000000ULL) { diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 67e917c..93f5afd 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -120,7 +120,8 @@ save_tf mv a0, sp - jal trap_handler + ld t0, trap_handler + jalr t0 restore_regs addi sp, sp, MENTRY_FRAME_SIZE diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 2c83092..eaf6190 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -58,6 +58,8 @@ if (saved_result) return saved_result; + printk(BIOS_DEBUG, "RAMDETECT: Starting\n"); + /* Find the MSB + 1. */ size_t tmp = probe_size; do { -- To view, visit https://review.coreboot.org/c/coreboot/+/36486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Gerrit-Change-Number: 36486 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45278 ) Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps ...................................................................... WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps Use GPIOs mapping defined in APCB GET_SPD_FROM_GPIO to fetch correct SPD block from PSP BIOS table entry type 0x69 (BIOS_SPD_DATA). There is only one APCB now with no SPD data in it. No need for board ID getting method. This will save ROM space consumed by multiple APCB copies in the past. This is a working example of an implementation tested on Dalboz. It does not require patching with APCB_EDIT_TOOL. All SPDs are assembled in one type 0x69 blob and inserted into PSP BIOS directory. BUG=b:127505025 TEST=Dalboz with CABLRV20090300 and test CB and boot loader code BRANCH=Zork Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45278/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index eb2be50..e83e08d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ # # type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) +PSP_SPD_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/SPD_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -262,6 +262,12 @@ # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 +# SPD data array blob (with SPDs for all possible memory IDs for this platform) +SPD_BLOB:=$(obj)/SPD_array.bin + +# APCB binary without SPD data +APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ @@ -304,9 +310,8 @@ OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) -OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) +OPT_PSP_APCB_FILE=$(call add_opt_prefix, $(APCB_NO_SPD_BLOB), --instance 0 --apcb) +OPT_SPD_BLOB=$(call add_opt_prefix, $(SPD_BLOB), --spd-data-blob) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) @@ -341,7 +346,8 @@ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILE) \ + $(OPT_SPD_BLOB) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ @@ -383,6 +389,16 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +$(obj)/SPD_%.bin: $$(SPD_SOURCES_DIR)/%.hex + xxd -r -p $< > $@ + +$(SPD_BLOB): $$(PSP_SPD_FILES) + cat $+ > $@ + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -418,12 +434,22 @@ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ + $(PSP_APCB_FILE) \ + $(SPD_BLOB) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@ $(AMDFWTOOL) \ $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f385068..2192a04 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,6 +215,7 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("--spd-data-blob Add SPD array\n"); printf("-C | --soc-name <socname> Specify SOC name. Supported names are\n"); printf(" Stoneyridge, Raven, Picasso, Renoir or Lucienne"); printf("-h | --help show this help\n"); @@ -251,6 +252,7 @@ AMD_BIOS_PMUD = 0x65, AMD_BIOS_UCODE = 0x66, AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_SPD_DATA = 0x69, AMD_BIOS_MP2_CFG = 0x6a, AMD_BIOS_PSP_SHARED_MEM = 0x6b, AMD_BIOS_L2_PTR = 0x70, @@ -409,6 +411,7 @@ { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, + { .type = AMD_BIOS_SPD_DATA, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, @@ -1085,6 +1088,7 @@ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, LONGOPT_SPI_MICRON_FLAG = 258, + LONGOPT_SPD_DATA = 259, }; // Unused values: D @@ -1136,6 +1140,7 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + {"spd-data-blob", required_argument, 0, LONGOPT_SPD_DATA }, /* Embedded Firmware Structure items*/ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, @@ -1450,6 +1455,11 @@ instance, optarg); sub = instance = 0; break; + case LONGOPT_SPD_DATA: + /* optional SPD data array outside of APCB */ + register_bdt_data(AMD_BIOS_SPD_DATA, sub, instance, optarg); + sub = instance = 0; + break; case 'Q': /* APOB destination */ register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Gerrit-Change-Number: 45278 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: arch/x86: x86_64 implies SSE2 support
by Patrick Rudolph (Code Review) 24 Oct '22

24 Oct '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44869 ) Change subject: arch/x86: x86_64 implies SSE2 support ...................................................................... arch/x86: x86_64 implies SSE2 support Enable SSE2 when compiling for x86_64. Tested on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig M src/arch/x86/bootblock_crt0.S 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44869/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index d906436..d0e4693 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -33,22 +33,27 @@ config ARCH_BOOTBLOCK_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_VERSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_ROMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_POSTCAR_X86_64 bool default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE + select SSE2 config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 if ARCH_X86 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413..9e17b7e 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -52,9 +52,15 @@ #if CONFIG(SSE) enable_sse: +#if ENV_X86_32 mov %cr4, %eax or $CR4_OSFXSR, %ax mov %eax, %cr4 +#else + mov %cr4, %rax + or $CR4_OSFXSR, %ax + mov %rax, %cr4 +#endif #endif /* CONFIG(SSE) */ /* We're done. Now it's up to platform-specific code */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Gerrit-Change-Number: 44869 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: arch/x86: Don't use .bss from car.ld if not running XIP
by Arthur Heymans (Code Review) 20 Oct '22

20 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48156 ) Change subject: arch/x86: Don't use .bss from car.ld if not running XIP ...................................................................... arch/x86: Don't use .bss from car.ld if not running XIP Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48156/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..7d7d3fc 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -36,6 +36,7 @@ mov $_STACK_TOP, %esp /* clear .bss section as it is not shared */ +#if ENV_STAGE_XIP cld xor %eax, %eax movl $(_ebss), %ecx @@ -43,6 +44,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c291efb..38128d1 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -62,6 +62,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram. */ +#if ENV_STAGE_HAS_CAR_XIP_BSS . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; /* Allow global uninitialized variables for stages without CAR teardown. */ @@ -71,6 +72,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; diff --git a/src/include/rules.h b/src/include/rules.h index 6ebb37e..f503914 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -261,14 +261,21 @@ #if ENV_X86 /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* Indicates if the stage runs XIP. */ +#define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ + !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 #define ENV_CACHE_AS_RAM 0 +#define ENV_STAGE_XIP 0 #endif +/* Indicates if the stages uses the _bss region defined in arch/x86/car.ld */ +#define ENV_STAGE_HAS_CAR_XIP_BSS ENV_STAGE_XIP + /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) diff --git a/src/lib/program.ld b/src/lib/program.ld index 3b6aa2e..ff3c672 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -103,7 +103,7 @@ } #endif -#if !ENV_CACHE_AS_RAM +#if !ENV_STAGE_HAS_CAR_XIP_BSS .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/48156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Gerrit-Change-Number: 48156 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

8 32

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 04 Oct '22

04 Oct '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: include/rules.h: Allow .data section on non-XIP stages
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48157 ) Change subject: include/rules.h: Allow .data section on non-XIP stages ...................................................................... include/rules.h: Allow .data section on non-XIP stages This allows platform that don't run stage XIP to have a .data section. Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/rules.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48157/1 diff --git a/src/include/rules.h b/src/include/rules.h index f503914..a7fc77f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -265,7 +265,7 @@ #define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION !ENV_STAGE_XIP #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Gerrit-Change-Number: 48157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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