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Change in coreboot[master]: mb/asus/p2b: Add ACPI support for p3b-f
by Keith Hui (Code Review) 03 Jan '23

03 Jan '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41098 ) Change subject: mb/asus/p2b: Add ACPI support for p3b-f ...................................................................... mb/asus/p2b: Add ACPI support for p3b-f Finally! Power button works to turn board on and off. ACPI hooks to manipulate power and message LEDs work. Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/dsdt.asl A src/mainboard/asus/p2b/suspend.asl A src/mainboard/asus/p2b/variants/p3b-f/suspend.asl 4 files changed, 393 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41098/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 1ad25e1..45018d6 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -29,7 +29,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F - select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS config MAX_CPUS diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 88be9ba..623b575 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -53,6 +53,7 @@ { Offset (0x03), TO12, 1, /* Device trap 12 */ +#if !CONFIG(BOARD_ASUS_P3B_F) Offset (0x08), FANM, 1, /* GPO0, meant for fan */ Offset (0x09), @@ -61,33 +62,25 @@ , 2, , 16, MSG0, 1 /* GPO30, message LED */ +#endif } - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) + OperationRegion (ECOS, SystemIO, 0x72, 0x02) + Field (ECOS, ByteAcc, NoLock, Preserve) { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) + CIDX, 8, + CDAT, 8 } - Method (\_WAK, 1, NotSerialized) + IndexField (CIDX, CDAT, ByteAcc, NoLock, Preserve) { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) + Offset (0x58), + RTCS, 8, + Offset (0x5F), + SUS3, 1, + , 3, + SLST, 4 } - /* Root of the bus hierarchy */ Scope (\_SB) { @@ -169,19 +162,9 @@ } } - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } +#if CONFIG(BOARD_ASUS_P3B_F) +#include "variants/p3b-f/suspend.asl" +#else +#include "suspend.asl" +#endif } diff --git a/src/mainboard/asus/p2b/suspend.asl b/src/mainboard/asus/p2b/suspend.asl new file mode 100644 index 0000000..5d2b540 --- /dev/null +++ b/src/mainboard/asus/p2b/suspend.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* ASUS P2B family board DSDT declarations (at top level) that does not apply to P3B-F */ + +/** + * ACPI message indicator. + * + * @param Arg0 Number of waiting messages + */ +Scope (\_SI) +{ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } +} + +/** + * Prepare To Sleep. + * + * @param Arg0 Target ACPI S-state + */ +Method (\_PTS, 1, NotSerialized) +{ + /*SLST = Arg0*/ + /* Disable fan, blink power LED. S5 will turn them off too */ + If (Arg0 != 5) + { + FANM = 0 + PLED = 0 + } + + /* Arms SMI for device 12 */ + Store (One, TO12) + /* Put out a POST code */ + P80 = 0xF0 | Arg0 +} + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ +Method (\_WAK, 1, NotSerialized) +{ + /* Re-enable fan, stop power led blinking */ + FANM = 1 + PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) +} + diff --git a/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl new file mode 100644 index 0000000..a84c700 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "southbridge/intel/i82371eb/i82371eb.h" + +/* ASUS P3B-F board specific (top level) DSDT declarations */ + +Name (PRW1, Package (0x04) +{ + Package (0x02) {0x09, 0x01}, + Package (0x02) {0x08, 0x01}, + Package (0x02) {0x0A, 0x01}, + Package (0x02) {0x0B, 0x01} +}) + +Name (PRW3, Package (0x04) +{ + Package (0x02) { 0x09, 0x03 }, + Package (0x02) { 0x08, 0x03 }, + Package (0x02) { 0x0A, 0x03 }, + Package (0x02) { 0x0B, 0x04 } +}) + +Name (PRWT, Package (0x04) +{ + 0x09, + 0x08, + 0x0A, + 0x0B +}) + +/* SPRW(n) = (SUS3==0) ? PRW1[n] : PRW3[n] */ +Method (SPRW, 1, NotSerialized) +{ + Store (Match (PRWT, MEQ, Arg0, MTR, 0x00, 0x00), Local0) + If (LEqual (SUS3, Zero)) + { + Return (DerefOf (Index (PRW1, Local0))) + } + Else + { + Return (DerefOf (Index (PRW3, Local0))) + } +} + +/* + * SMBus driver functions + * + * These functions communicate with the AS99127F ASIC on the P3B-F to handle hardware + * sequencing required around S3 suspend and resume. This chip is undocumented except it has + * W83781D-compatible hardware monitoring features, and seems to be responsible for hiding the + * flashchip from internal programming via flashrom. + * + * Note: The SMBus host controller interface is located in the southbridge. + */ + /* The SMBus controller hardware interface. Only byte accesses covered. */ + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + /* Wait for SMBus activity to complete, error or not */ + Method (SWFS, 0, NotSerialized) + { + And (HSTS, 0x06, Local0) + While (Local0 == 0) + { + Stall (1) + And (HSTS, 0x06, Local0) + } + } + + /** + * Writes a byte to a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @param Arg2 Data + */ + Method (WBYT, 3, NotSerialized) + { + Store (Arg0, ADDR) + Store (Arg1, CMDR) + Store (Arg2, DAT0) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + SWFS () + } + + /** + * Reads a byte from a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @return Data read + */ + Method (RBYT, 2, NotSerialized) + { + Or (Arg0, 0x01, ADDR) /* Set bit 0, this will be a read */ + Store (Arg1, CMDR) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + + /* If interrupted without success, restart and try again */ + And (HSTS, 0x02, Local0) + While (LEqual (Local0, Zero)) + { + Store (0xFF, HSTS) + Store (0x48, CTLR) + SWFS () + And (HSTS, 0x02, Local0) + } + + Return (DAT0) /* \DAT0 */ + } + + Method (SGOH, 2, NotSerialized) + { + /* SMBus address 0x48 */ + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Or (Local1, Arg1, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (SGOL, 2, NotSerialized) + { + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Not (Arg1, Local2) + And (Local1, Local2, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (FANC, 1, NotSerialized) + { + /* SMBus address 0x2d */ + WBYT (0x5A, 0x59, Arg0) + } + + Method (FANP, 1, NotSerialized) + { + WBYT (0x5A, 0x5A, Arg0) + } + + Method (EN18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + And (Local1, 0xDF, Local1) + WBYT (Local0, 0x5F, Local1) + } + + Method (DS18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + Or (Local1, 0x20, Local1) + WBYT (Local0, 0x5F, Local1) + } + +/** + * Prepare To Sleep, + * + * @param Arg0 Target ACPI S-state + */ + Method (\_PTS, 1, NotSerialized) + { + SLST = Arg0 + If (Arg0 == 0x01) + { + /* Disable BX.PMCR[CRst_En] */ + Store (\_SB.PCI0.NB.PMCR, Local0) + And (Local0, 0xFE, \_SB.PCI0.NB.PMCR) + + /* Isolate CPU_STP# and SUS_STAT1# signals at GENCFG register */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + Or (Local0, 0x24, Local1) + Store (Local1, \_SB.PCI0.PX40.FXS1) + + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + /* In SIO Dev A CR E4 = xxxx01xx (these bits are reserved per datasheet?) */ + And (\_SB.PCI0.KBWK, 0xF7, Local0) + Or (Local0, 0x04, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + } + + If (Arg0 == 0x03) + { + SGOH (0x83, 0x04) + SGOL (0x80, 0x04) + SGOH (0x80, 0x04) + SGOH (0x83, 0x01) + EN18 () + } + + /* Arms SMI for device 12 */ + TO12 = 1 + /* Put out a POST code */ + P80 = 0xF0 | Arg0 + } + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ + Method (\_WAK, 1, NotSerialized) // _WAK: Wake + { + DS18 () + Store (Zero, TO12) + /* Restore CPU_STP# and SUS_STAT1# signals */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + And (Local0, 0xDB, \_SB.PCI0.PX40.FXS1) + SGOL (0x83, 0x01) + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + And (\_SB.PCI0.MSWK, 0xFD, Local1) + Store (Local1, \_SB.PCI0.MSWK) + /* In SIO Dev A CR E4 = xxxx00xx */ + And (\_SB.PCI0.KBWK, 0xF3, Local0) + Store (Local0, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + /* Put out a POST code */ + P80 = 0xFF + Return(Package(0x02){0x00, 0x00}) + } + + Scope (\_GPE) + { + Method (_L0A, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0.SER2, 0x02) // Device Wake + Notify (\_SB.PCI0.SER3, 0x02) // Device Wake + } + + Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0, 0x02) // Device Wake + } + } + +Scope (\_SI) +{ + /** + * ACPI message indicator + * + * @param Arg0 Number of waiting messages + */ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + SGOL (0x81, 0x02) + SGOH (0x81, 0x01) + SGOL (0x81, 0x01) + } + Else + { + SGOH (0x81, 0x02) + SGOL (0x81, 0x02) + } + } + + + /** + * System Status. OS calls to set system status indicator. + * Arg0: + * 0 = Indicator off + * 1 = Working + * 2 = Waking + * 3 = Sleeping: States S1, S2, S3 + * 4 = Sleeping with context saved to non-volatile storage. + * + * @param Arg0 System status indicator + */ + Method (_SST, 1, NotSerialized) // _SST: System Status + { + If (LEqual (Arg0, 0x00)) + { + SGOH (0x80, 0x40) + } + ElseIf (LEqual (Arg0, 0x03)) + { + SGOL (0x80, 0x40) + SGOL (0x80, 0x80) + FANC (0x81) + FANP (0x81) + } + Else + { + SGOL (0x80, 0x40) + SGOH (0x80, 0x80) + FANC (0x8F) + FANP (0x8F) + } + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/41098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Gerrit-Change-Number: 41098 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: sb/intel/i82371eb: Implement SMBus Control Method Interface support
by Keith Hui (Code Review) 03 Jan '23

03 Jan '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41735 ) Change subject: sb/intel/i82371eb: Implement SMBus Control Method Interface support ...................................................................... sb/intel/i82371eb: Implement SMBus Control Method Interface support Upcoming ACPI support for asus/p3b-f mainboard contains ASL code to manipulate its AS99127F chip over SMBus before and after suspend, to blink front panel lights, turn off fans, among other things. This code caused an ACPI/PCI resource conflict that disabled access to the entire SMBus, rendering its hardware monitor inoperative, and all resolution attempts so far have not worked. This is an attempt to expand the ASL SMBus routines into a complete SMBus Control Method Interface (SCMI), that Linux kernel can use via the i2c-scmi driver, sidestepping this conflict. Because SCMI methods begin with an underscore, which iasl considers "unknown reserved name", on which our build process errors out, it must also be told to ignore this particular warning, at least for asus/p3b-f. Change-Id: I97deb2d292af25e42068474f48e11c94a7480be6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Makefile.inc M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 2 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41735/1 diff --git a/Makefile.inc b/Makefile.inc index 210e9cf..d1aebd3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -253,11 +253,17 @@ # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 +UNKNOWN_RESERVED_NAME = 3133 + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) else +ifeq ($(CONFIG_BOARD_ASUS_P3B_F),y) +IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(UNKNOWN_RESERVED_NAME) +else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) endif +endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index b64036e..27c2a3c 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -2,6 +2,8 @@ #include "southbridge/intel/i82371eb/i82371eb.h" +#define SCMI_MUTEX SBX0 + /* Declares assorted devices that falls under this southbridge. */ Device (PX40) { @@ -135,4 +137,179 @@ }) Return (BUF1) } +/* Begin SCMI implementation */ + Mutex(SCMI_MUTEX, 1) + + Device (SMB0) + { + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + /* Should have been SMBUS01, but Intel iasl won't accept */ + Name (_HID, "SMB0001") + + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* SMBus register ports */ + IO (Decode16, SMBUS_IO_BASE, SMBUS_IO_BASE, 0x01, 0x10, ) + }) + Return (BUF1) + } + /** + * SCMI: SMBus Information + * + * @return SMBus information buffer + */ + Method (_SBI, 0) + { + Local0 = Package(2) {0x10, Buffer() + { + 0x10, 0x10, /* SCMI and SMBus versions, both 1.0 */ + 0, 0, + 3, /* Device count */ + 0x2d, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x48, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x49, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 + } + }; + return (Local0) + } + /** + * Read from a SMBus device. + * + * @param Arg0 Protocol + * @param Arg1 Slave address + * @param Arg2 Command (register index in our case) + * @return Package (status code, data length, data) + */ + Method (_SBR, 3) { + Local2 = Package(3) {0, 0, 0} + if (Arg0 == 0x07) + { + Local0 = 0x48 /* Start a byte data R/W access */ + Local3 = 1; /* 1 byte */ + } + elseif (Arg0 == 0x09) + { + Local0 = 0x4c /* Start a word data R/W access */ + } + else + { + Index(Local2, 0) = 0x19 // Protocol not supported + return (Local2) + } + if (HSTS & 0x01) + { + Index(Local2, 0) = 0x1a // Bus busy + return (Local2) + } + if (Acquire(SCMI_MUTEX, 100)) + { + Index(Local2, 0) = 0x18 // Timeout + } else { + ADDR = (Arg1 << 1) | 0x01 /* Set bit 0, this is a read */ + CMDR = Arg2 + HSTS = 0xFF + CTLR = Local0 + + while (HSTS & 0x01) + { + Stall(1) + } + if (HSTS & 0x06) + { + Index(Local2, 0) = 0x11 /* Device error */ + } + else + { + Local1 = DAT0 + /* Get high byte of word read */ + if (Arg0 == 0x09) + { + Local1 |= (DAT1 << 8) + Local3 = 2 /* 2 bytes */ + } + Index(Local2, 1) = Local3 + Index(Local2, 2) = Local1 + } + Release(SCMI_MUTEX); + } + return (Local2); + } + /** + * Write to a SMBus device. + * + * @param Arg0 Protocol + * @param Arg1 Slave address + * @param Arg2 Command (register index in our case) + * @param Arg3 Data length + * @param Arg4 Data + * @return Status code + */ + Method (_SBW, 5) { + if (Arg0 == 0x06) + { + Local0 = 0x48 /* Start a byte data R/W access */ + } + elseif (Arg0 == 0x08) + { + Local0 = 0x4c /* Start a word data R/W access */ + } + else + { + Return (0x19) //* Protocol not supported */ + } + if (HSTS & 0x01) + { + Return (0x1a) /* Bus busy */ + } + if (Acquire(SCMI_MUTEX, 100)) + { + Local1 = 0x18 /* Timeout */ + } + else + { + Local1 = 0 + ADDR = Arg1 << 1 + CMDR = Arg2 + DAT0 = Arg4 + if (Arg0 == 0x08) { + DAT1 = Arg4 >> 8 + } + HSTS = 0xFF + CTLR = Local0 + while (HSTS & 0x01) + { + Stall(1) + } + if (HSTS & 0x06) + { + Local1 = 0x11 /* Device error */ + } + Release(SCMI_MUTEX) + } + return (Local1); + } + /* _SBT, _SBA not implemented */ + } +/* End SCMI implementation */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/41735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97deb2d292af25e42068474f48e11c94a7480be6 Gerrit-Change-Number: 41735 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: sb/intel/lynxpoint/me_9.x.c: Reorder functions
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42631 ) Change subject: sb/intel/lynxpoint/me_9.x.c: Reorder functions ...................................................................... sb/intel/lynxpoint/me_9.x.c: Reorder functions This file is shared between ramstage and smm. However, not everything is used in both ramstage and smm, so there's a lot of `__unused` tags. So, reorder the functions so that they build only for stages needing them. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/me_9.x.c 1 file changed, 167 insertions(+), 180 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42631/1 diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index d182e31..eaeab0f 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -31,24 +31,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* Path that the BIOS should take based on ME state */ -static const char *const me_bios_path_values[] __unused = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); - /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#ifdef __SIMPLE_DEVICE__ -void intel_me_mbp_clear(pci_devfn_t dev); -#else -void intel_me_mbp_clear(struct device *dev); -#endif static void mei_dump(void *ptr, int dword, int offset, const char *type) { @@ -426,8 +410,10 @@ * the MBP has been read and cleared. */ #ifdef __SIMPLE_DEVICE__ +void intel_me_mbp_clear(pci_devfn_t dev); void intel_me_mbp_clear(pci_devfn_t dev) #else +void intel_me_mbp_clear(struct device *dev); void intel_me_mbp_clear(struct device *dev) #endif { @@ -450,73 +436,10 @@ } } -static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) -{ - if (!vers_name) { - printk(BIOS_ERR, "ME: mbp missing version report\n"); - return; - } - - printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", - vers_name->major_version, vers_name->minor_version, - vers_name->hotfix_version, vers_name->build_version); -} - -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); -} - -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mbp_mefwcaps *cap) -{ - u32 rule_id = 0; - struct me_fwcaps cap_msg; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - - /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), - &cap_msg, sizeof(cap_msg)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - *cap = cap_msg.caps_sku; - return 0; -} - -/* Get ME Firmware Capabilities */ -static void __unused me_print_fwcaps(mbp_mefwcaps *cap) -{ - mbp_mefwcaps local_caps; - if (!cap) { - cap = &local_caps; - printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); - if (mkhi_get_fwcaps(cap)) - return; - } - - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); -} +#ifdef __SIMPLE_DEVICE__ /* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -535,8 +458,6 @@ return 0; } -#ifdef __SIMPLE_DEVICE__ - void intel_me_finalize_smm(void) { struct me_hfs hfs; @@ -768,94 +689,6 @@ return 0; } -/* Check whether ME is present and do basic init */ -static void intel_me_init(struct device *dev) -{ - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - me_bios_path path = intel_me_path(dev); - me_bios_payload mbp_data; - - /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); - - if (path == ME_NORMAL_BIOS_PATH) { - /* Validate the extend register */ - intel_me_extend_valid(dev); - } - - memset(&mbp_data, 0, sizeof(mbp_data)); - - /* - * According to the ME9 BWG, BIOS is required to fetch MBP data in - * all boot flows except S3 Resume. - */ - - /* Prepare MEI MMIO interface */ - if (intel_mei_setup(dev) < 0) - return; - - if (intel_me_read_mbp(&mbp_data, dev)) - return; - - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { - me_print_fw_version(mbp_data.fw_version_name); - - if (CONFIG(DEBUG_INTEL_ME)) - me_print_fwcaps(mbp_data.fw_capabilities); - - if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); - } - } - - /* Set clock enables according to devicetree */ - if (config && config->icc_clock_disable) - me_icc_set_clock_enables(config->icc_clock_disable); - - /* - * Leave the ME unlocked. It will be locked via SMI command later. - */ -} - -static void intel_me_enable(struct device *dev) -{ - /* Avoid talking to the device in S3 path */ - if (acpi_is_wakeup_s3()) { - dev->enabled = 0; - pch_disable_devfn(dev); - } -} - -static struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = intel_me_enable, - .init = intel_me_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - 0x8c3a, /* Mobile */ - 0x9c3a, /* Low Power */ - 0 -}; - -static const struct pci_driver intel_me __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -#endif /* !__SIMPLE_DEVICE__ */ - -/****************************************************************************** - * */ static u32 me_to_host_words_pending(void) { struct mei_csr me; @@ -875,7 +708,7 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; @@ -884,11 +717,7 @@ struct mbp_payload *mbp; int i; -#ifdef __SIMPLE_DEVICE__ - pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2); -#else pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); -#endif if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); @@ -998,10 +827,168 @@ return 0; mbp_failure: -#ifdef __SIMPLE_DEVICE__ - intel_me_mbp_give_up(PCI_BDF(dev)); -#else intel_me_mbp_give_up(dev); -#endif + return -1; } + +static void me_print_fw_version(mbp_fw_version_name *vers_name) +{ + if (!vers_name) { + printk(BIOS_ERR, "ME: mbp missing version report\n"); + return; + } + + printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", + vers_name->major_version, vers_name->minor_version, + vers_name->hotfix_version, vers_name->build_version); +} + +static inline void print_cap(const char *name, int state) +{ + printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", + name, state ? " en" : "dis"); +} + +/* Get ME Firmware Capabilities */ +static int mkhi_get_fwcaps(mbp_mefwcaps *cap) +{ + u32 rule_id = 0; + struct me_fwcaps cap_msg; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + }; + + /* Send request and wait for response */ + if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), + &cap_msg, sizeof(cap_msg)) < 0) { + printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); + return -1; + } + *cap = cap_msg.caps_sku; + return 0; +} + +/* Get ME Firmware Capabilities */ +static void me_print_fwcaps(mbp_mefwcaps *cap) +{ + mbp_mefwcaps local_caps; + if (!cap) { + cap = &local_caps; + printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); + if (mkhi_get_fwcaps(cap)) + return; + } + + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); +} + +/* Path that the BIOS should take based on ME state */ +static const char *const me_bios_path_values[] = { + [ME_NORMAL_BIOS_PATH] = "Normal", + [ME_S3WAKE_BIOS_PATH] = "S3 Wake", + [ME_ERROR_BIOS_PATH] = "Error", + [ME_RECOVERY_BIOS_PATH] = "Recovery", + [ME_DISABLE_BIOS_PATH] = "Disable", + [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", +}; + +/* Check whether ME is present and do basic init */ +static void intel_me_init(struct device *dev) +{ + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + me_bios_path path = intel_me_path(dev); + me_bios_payload mbp_data; + + /* Do initial setup and determine the BIOS path */ + printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + + if (path == ME_NORMAL_BIOS_PATH) { + /* Validate the extend register */ + intel_me_extend_valid(dev); + } + + memset(&mbp_data, 0, sizeof(mbp_data)); + + /* + * According to the ME9 BWG, BIOS is required to fetch MBP data in + * all boot flows except S3 Resume. + */ + + /* Prepare MEI MMIO interface */ + if (intel_mei_setup(dev) < 0) + return; + + if (intel_me_read_mbp(&mbp_data, dev)) + return; + + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(mbp_data.fw_version_name); + + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } + } + + /* Set clock enables according to devicetree */ + if (config && config->icc_clock_disable) + me_icc_set_clock_enables(config->icc_clock_disable); + + /* + * Leave the ME unlocked. It will be locked via SMI command later. + */ +} + +static void intel_me_enable(struct device *dev) +{ + /* Avoid talking to the device in S3 path */ + if (acpi_is_wakeup_s3()) { + dev->enabled = 0; + pch_disable_devfn(dev); + } +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = intel_me_enable, + .init = intel_me_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + 0x8c3a, /* Mobile */ + 0x9c3a, /* Low Power */ + 0 +}; + +static const struct pci_driver intel_me __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; + +#endif /* !__SIMPLE_DEVICE__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Gerrit-Change-Number: 42631 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: util/lint: Provide some exemption to common parts of a vendor's MB
by Karthik Ramasubramanian (Code Review) 23 Dec '22

23 Dec '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37807 ) Change subject: util/lint: Provide some exemption to common parts of a vendor's MB ...................................................................... util/lint: Provide some exemption to common parts of a vendor's MB Adding common definitions for a vendor's mainboard(eg. CB:37705) requires creating dummy board_info.txt and Kconfig.name files due to lint checks. Update the lint scripts to provide exemption to common definitions for a vendor's mainboard. BUG=None TEST=Ensure that no lint errors are observed when common definitions are added for a vendor's mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I55c3474c17eacd008fee5f4089da33d4f7d6002a --- M util/lint/lint-stable-005-board-status M util/lint/lint-stable-006-board-name 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37807/1 diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 952a9b5..e8313f2 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -17,6 +17,10 @@ LC_ALL=C export LC_ALL for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do + if [[ ${mobodir} =~ ^src\/mainboard\/.*\/common$ ]]; then + continue + fi + board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" diff --git a/util/lint/lint-stable-006-board-name b/util/lint/lint-stable-006-board-name index b2418a1..cf3b0e2 100755 --- a/util/lint/lint-stable-006-board-name +++ b/util/lint/lint-stable-006-board-name @@ -29,6 +29,9 @@ done for i in src/mainboard/*/*/; do + if [[ ${i} =~ ^src\/mainboard\/.*\/common\/$ ]]; then + continue + fi if [ -r $i/Kconfig ]; then if [ ! -r $i/Kconfig.name ]; then BOARD="$(grep -A2 MAINBOARD_PART_NUMBER $i/Kconfig | tail -1 | cut -f2 -d\")" -- To view, visit https://review.coreboot.org/c/coreboot/+/37807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55c3474c17eacd008fee5f4089da33d4f7d6002a Gerrit-Change-Number: 37807 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: Disable SeaBIOS options unsupported by hardware: scripts to apply the...
by Mike Banon (Code Review) 18 Dec '22

18 Dec '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44638 ) Change subject: Disable SeaBIOS options unsupported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options unsupported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:44636 and CB:44637 to disable SeaBIOS options unsupported by ASUS AM1I-A and ASUS A88XM-E. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/44636 mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware https://review.coreboot.org/c/coreboot/+/44637 mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44638/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..657211e --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./4f95dab.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..87f2bac --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./f4b8121.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./4f95dab.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..8070382 --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +rm -f "./f4b8121.diff" +wget "https://review.coreboot.org/changes/44636/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +rm -f "./4f95dab.diff" +wget "https://review.coreboot.org/changes/44637/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./4f95dab.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..afe90bc --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +1a3aced0e9d3cce8aaeeebf94c035ed028dc4b262d06cce0addc97df85905dc3 ./f4b8121.diff +270e30aa319e0fa9b661b2f7f0aaa6e04e6c6f2fea0fc354160867c4e92bb7a3 ./4f95dab.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/44638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 Gerrit-Change-Number: 44638 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) 29 Nov '22

29 Nov '22

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44637 ) Change subject: mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware ...................................................................... mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware A88XM-E doesn't have any SAS or NVMe controllers and couldn't have a TPM so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ie9760449734499628637e015cacc0541ec0002a2 --- M src/mainboard/asus/a88xm-e/Kconfig A src/mainboard/asus/a88xm-e/config_seabios 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44637/1 diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig index 6874e9e..139f989 100644 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -56,4 +56,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/config_seabios b/src/mainboard/asus/a88xm-e/config_seabios new file mode 100644 index 0000000..03bf0e8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/config_seabios @@ -0,0 +1,7 @@ +### +### SeaBIOS custom configuration for ASUS A88XM-E +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9760449734499628637e015cacc0541ec0002a2 Gerrit-Change-Number: 44637 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44636 ) Change subject: mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware ...................................................................... mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ideec5d8cf3cf4cc7fba0787e56ab38b5172a5314 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44636/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 172d808..ff12d74 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -51,4 +51,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideec5d8cf3cf4cc7fba0787e56ab38b5172a5314 Gerrit-Change-Number: 44636 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneded 'esle'
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33336 Change subject: soc/intel/common/block/pcr: Remove unneded 'esle' ...................................................................... soc/intel/common/block/pcr: Remove unneded 'esle' 'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33336/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 4a35a03..f3971c2 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -394,10 +394,9 @@ break; } return 0; - } else { - printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", - *response); - return -1; } + printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", + *response); + return -1; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Gerrit-Change-Number: 33336 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/Kconfig: Move DRAM section to 'Devices' menu
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32882 Change subject: src/Kconfig: Move DRAM section to 'Devices' menu ...................................................................... src/Kconfig: Move DRAM section to 'Devices' menu This moves DRAM to 'Devices' menu and allow to change default DIMM_MAX value if needed. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig M src/device/Kconfig 2 files changed, 24 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32882/1 diff --git a/src/Kconfig b/src/Kconfig index 2c9dc4a..d30aa99 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1158,31 +1158,6 @@ implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. -config GENERIC_SPD_BIN - bool - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config SPD_READ_BY_WORD - bool - config BOOTBLOCK_CUSTOM # To be selected by arch, SoC or mainboard if it does not want use the normal # src/lib/bootblock.c#main() C entry point. diff --git a/src/device/Kconfig b/src/device/Kconfig index 0539062..d4cacec 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -681,5 +681,29 @@ be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int "Total number of memory DIMM slots" + default 4 + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config SPD_READ_BY_WORD + bool endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Gerrit-Change-Number: 32882 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020