coreboot-gerrit November 2020

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Change in coreboot[master]: force --divide for iPXE default build
by Daniel Maslowski (Code Review) 09 Jun '23

09 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35820 ) Change subject: force --divide for iPXE default build ...................................................................... force --divide for iPXE default build Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35820/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa..7005016 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -72,7 +72,7 @@ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom WORKAROUND_ASFLAGS="--divide" endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) -- To view, visit https://review.coreboot.org/c/coreboot/+/35820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Gerrit-Change-Number: 35820 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Use Broadwell SerialIO implementation
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46969 ) Change subject: sb/intel/lynxpoint: Use Broadwell SerialIO implementation ...................................................................... sb/intel/lynxpoint: Use Broadwell SerialIO implementation Add power state control methods for more devices using helper methods. Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 96 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46969/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 845949c..0e246f7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,28 @@ External (\S6EN) External (\S7EN) +// Put SerialIO device in D0 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) +{ + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + +// Put SerialIO device in D3 state +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) +{ + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing + + // Use Local0 to avoid iasl warning: Method Local is set but never used + Local0 &= Ones +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -193,32 +215,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -273,32 +283,20 @@ } } - // Access to PCI Config in ACPI mode - OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, Preserve) + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) { - Offset (0x84), - PSAT, 32, + SPCS, 32 } - // Put controller in D0 state Method (_PS0, 0, Serialized) { - ^PSAT &= 0xfffffffc - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD0 (RefOf (SPCS)) } - // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - ^PSAT |= 0x00000003 - Local0 = ^PSAT // Read back after writing - - // Use Local0 to avoid iasl warning: Method Local is set but never used - Local0 &= Ones + ^^LPD3 (RefOf (SPCS)) } } @@ -337,6 +335,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SPI1) @@ -386,6 +400,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR0) @@ -435,6 +465,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (UAR1) @@ -472,6 +518,22 @@ Return (0xF) } } + + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (RefOf (SPCS)) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (RefOf (SPCS)) + } } Device (SDIO) -- To view, visit https://review.coreboot.org/c/coreboot/+/46969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a3b896346f6f1e5aa4a1dc45638cbcff01b7dd Gerrit-Change-Number: 46969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46960 ) Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ...................................................................... sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds. Also, add the `ISWP` object (Name or Method) to test for WildcatPoint. Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl 2 files changed, 77 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46960/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc2..134a7cf 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -27,6 +27,25 @@ , 5, HPTE, 1, // Address Enable } + + /* + * Check PCH type + * Return 1 if PCH is WildcatPoint + * Return 0 if PCH is LynxPoint + */ +#if CONFIG(INTEL_LYNXPOINT_LP) + Method (ISWP) + { + Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { + Return (1) + } Else { + Return (0) + } + } +#else + Name (ISWP, 0) +#endif } // High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 2b3d433..203ee3b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -17,6 +17,14 @@ Offset (0x10), , 16, XMEM, 16, // MEM_BASE + Offset (0x40), + , 11, + SWAI, 1, + , 20, + Offset (0x44), + , 12, + SAIP, 2, + , 18, Offset (0x74), D0D3, 2, , 6, @@ -214,25 +222,39 @@ } #if CONFIG(INTEL_LYNXPOINT_LP) - // Clear PCI 0xB0[14:13] - ^MB13 = 0 - ^MB14 = 0 + If (!\ISWP()) { + // Clear PCI 0xB0[14:13] + ^MB13 = 0 + ^MB14 = 0 - // Clear MMIO 0x816C[14,2] - CLK0 = 0 - CLK1 = 0 + // Clear MMIO 0x816C[14,2] + CLK0 = 0 + CLK1 = 0 - // Set MMIO 0x8154[31] - CLK2 = 1 + // Set MMIO 0x8154[31] + CLK2 = 1 - // Handle per-port reset if needed - LPS0 () + // Handle per-port reset if needed + LPS0 () - // Set MMIO 0x80e0[15] - AX15 = 1 + // Set MMIO 0x80e0[15] + AX15 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 + } #else // Set MMIO 0x8154[31] CLK2 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 #endif Return () @@ -273,22 +295,36 @@ } #if CONFIG(INTEL_LYNXPOINT_LP) - // Set PCI 0xB0[14:13] - ^MB13 = 1 - ^MB14 = 1 + If (!\ISWP()) { + // Set PCI 0xB0[14:13] + ^MB13 = 1 + ^MB14 = 1 - // Set MMIO 0x816C[14,2] - CLK0 = 1 - CLK1 = 1 + // Set MMIO 0x816C[14,2] + CLK0 = 1 + CLK1 = 1 - // Clear MMIO 0x8154[31] - CLK2 = 0 + // Clear MMIO 0x8154[31] + CLK2 = 0 - // Clear MMIO 0x80e0[15] - AX15 = 0 + // Clear MMIO 0x80e0[15] + AX15 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 + } #else // Clear MMIO 0x8154[31] CLK2 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 #endif // Put device in D3 -- To view, visit https://review.coreboot.org/c/coreboot/+/46960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Gerrit-Change-Number: 46960 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46973 ) Change subject: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices ...................................................................... soc/intel/broadwell: Add ACPI CIDs for SerialIO devices Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46973/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 2bacd2b..1e6dbac 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -166,6 +166,7 @@ // LynxPoint-LP Return ("INT33C2") } + Name (_CID, "INT33C2") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -242,6 +243,7 @@ // LynxPoint-LP Return ("INT33C3") } + Name (_CID, "INT33C3") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -318,6 +320,7 @@ // LynxPoint-LP Return ("INT33C0") } + Name (_CID, "INT33C0") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -379,6 +382,7 @@ // LynxPoint-LP Return ("INT33C1") } + Name (_CID, "INT33C1") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -452,6 +456,7 @@ // LynxPoint-LP Return ("INT33C4") } + Name (_CID, "INT33C4") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -525,6 +530,7 @@ // LynxPoint-LP Return ("INT33C5") } + Name (_CID, "INT33C5") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/46973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Gerrit-Change-Number: 46973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47046 ) Change subject: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order ...................................................................... sb/intel/lynxpoint/lpc.c: Follow Broadwell's order Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47046/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1845273..d1780fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -190,7 +190,6 @@ u16 reg16; u32 reg32; const char *state; - u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -232,26 +231,6 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute @@ -275,6 +254,11 @@ /* SMI setup based on device tree configuration */ enable_alt_smi(config->alt_gp_smi_en); } +} + +static void pch_misc_init(struct device *dev) +{ + u16 pmbase = get_pmbase(); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT @@ -282,12 +266,40 @@ reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); + + /* Enable BIOS updates outside of SMM */ + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + /* Clear magic status bits to prevent unexpected wake */ RCBA32_OR(0x3310, (1 << 4) | (1 << 5) | (1 << 0)); reg16 = RCBA16(0x3f02); reg16 &= ~0xf; RCBA16(0x3f02) = reg16; + + pch_enable_serial_irqs(dev); } /* LynxPoint PCH Power Management init */ @@ -461,18 +473,8 @@ apm_control(APM_CNT_ACPI_DISABLE); } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - /* * Enable DMI ASPM in the PCH */ @@ -488,14 +490,14 @@ /* IO APIC initialization. */ pch_enable_ioapic(dev); - pch_enable_serial_irqs(dev); - /* Setup the PIRQ. */ pch_pirq_init(dev); /* Setup power options. */ pch_power_options(dev); + pch_misc_init(dev); + /* Initialize power management */ if (pch_is_lp()) { lpt_lp_pm_init(dev); @@ -519,8 +521,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/47046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Gerrit-Change-Number: 47046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47029 ) Change subject: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps ...................................................................... soc/intel/broadwell/pch/sata.c: Add missing SATA init steps WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Keep the BWG comments for now, since both platforms will be merged soon. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47029/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 91c2ff5..e9d70f1 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -95,6 +95,15 @@ /* Setup register 98h */ reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Gerrit-Change-Number: 47029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Extend criteria to determine CSE fimrware update
by Sridhar Siricilla (Code Review) 09 Jun '23

09 Jun '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46553 ) Change subject: soc/intel/common: Extend criteria to determine CSE fimrware update ...................................................................... soc/intel/common: Extend criteria to determine CSE fimrware update The patch extends criteria to determine the CSE Firmware Update. As part of exended criteria, coreboot checks for IFWI Build Version field besides CSE RW partition signature corruption and CSE RW version. Having this additional check to help coreboot to trigger CSE Fimrware update when there is no change in CSE firmware but in other components like TCSS etc. TEST=Verified on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I129a6461e2f53259560c0e5d7d3b2fb85c8b3238 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 38 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46553/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a7bb757..77a8d5f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -173,7 +173,7 @@ /* CSE CBFS RW version */ struct fw_version fw_ver; - uint8_t reserved1[4]; + uint32_t ifwi_build_ver; /* * CSE RW blob needs to be moved outside of FW_MAIN_A and FW_MAIN_B to reduce the boot * time. When the RW blob is placed outside of FW_MAIN_A and FW_MAIN_B, coreboot needs @@ -186,6 +186,22 @@ uint8_t reserved2[4]; }; +/* CSE Boot Partition Descriptor Table Header */ +struct cse_bpdt { + + /* Signature:0x000055AA is expected for a valid BP */ + uint32_t signature; + + /* reserved field */ + uint8_t reserved[8]; + + /* ifwi build version */ + uint32_t ifwi_build_ver; + + /* FIT tool version */ + struct fw_version fit_tool_ver; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -592,6 +608,9 @@ source_info->fw_ver.hotfix, source_info->fw_ver.build); + printk(BIOS_SPEW, "cse_lite: IFWI build version: %u\n", + source_info->ifwi_build_ver); + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW's hash: "); for (uint8_t i = 0; i < VB2_SHA256_DIGEST_SIZE; i++) @@ -630,6 +649,22 @@ return source_info->fw_ver.build - cse_rw_ver->build; } +static bool cse_is_ifwi_build_version_latest(const struct cse_cbfs_rw_info *source_info, + const struct region_device *target_dev) +{ + uint32_t ifwi_build_ver; + uint8_t ifwi_build_ver_offset = offsetof(struct cse_bpdt, ifwi_build_ver); + + if (rdev_readat(target_dev, &ifwi_build_ver, ifwi_build_ver_offset, + sizeof(ifwi_build_ver)) != sizeof(ifwi_build_ver)) { + printk(BIOS_ERR, "cse_lite: Failed to read IFWI build version from" + "CSE RW partition\n"); + return false; + } + + return (ifwi_build_ver == source_info->ifwi_build_ver); +} + /* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ static bool cse_verify_cbfs_rw_sha256(const uint8_t *expected_rw_blob_sha, const void *rw_blob, const size_t rw_blob_sz) @@ -719,7 +754,8 @@ const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_info)); + !cse_is_rw_version_latest(cse_bp_info, source_info) || + !cse_is_ifwi_build_version_latest(source_info, target_rdev)); } static bool cse_write_rw_region(const struct region_device *target_rdev, -- To view, visit https://review.coreboot.org/c/coreboot/+/46553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I129a6461e2f53259560c0e5d7d3b2fb85c8b3238 Gerrit-Change-Number: 46553 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/sandybridge: Improve channel disable logic
by Angel Pons (Code Review) 09 Jun '23

09 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45500 ) Change subject: nb/intel/sandybridge: Improve channel disable logic ...................................................................... nb/intel/sandybridge: Improve channel disable logic Do not consider the failed channel's SPDs in emergency mode. Also, force a full training if not resuming from S3 and the saved data indicates a channel has failed. Special care needs to be taken as the selected memory frequency could be raised after a channel has been disabled. Tested on Asus P8Z77-V LX2, with a good DIMM on channel 0 and a bad DIMM on channel 1. The failing channel causes errors when discovering timB, and emergency mode raminit for the other channel is good enough to boot. With this commit: a. Regular boots always result in full training. b. The board still boots, as emergency raminit trained the good DIMM. c. S3 resume still works in all tested configurations. d. If pretending the bad DIMM is slower: 1. The MPLL gets locked at the slow frequency of the bad DIMM. 2. The first raminit attempt still fails miserably on the bad DIMM. 3. Emergency mode uses the frequency the MPLL is locked at. 4. The board boots with the good DIMM running at the slow frequency. With good DIMMs on both channels, everything works the same as before. Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 38 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45500/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 319fea3..51c57c6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -43,15 +43,7 @@ /* Disable a channel in ramctr_timing */ static void disable_channel(ramctr_timing *ctrl, int channel) { - ctrl->rankmap[channel] = 0; - - memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); - - ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); - memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); + ctrl->failed_channels |= BIT(channel); } static bool nb_supports_ecc(const uint32_t capid0_a) @@ -163,6 +155,10 @@ FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; + /* Skip decoding the SPDs of failed channels */ + if (ctrl->failed_channels & BIT(channel)) + continue; + ch_dimms = 0; /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { @@ -345,8 +341,21 @@ system_reset(); } + /* + * Discard the saved data if it is from raminit emergency mode. + * Ideally, we would not advertise support for ACPI S3 in such + * cases, because there is evidence that the RAM has stability + * problems. Until then, skip this sanity check on S3 resumes. + */ + if (!s3resume && ctrl_cached && ctrl_cached->failed_channels) { + printk(BIOS_ERR, "Stored timings indicate channels have failed.\n"); + + ctrl_cached = NULL; + } + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { + /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); mainboard_get_spd(spds, 1); @@ -391,6 +400,13 @@ } if (err) { + /* + * We can't reinitialize the DRAM MPLL at a different frequency. + * As we want to ignore the SPDs on the failed channel, we have + * to use the same tCK in emergency mode to avoid some troubles. + */ + const u32 old_tCK = ctrl.tCK; + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -398,12 +414,15 @@ /* Reset internal state */ reinit_ctrl(&ctrl, cpuid); - /* Reset DDR3 frequency */ - dram_find_spds_ddr3(spds, &ctrl); - /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + /* Restore tCK */ + ctrl.tCK = old_tCK; + + /* Recalculate DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 32f2b44..cf3d6a9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -105,7 +105,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 typedef struct odtmap_st { u16 rttwr; @@ -185,6 +185,9 @@ /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ u16 mdll_wake_delay; + /* Bitmap of channels that have failed */ + u8 failed_channels; + u8 rankmap[NUM_CHANNELS]; int ref_card_offset[NUM_CHANNELS]; u32 mad_dimm[NUM_CHANNELS]; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c23a5ac..a469910 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -265,7 +265,9 @@ printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); - ctrl->tCK = get_mem_min_tck(); + /* In emergency mode, use provided tCK if non-zero. Otherwise, calculate it. */ + if (!ctrl->failed_channels || !ctrl->tCK) + ctrl->tCK = get_mem_min_tck(); /* Find CAS latency */ while (1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Gerrit-Change-Number: 45500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Add device settings
by Tim Chen (Code Review) 09 Jun '23

09 Jun '23

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47013 to review the following change. Change subject: mb/google/dedede/var/metaknight: Add device settings ...................................................................... mb/google/dedede/var/metaknight: Add device settings Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan, Raydium and Goodix touchscreen setting 3. Add user/world facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration 6. Add DPTF setting BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ie034724ea5c6edff6cdba694605d3238f66be910 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 175 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47013/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 404024b..af7de71 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -1,5 +1,9 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -11,7 +15,7 @@ #| I2C0 | Trackpad | #| I2C1 | Digitizer | #| I2C2 | Touchscreen | - #| I2C3 | Camera | + #| I2C3 | TBD | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -36,7 +40,176 @@ }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on - device pci 15.0 on end + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie034724ea5c6edff6cdba694605d3238f66be910 Gerrit-Change-Number: 47013 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/...
by Kevin Cody-Little (Code Review) 09 Jun '23

09 Jun '23

Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38207 ) Change subject: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. ...................................................................... Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Signed-off-by: Kevin Cody <kcodyjr(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/soc/intel/skylake/Kconfig 13 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38207/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..165c440 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -16,6 +16,7 @@ select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 3261661..2dabb2b 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b38..34a0368 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index cafb855..9abf2bc 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -26,6 +26,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SPD_READ_BY_WORD + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index bc0c67b..e8f3e3e 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 5a621bb..b2f28fa 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index afc510f..cd5f8a2 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d7706d1..6bad7c8 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 315104e..f985cde 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -30,6 +30,7 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a..cfef895 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -11,6 +11,7 @@ select SPD_READ_BY_WORD select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_PURISM_BASEBOARD_LIBREM_SKL diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 903d7ba..4aa6669 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -16,6 +16,7 @@ select HAVE_ACPI_TABLES select ADD_FSP_BINARIES select FSP_USE_REPO + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 5a99f7a..27b4e44 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d90fb6b..ab944b6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -57,7 +57,6 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/38207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Gerrit-Change-Number: 38207 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020