Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47429 )


Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................

nb/intel/sandybridge: Clarify RAM overclock options

Rewrite them to more accurately describe what they are about.

Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <[e-mail]>
---
M src/northbridge/intel/sandybridge/Kconfig
1 file changed, 7 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47429/1

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index ef6dc3d..b4834cd 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -44,19 +44,19 @@
 	  System Agent/MRC.bin. You should answer Y.
 
 config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
-	bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
+	bool "[OVERCLOCKING] Ignore CAPID fuses that limit max. DRAM frequency"
 	default n
 	depends on USE_NATIVE_RAMINIT
 	help
-	  Ignore the mainboard's vendor programmed fuses that might limit the
-	  maximum DRAM frequency. By selecting this option the fuses will be
-	  ignored and the only limits on DRAM frequency are set by RAM's SPD and
-	  hard fuses in southbridge's clockgen.
-	  Disabled by default as it might causes system instability.
+	  Ignore the CAPID fuses and devicetree settings that might limit the
+	  maximum DRAM frequency on overclocking-capable parts. By selecting
+	  this option, the fuse values will be ignored and the only limits on
+	  DRAM frequency are determined by SPD values and hard limits in the
+	  northbridge's MPLL. Disabled by default as it can cause instability.
 	  Handle with care!
 
 config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
-	bool "Ignore XMP profile max DIMMs per channel"
+	bool "[OVERCLOCKING] Ignore XMP profile max DIMMs per channel"
 	default n
 	depends on USE_NATIVE_RAMINIT
 	help

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[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429 )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 1:

I don't like the brackets in the name. But having those options in a overclocking submenu seems to make sense.


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[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429 )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 1: Code-Review+1


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[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429 )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 1:
> Patch Set 1:
>
> I don't like the brackets in the name. But having those options in a overclocking submenu seems to make sense.

Good idea


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[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429 )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47429/1/src/northbridge/intel/sandy... 
File src/northbridge/intel/sandybridge/Kconfig:

https://review.coreboot.org/c/coreboot/+/47429/1/src/northbridge/intel/sandy... 
PS1, Line 51: and devicetree settings 
false



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[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


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[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Angel Pons (Code Review)]

Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Restored
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[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Angel Pons (Code Review)]

Attention is currently required from: Angel Pons, Paul Menzel.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 2:

(1 comment)

File src/northbridge/intel/sandybridge/Kconfig:

https://review.coreboot.org/c/coreboot/+/47429/comment/e40cb208_13ce781d :
PS1, Line 51: and devicetree settings
> false
> unfalsed, also rewrote a bunch of stuff.

[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Martin L Roth (Code Review)]

Attention is currently required from: Angel Pons, Paul Menzel.

Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 3: Code-Review+2

(1 comment)

Patchset:

PS3: 
This can be moved into an overclocking submenu in a follow-on patch if desired.



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[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................

nb/intel/sandybridge: Clarify RAM overclock options

Rewrite them to more accurately describe what they are about.

Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <[e-mail]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47429
Tested-by: build bot (Jenkins) <[e-mail]>
Reviewed-by: Martin L Roth <[e-mail]>
---
M src/northbridge/intel/sandybridge/Kconfig
1 file changed, 18 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved




diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 01aa11c..b7738a2 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -47,25 +47,32 @@
 	  System Agent/MRC.bin. You should answer Y.
 
 config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
-	bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
+	bool "[OVERCLOCK] Ignore CAPID fuses that limit max DRAM frequency"
 	default n
 	depends on USE_NATIVE_RAMINIT
 	help
-	  Ignore the mainboard's vendor programmed fuses that might limit the
-	  maximum DRAM frequency. By selecting this option the fuses will be
-	  ignored and the only limits on DRAM frequency are set by RAM's SPD and
-	  hard fuses in southbridge's clockgen.
-	  Disabled by default as it might causes system instability.
-	  Handle with care!
+	  Ignore the CAPID fuses that might limit the maximum DRAM frequency
+	  on overclocking-capable parts. By selecting this option, the fuse
+	  values will be ignored and the only limits on DRAM frequency are
+	  determined by SPD values, per-board devicetree settings and hard
+	  limits in the northbridge's MPLL. Disabled by default as it can
+	  cause instability.
+	  Consider this to be an overclocking option. Handle with care!
 
 config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
-	bool "Ignore XMP profile max DIMMs per channel"
+	bool "[OVERCLOCK] Ignore XMP max DIMMs per channel"
 	default n
 	depends on USE_NATIVE_RAMINIT
 	help
-	  Ignore the max DIMMs per channel restriciton defined in XMP profiles.
-	  Disabled by default as it might cause system instability.
-	  Handle with care!
+	  The more DIMMs are in a channel, the more signal integrity worsens.
+	  Because of this, some DIMMs only support running at XMP timings if
+	  the number of DIMMs in the channel is below a limit. This limit is
+	  usually 1, i.e. there must be no other DIMMs in the channel to use
+	  XMP timings. Otherwise, non-XMP timings are used.
+	  When this option is enabled, the max DIMMs per channel restriction
+	  in XMP is ignored. Depending on available margins, this could work
+	  but it can also result in system instability.
+	  Consider this to be an overclocking option. Handle with care!
 
 config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
 	bool "Ignore XMP profile requested voltage"

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[S] Change in coreboot[master]: nb/intel/sandybridge: Clarify RAM overclock options

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47429?usp=email )

Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................


Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 1 / 7
     
FAIL: x86_32  "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG 
     and payload TianoCore : https://lava.9esec.io/r/178592
PASS: x86_32  "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG 
     and payload SeaBIOS : https://lava.9esec.io/r/178591
PASS: x86_32  "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 
     and payload SeaBIOS : https://lava.9esec.io/r/178589
PASS: x86_64  "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 
     and payload SeaBIOS : https://lava.9esec.io/r/178588
PASS: x86_32  "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN 
     and payload SeaBIOS : https://lava.9esec.io/r/178587
PASS: x86_32  "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ 
     and payload SeaBIOS : https://lava.9esec.io/r/178586
PASS: x86_32  "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX 
     and payload SeaBIOS : https://lava.9esec.io/r/178585

Please note: This test is under development and might not be accurate at all!


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