coreboot-gerrit November 2020

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Change in coreboot[master]: mb/asus/f2a85-m_pro: Add HA verbs
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46668 ) Change subject: mb/asus/f2a85-m_pro: Add HA verbs ...................................................................... mb/asus/f2a85-m_pro: Add HA verbs Copy the values `/sys/class/sound/hwC1D0/init_pin_configs` with vendor firmware 6601 Linux 5.8.14. The values are the same as for the Asus F2A85-M, but the codec is ALC892. Change-Id: I3adb1e5d2cde0557b96dfa88c58262dc22f1f1c8 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/BiosCallOuts.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46668/1 diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index a426f01..8068686 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -63,9 +63,28 @@ }; #endif +const CODEC_ENTRY f2a85_m_pro_alc892_VerbTbl[] = { + {0x11, 0x99430140}, + {0x12, 0x411111f0}, + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01a19850}, + {0x19, 0x02a19c60}, + {0x1a, 0x0181305f}, + {0x1b, 0x02214c20}, + {0x1c, 0x411111f0}, + {0x1d, 0x4005e601}, + {0x1e, 0x01456130}, + {0x1f, 0x411111f0}, + {0xff, 0xffffffff} +}; + static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]}, + {0x10ec0892, (CODEC_ENTRY*)&f2a85_m_pro_alc892_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3adb1e5d2cde0557b96dfa88c58262dc22f1f1c8 Gerrit-Change-Number: 46668 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/mainboard/dedede: support touchpad for Boten
by Yan Liu (Code Review) 10 Jun '23

10 Jun '23

Yan Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43175 ) Change subject: mb/mainboard/dedede: support touchpad for Boten ...................................................................... mb/mainboard/dedede: support touchpad for Boten Add device tree for touchpad BUG=b:160664447 BRANCH=NONE TEST=build bios and verify touchpad function for boten Signed-off-by: Yan Liu <yan.liu(a)bitland.corp-partner.google.com> Change-Id: Ib0c692bd7f997e9a90de646b807c6c1b37a834d2 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 167 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/43175/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 1e75864..fea72ef 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -35,5 +35,171 @@ .speed = I2C_SPEED_FAST, }, }" - device domain 0 on end + + # USB Port Configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # IPU + device pci 09.0 off end # Intel Trace Hub + device pci 12.6 off end # GSPI 2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + device usb 2.4 off end + end + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + device pci 15.1 on end # I2C 1 + device pci 15.2 on end # I2C 2 + device pci 15.3 on end # I2C 3 + device pci 16.0 on end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 off end # SATA + device pci 19.0 on end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 on end # UART 2 + device pci 1a.0 on end # eMMC + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + # External PCIe port 4 is mapped to PCIe Root port 8 + device pci 1c.7 on end # PCI Express Root Port 8 - WLAN + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" + device spi 0 on end + end + end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.4 off end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + end + end -- To view, visit https://review.coreboot.org/c/coreboot/+/43175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c692bd7f997e9a90de646b807c6c1b37a834d2 Gerrit-Change-Number: 43175 Gerrit-PatchSet: 1 Gerrit-Owner: Yan Liu <yan.liu(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

10 31

Change in coreboot[master]: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44431 to review the following change. Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ...................................................................... mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44431/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..9ccc5e0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -63,6 +63,9 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" + # PCIe RP PTM + register "PciePtm[8]" = "0x0"; + register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..496f837 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -52,6 +52,9 @@ register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[10]" = "1" + # PCIe PTM for Root Port 9 + register "PciePtm[8]" = "0" + # Hybrid storage mode register "HybridStorageMode" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 812dbac..3cadcf0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -174,6 +174,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe Precision Time Measurement for Root Ports */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9..8a72573 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -172,6 +172,7 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = config->PciePtm[i]; } /* Enable ClkReqDetect for enabled port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Gerrit-Change-Number: 44431 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TEST] Revert "mb/google/dedede/variants/drawcia: Update TSR1 passive...
by Sumeet R Pawnikar (Code Review) 10 Jun '23

10 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46838 ) Change subject: [TEST] Revert "mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature" ...................................................................... [TEST] Revert "mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature" This reverts commit b5e4e3441841d8d1b7fac1240b7c73d288df66d5 Due to TSR1 passive threshold set to 51C which seems very low. This is impacting the performance on the system as per this reported bug. BUG=b:170229672 BRANCH=None TEST=Built and tested on dedede system Change-Id: Ie87bb0a4b6c71f21ac7a83029be2bb6d83e62793 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46838/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 5942121..0c69d4b 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -92,7 +92,7 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) }" -- To view, visit https://review.coreboot.org/c/coreboot/+/46838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87bb0a4b6c71f21ac7a83029be2bb6d83e62793 Gerrit-Change-Number: 46838 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [WIP] Add Multiple Segment support
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40722 ) Change subject: [WIP] Add Multiple Segment support ...................................................................... [WIP] Add Multiple Segment support Test Patch for get feedback on design aspect Change-Id: Ide7e97aa7c48fd0e993b248b38b2ad6ad94a21cb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c A src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl A src/soc/intel/common/block/acpi/acpi/pcisegment.asl M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c A src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/systemagent.c 19 files changed, 195 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40722/1 diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index af13d9f..c531baa 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -28,6 +28,9 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } + #if CONFIG_SA_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> + #endif } #if CONFIG(CHROMEOS) diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index a1b6b4d..a15200b 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -31,7 +31,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, }; diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 1ab365e..9d7e40e 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -20,7 +20,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..9b0457f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -35,10 +35,13 @@ __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { - /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ - current += acpi_create_mcfg_mmconfig((void *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; } diff --git a/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl new file mode 100644 index 0000000..77c0248 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + }) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ + Store (\_SB.PCI0.MCHC.TLUD, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) + } + + Return (MCRS) +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcisegment.asl b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl new file mode 100644 index 0000000..4efaf20 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcisegment.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +Device (PCI1) +{ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, 1) // _SEG: PCI Segment + Name (_UID, 1) // _UID: Unique ID + Name (_ADR, 0x00000000) + + Name (PICN, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + }) + + Name (PICP, Package () { + /* SEG1: PCIe Root Port*/ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + }) + + Method (_PRT) + { + If (PICM) { + Return (PICP) + } Else { + Return (PICN) + } + } + #include "extrahostbridge.asl" +} diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index c6aa4b4..cfa96e3 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -4,11 +4,14 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H +#include <commonlib/helpers.h> #include <device/device.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <stddef.h> +#define PCIEXBAR_LENGTH_MiB(x) (x * 256 * MiB) + /* Device 0:0.0 PCI configuration space */ #define MCHBAR 0x48 #define PCIEXBAR 0x60 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 6dd1f3b..759abc9 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -9,23 +9,18 @@ hex default 0xe0000000 -config SA_PCIEX_LENGTH +config SA_PCI_SEGMENT_GROUPS hex - default 0x10000000 if (PCIEX_LENGTH_256MB) - default 0x8000000 if (PCIEX_LENGTH_128MB) - default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 + default 1 + default 2 if TCSS_PCIE_SEGMENT help - This option allows you to select length of PCIEX region. + This option allows you to select required PCI segment. -config PCIEX_LENGTH_256MB - bool - -config PCIEX_LENGTH_128MB - bool - -config PCIEX_LENGTH_64MB - bool + Each PCI segment supports up to 256 buses (0-255). + PCIE length selection is depends on PCI_SEGMENT_GROUPS. + Formula for PCIE Length = PCI_SEGMENT_GROUPS * 256 MB + If PCI segment is 1 then length of PCIEX region is 256MB to support 256 buses + else PCIEX region would be multiple of 256MB based on PCI_SEGMENT_GROUPS. config SA_ENABLE_IMR bool diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 03f4de4..ef2f7b4 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -4,7 +4,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H - /* Device 0:0.0 PCI configuration space */ /* GMCH Graphics Control Register */ @@ -19,8 +18,10 @@ #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 -#define PCIEXBAR_LENGTH_64MB 2 -#define PCIEXBAR_LENGTH_128MB 1 +#define PCIEXBAR_LENGTH_4096MB 6 +#define PCIEXBAR_LENGTH_2048MB 5 +#define PCIEXBAR_LENGTH_1024MB 4 +#define PCIEXBAR_LENGTH_512MB 3 #define PCIEXBAR_LENGTH_256MB 0 #define PCIEXBAR_PCIEXBAREN (1 << 0) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index cb0ed34..69b36f8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -27,15 +27,21 @@ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); /* Get PCI Express Region Length */ - switch (CONFIG_SA_PCIEX_LENGTH) { - case 256 * MiB: + switch (CONFIG_SA_PCI_SEGMENT_GROUPS) { + case 1: pciexbar_length = PCIEXBAR_LENGTH_256MB; break; - case 128 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_128MB; + case 2: + pciexbar_length = PCIEXBAR_LENGTH_512MB; break; - case 64 * MiB: - pciexbar_length = PCIEXBAR_LENGTH_64MB; + case 4: + pciexbar_length = PCIEXBAR_LENGTH_1024MB; + break; + case 8: + pciexbar_length = PCIEXBAR_LENGTH_2048MB; + break; + case 16: + pciexbar_length = PCIEXBAR_LENGTH_4096MB; break; default: pciexbar_length = PCIEXBAR_LENGTH_256MB; diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig new file mode 100644 index 0000000..0f7fe7c --- /dev/null +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_TCSS + bool + help + Intel Processor common TCSS support + +config TCSS_PCIE_SEGMENT + bool + help + Indicate the extra PCIE segment is required for iTBT or not diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index c07fd0a..6cf6354 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -16,7 +16,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 7be471a..4c5efe7 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -17,7 +17,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 75f6b69..5d95029 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -200,9 +200,13 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); + /* + * PCI Segment Group depends on CONFIG_SA_PCI_SEGMENT_GROUPS, + * Start Bus Number 0, End Bus Number is 255 + */ + for (int i = 0; i < CONFIG_SA_PCI_SEGMENT_GROUPS; i++) + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, i, 0, 255); return current; } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 9a4c4de..a71dbb2 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -31,7 +31,8 @@ struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@ #define ISH_IRQ 16 -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16 diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 8859386..a6d7ae8 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -23,7 +23,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, + PCIEXBAR_LENGTH_MiB(CONFIG_SA_PCI_SEGMENT_GROUPS), "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7e97aa7c48fd0e993b248b38b2ad6ad94a21cb Gerrit-Change-Number: 40722 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/kontron/986lcd-m: Use `winbond_enable_serial()`
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39125 ) Change subject: mb/kontron/986lcd-m: Use `winbond_enable_serial()` ...................................................................... mb/kontron/986lcd-m: Use `winbond_enable_serial()` Note, the common function does not set the IRQ. pnp_set_irq(dev, PNP_IDX_IRQ0, 4); Change-Id: Ia437aa31ae92a299d0d0b35db15715997ee9bad3 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/kontron/986lcd-m/early_init.c 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39125/1 diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 827f792..467d907 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -52,19 +52,15 @@ pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ + pnp_exit_conf_state(dev); + dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); + winbond_enable_serial(dev, 0x3f8); dev = PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - pnp_set_enable(dev, 1); + winbond_enable_serial(dev, 0x2f8); + + pnp_enter_conf_state(dev); dev = PNP_DEV(0x2e, W83627THG_KBC); pnp_set_logical_device(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/39125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia437aa31ae92a299d0d0b35db15715997ee9bad3 Gerrit-Change-Number: 39125 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: [WIP] mb/amd/mandolin: add missing PCIe devices to devicetree
by Felix Held (Code Review) 10 Jun '23

10 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46138 ) Change subject: [WIP] mb/amd/mandolin: add missing PCIe devices to devicetree ...................................................................... [WIP] mb/amd/mandolin: add missing PCIe devices to devicetree Haven't verified if this behaves correctly for Dali chips. Change-Id: I8b0f590eab086b6b85219b739741c0f1ca25aeac Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46138/1 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 3de5812..8d63ebe 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -143,7 +143,12 @@ device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to GPU PCIe slot + device pci 1.2 on end # Bridge to WIFI M.2 slot device pci 1.3 on end # Bridge to PCIe Ethernet chip + device pci 1.4 on end # Bridge to WWAN M.2 slot; not available on Dali + device pci 1.5 on end # Bridge to second WIFI M.2 slot; not available on Dali + device pci 1.7 on end # Bridge to NVME M.2 slot device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU -- To view, visit https://review.coreboot.org/c/coreboot/+/46138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0f590eab086b6b85219b739741c0f1ca25aeac Gerrit-Change-Number: 46138 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig
by Felix Held (Code Review) 10 Jun '23

10 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46139 ) Change subject: [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig ...................................................................... [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig Haven't verified this, since I currently don't have PCIe devices to test against; all devices I have here to test against won't work without reworking the board, since the EC that controls the rest on those connectors has no coreboot driver to deassert the reset lines. Change-Id: Ib94e165c0ba1d16f6df9bb3cf95f0eb5067a3b82 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46139/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8e2bd8b..be1c2bc 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -13,6 +13,10 @@ select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config FMDFILE string -- To view, visit https://review.coreboot.org/c/coreboot/+/46139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94e165c0ba1d16f6df9bb3cf95f0eb5067a3b82 Gerrit-Change-Number: 46139 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: cpu/x86: Select proper SMM save Kconfig option
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45473 ) Change subject: cpu/x86: Select proper SMM save Kconfig option ...................................................................... cpu/x86: Select proper SMM save Kconfig option Note: Qemu always uses AMD64 save states but messes up the revision if the CPU is set to be a 32bit-only one the save state revision is 0 but still uses the AMD64 one. This is currently not handled by coreboot. Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 30 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45473/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..538fb6c 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507e..0aa3183 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_PI diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 18fc392..1242dd7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -21,6 +21,7 @@ select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 0a29d69..b29d426 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,3 +12,4 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 095fee5..44d9805 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -14,6 +14,8 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..de3e835 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..abb8eba 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 0c92479..50c64b9 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -8,3 +8,5 @@ select SMM_ASEG select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index fbb00fa..60eeac7 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -7,3 +7,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 9398d18..91adff9 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -5,3 +5,4 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 2b6deb6..720ce11 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -17,6 +17,7 @@ select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE + select X86_LEGACY_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72..9c5f292 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -9,6 +9,7 @@ select MMX select SSE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 638653c..b903fdf 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -3,6 +3,7 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_SOCKET_BGA956 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8db932c..2c2141c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,6 +14,7 @@ select MMX select SSE select SIPI_VECTOR_IN_ROM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 8b1f5ed..0ca7c99 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -9,6 +9,8 @@ select CPU_INTEL_MODEL_6FX select MMX select SSE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 176ae9e..8911a8d 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -13,6 +13,7 @@ select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 06ac685..6aa081b 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -13,6 +13,7 @@ select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..19fb1d3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_CHROMEOS + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..7e28e27 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -58,6 +58,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..59f6a66 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -48,6 +48,7 @@ select SSE2 select RTC select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f837a2e..817c3e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -105,6 +105,7 @@ select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select X86_EM64T100_SAVE_STATE config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..a74f243 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select X86_EM64T100_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..2e7d32e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -44,6 +44,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + select X86_EM64T100_SAVE_STATE config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..7b0a0bd 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,7 @@ select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select X86_EM64T101_SAVE_STATE config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..981ac69 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -113,6 +113,7 @@ select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE + select X86_EM64T101_SAVE_STATE config MAX_CPUS int diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3fce223..202704a8 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -40,6 +40,7 @@ select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T100_SAVE_STATE config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1230675..bc4c44c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -61,6 +61,7 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index f2922f5..2f23c5f 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..338a5be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -79,6 +79,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select X86_EM64T101_SAVE_STATE config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2659357..beb87ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/45473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Gerrit-Change-Number: 45473 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci: Don't enabled unassigned resources
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41553 to review the following change. Change subject: device/pci: Don't enabled unassigned resources ...................................................................... device/pci: Don't enabled unassigned resources We only have a single bit in the PCI_COMMAND register to enable or disable resources of one type. If any resource of a type is unassigned, we have to disable all of them. Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/pci_device.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/41553/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5afbfa9..8df44df 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -506,7 +506,8 @@ } } -static void pci_set_resource(struct device *dev, struct resource *resource) +static void pci_set_resource(struct device *const dev, struct resource *const resource, + uint16_t *const command_mask) { /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -518,6 +519,11 @@ printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " "assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); + /* We'll have to disable all resources of this type. */ + if (resource->flags & IORESOURCE_MEM) + *command_mask &= ~PCI_COMMAND_MEMORY; + if (resource->flags & IORESOURCE_IO) + *command_mask &= ~PCI_COMMAND_IO; return; } } @@ -561,12 +567,16 @@ void pci_dev_set_resources(struct device *dev) { + uint16_t command_mask = 0xffff; struct resource *res; struct bus *bus; u8 line; for (res = dev->resource_list; res; res = res->next) - pci_set_resource(dev, res); + pci_set_resource(dev, res, &command_mask); + /* If there are unassigned resources, we might + have to disable others of the same type. */ + dev->command &= command_mask; for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) -- To view, visit https://review.coreboot.org/c/coreboot/+/41553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Gerrit-Change-Number: 41553 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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