coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37317 ) Change subject: mb: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb: Add unaligned flag (%) sections that don't need alignment Fix all FMD files with unaligned sections. Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd M src/mainboard/lenovo/t400/vboot-rwa.fmd M src/mainboard/lenovo/t410/vboot-rwa.fmd M src/mainboard/lenovo/t420/vboot-rwa.fmd M src/mainboard/lenovo/t420s/vboot-rwa.fmd M src/mainboard/lenovo/t520/vboot-rwa.fmd M src/mainboard/lenovo/x200/vboot-rwa.fmd M src/mainboard/lenovo/x201/vboot-rwa.fmd M src/mainboard/lenovo/x220/vboot-rwa.fmd M src/mainboard/opencellular/elgon/vboot.fmd M src/mainboard/samsung/lumpy/chromeos.fmd M src/mainboard/samsung/stumpy/chromeos.fmd M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd M src/mainboard/up/squared/vboot-ro.fmd M src/mainboard/up/squared/vboot-roa.fmd M src/mainboard/up/squared/vboot-roab.fmd 19 files changed, 104 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37317/1 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd index 0d2c9da..fb8960b 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -2,15 +2,15 @@ SI_BIOS 0x1000000 { RW_SECTION_A 0x7c0000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) 0x74ffc0 - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% 0x74ffc0 + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t400/vboot-rwa.fmd b/src/mainboard/lenovo/t400/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/t400/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t400/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/t410/vboot-rwa.fmd b/src/mainboard/lenovo/t410/vboot-rwa.fmd index 8f50d33..885aa0d 100644 --- a/src/mainboard/lenovo/t410/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t410/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -20,9 +20,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION 0x11e000 { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/t520/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/lenovo/x200/vboot-rwa.fmd b/src/mainboard/lenovo/x200/vboot-rwa.fmd index 4af3fcd..9112721 100644 --- a/src/mainboard/lenovo/x200/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x200/vboot-rwa.fmd @@ -8,16 +8,16 @@ SI_BIOS@0x600000 0x200000 { RW_SECTION_A 0x100000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } RW_VPD(PRESERVE) 0x1000 CONSOLE 0x10000 SMMSTORE(PRESERVE) 0x40000 WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 RO_VPD(PRESERVE) 0x1000 GBB 0x1e000 COREBOOT(CBFS) diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd index 0d1aa5d..dc035e9 100644 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A 0x180000 { VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + FW_MAIN_A(CBFS)% + RW_FWID_A% 0x40 } UNIFIED_MRC_CACHE 0x20000 { RECOVERY_MRC_CACHE 0x10000 @@ -19,9 +19,9 @@ WP_RO { RO_VPD(PRESERVE) 0x1000 RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_PADDING% 0x7c0 GBB 0x1e000 COREBOOT(CBFS) } diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..0f3fe32 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -7,8 +7,8 @@ SI_BIOS@0x500000 0x300000 { RW_SECTION_A@0x00000 0x180000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x16ffc0 + RW_FWID_A@0x17ffc0% 0x40 } UNIFIED_MRC_CACHE@0x180000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 @@ -18,9 +18,9 @@ SMMSTORE(PRESERVE)@0x1a1000 0x40000 WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 COREBOOT(CBFS)@0x20000 0xff000 diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd index 0d6af2d..dbb31cb 100644 --- a/src/mainboard/opencellular/elgon/vboot.fmd +++ b/src/mainboard/opencellular/elgon/vboot.fmd @@ -4,8 +4,8 @@ RO_SECTION@0x0 0x3fc000 { # 0 - 0x10000 is free for firmware usage. # bootblock starts at 0x20000 - FMAP@0x0 0x1000 - RO_FRID@0x1000 0x100 + FMAP@0x0% 0x1000 + RO_FRID@0x1000% 0x100 # bootblock includes trusted/non-trusted CLIB, CSIB, # and BL1FWs packaged in # src/soc/cavium/common/Makefile.inc. @@ -17,13 +17,13 @@ } RW_SECTION_A@0x400000 0x5fa000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x5f7f00 - RW_FWID_A@0x5f9f00 0x100 + FW_MAIN_A(CBFS)@0x2000% 0x5f7f00 + RW_FWID_A@0x5f9f00% 0x100 } RW_SECTION_B@0x9fa000 0x5fa000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x5f7f00 - RW_FWID_B@0x5f9f00 0x100 + FW_MAIN_B(CBFS)@0x2000% 0x5f7f00 + RW_FWID_B@0x5f9f00% 0x100 } RW_ELOG(PRESERVE)@0xff4000 0x4000 RW_VPD(PRESERVE)@0xff8000 0x8000 diff --git a/src/mainboard/samsung/lumpy/chromeos.fmd b/src/mainboard/samsung/lumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/lumpy/chromeos.fmd +++ b/src/mainboard/samsung/lumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/samsung/stumpy/chromeos.fmd b/src/mainboard/samsung/stumpy/chromeos.fmd index 9852a22..95ec048 100644 --- a/src/mainboard/samsung/stumpy/chromeos.fmd +++ b/src/mainboard/samsung/stumpy/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 36772d6..2dd2173 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI 0x2ff000 - FMAP 0x800 - COREBOOT(CBFS) 0xb9d800 + FMAP% 0x800 + COREBOOT(CBFS)% 0xb9d800 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index 8af2e9a..c9d1c148 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -4,9 +4,9 @@ IFWI 0x2ff000 RO_VPD 0x4000 RO_SECTION 0xb8f000 { - FMAP 0x800 - RO_FRID 0x40 - RO_FRID_PAD 0x7c0 + FMAP% 0x800 + RO_FRID% 0x40 + RO_FRID_PAD% 0x7c0 COREBOOT(CBFS) 0xb4e000 GBB 0x40000 } diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd index a295680..96f359e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x500000 0xb00000 { RW_SECTION_A@0x0 0x33e000 { VBLOCK_A@0x0 0x20000 - FW_MAIN_A(CBFS)@0x20000 0x31dfc0 - RW_FWID_A@0x33dfc0 0x40 + FW_MAIN_A(CBFS)@0x20000% 0x31dfc0 + RW_FWID_A@0x33dfc0% 0x40 } RW_SECTION_B@0x33e000 0x33e000 { VBLOCK_B@0x0 0x20000 - FW_MAIN_B(CBFS)@0x20000 0x31dfc0 - RW_FWID_B@0x33dfc0 0x40 + FW_MAIN_B(CBFS)@0x20000% 0x31dfc0 + RW_FWID_B@0x33dfc0% 0x40 } MISC_RW@0x67d000 0x62000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -25,9 +25,9 @@ WP_RO@0x6df000 0x421000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x41d000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x32d000 } diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd index 72f92fe..afebc8c 100644 --- a/src/mainboard/up/squared/vboot-ro.fmd +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0xe91000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0xb8d800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0xb8d800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0xb4d000 } diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd index 330ce03..b23e69f 100644 --- a/src/mainboard/up/squared/vboot-roa.fmd +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -3,11 +3,11 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x502000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1fe800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1fe800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 GBB@0x800 0x40000 COREBOOT(CBFS)@0x40800 0x1be000 } @@ -28,8 +28,8 @@ } RW_SECTION_A@0x52f000 0x98f000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x97efc0 - RW_FWID_A@0x98efc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x97efc0 + RW_FWID_A@0x98efc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd index 4ddcbc0..90e8e37 100644 --- a/src/mainboard/up/squared/vboot-roab.fmd +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -3,12 +3,12 @@ SI_BIOS@0x1000 0xefe000 { WP_RO@0x0 0x503000 { IFWI@0x0 0x2ff000 - FMAP@0x2ff000 0x800 - RO_VPD(PRESERVE)@0x2ff800 0x4000 - RO_SECTION@0x303800 0x1ff800 { - RO_FRID@0x0 0x40 - RO_FRID_PAD@0x40 0x7c0 - GBB@0x800 0x40000 + FMAP@0x2ff000% 0x800 + RO_VPD(PRESERVE)@0x2ff800% 0x4000 + RO_SECTION@0x303800% 0x1ff800 { + RO_FRID@0x0% 0x40 + RO_FRID_PAD@0x40% 0x7c0 + GBB@0x800% 0x40000 COREBOOT(CBFS)@0x40800 0x1bf000 } } @@ -28,13 +28,13 @@ } RW_SECTION_A@0x530000 0x4c7000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 - RW_FWID_A@0x4c6fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_A@0x4c6fc0% 0x40 } RW_SECTION_B@0x9f7000 0x4c7000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 - RW_FWID_B@0x4c6fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x4b6fc0 + RW_FWID_B@0x4c6fc0% 0x40 } BIOS_UNUSABLE@0xebe000 0x40000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd1e68990a272fbde9a0238f8a8b75db1549b05 Gerrit-Change-Number: 37317 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: [WIP]security: Add option to lock regions for SMMSTORE
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40829 ) Change subject: [WIP]security: Add option to lock regions for SMMSTORE ...................................................................... [WIP]security: Add option to lock regions for SMMSTORE On many server boards the flash is updateable out of band using the BMC and the bios region doesn't need to be writeable except for the SMM_STORE. Add an option to write-protect the COREBOOT and FMAP region. UNTESTED. Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/lockdown.c 2 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/40829/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index 30b5237..d24c5e5 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -72,6 +72,23 @@ is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS). +config BOOTMEDIA_LOCK_COREBOOT_FMAP_RO + depends on BOOTMEDIA_LOCK_CONTROLLER + bool "Write-protect COREBOOT and FMAP region in boot medium" + help + Select this if you want to write-protect the COREBOOT and FMAP region + as specified in the FMAP. You will be able to write every region outside + of COREBOOT and FMAP using the internal controller (eg. SMM_STORE). + + The locking will take place during the chipset lockdown. + Chipset lockdown is platform specific und might be done unconditionally, + when INTEL_CHIPSET_LOCKDOWN is set or has to be triggered later + (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to update coreboot using the internal + controller any more. + endchoice config BOOTMEDIA_LOCK_IN_VERSTAGE diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index 62d0a29..b4698d7 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -28,8 +28,11 @@ } else if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = CTRLR_WP; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + printk(BIOS_DEBUG, "'COREBOOT and FMAP'"); + lock_type = CTRLR_WP; } - printk(BIOS_DEBUG, "using CTRL...\n"); + printk(BIOS_DEBUG, " using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); @@ -38,7 +41,7 @@ printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = MEDIA_WP; } - printk(BIOS_DEBUG, "using flash chip...\n"); + printk(BIOS_DEBUG, " using flash chip...\n"); } if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { @@ -46,6 +49,11 @@ printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); else rdev = &dev; + } else if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("COREBOOT", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'COREBOOT'\n"); + else + rdev = &dev; } else { rdev = boot_device_ro(); } @@ -54,6 +62,15 @@ printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); else printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + + if (CONFIG(BOOTMEDIA_LOCK_COREBOOT_FMAP_RO)) { + if (fmap_locate_area_as_rdev("FMAP", &dev) < 0) + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'FMAP'\n"); + else if (boot_device_wp_region(&dev, lock_type) >= 0) + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled bootmedia protection\n"); + else + printk(BIOS_ERR, "BM-LOCKDOWN: Failed to enable bootmedia protection\n"); + } } static void lock(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/40829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1096be9650f2af3e886f12f7db50c5060e0d40e1 Gerrit-Change-Number: 40829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub
by Philipp Hug (Code Review) 10 Jun '23

10 Jun '23

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41826 ) Change subject: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub ...................................................................... WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub Set PchTraceHubMode and CpuTraceHubMode if TraceHubMode is set. To use Intel DCI: * enable the following PCI devices 14.1 xDCI and 1f.7 Trace Hub * set the TraceHubMode to 2 in the devicetree for remote debugging * set CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=3 in KConfig TODO=Add documentation TEST=Tested on lemp9, debugging works Change-Id: I86e2aff3002a8d2a9e4d121cafaef79aa3ee981b Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41826/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a30f732..f7f8828 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -335,6 +335,21 @@ enum serirq_mode serirq_mode; + /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c1afd1e..8a8168b 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -67,8 +67,16 @@ * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub * BIT2 - Not used. */ - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -- To view, visit https://review.coreboot.org/c/coreboot/+/41826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86e2aff3002a8d2a9e4d121cafaef79aa3ee981b Gerrit-Change-Number: 41826 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32078 Change subject: mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 ...................................................................... mb/google/hatch:[DEBUG ONLY] Assert DEVSLP in S3 It was obsevred that the DEVSLP is keeping low in S3, and SDD is drawing some power, assert DEVSLP in S3 to indicate SSD to go into low power mode. Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32078/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 5987abc..15038b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -410,6 +410,7 @@ /* Default GPIO settings before entering sleep. */ static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_E5, 1, DEEP), }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001781fd0e1e5763f6865966658fc9fccc3edff8 Gerrit-Change-Number: 32078 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: [WIP]device/pci_rom: Add ATRM method
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31502 Change subject: [WIP]device/pci_rom: Add ATRM method ...................................................................... [WIP]device/pci_rom: Add ATRM method Add ATRM method for AMD GPUs, which is similar to _ROM. As both functions seem to have identical arguments and return values, redirect ATRM to _ROM. Don't depend on VGA devices, but display devices, as some AMD dGPUs identify themself as PCI_CLASS_DISPLAY_OTHER. Needs test on platforms with AMD display devices. Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pci_rom.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31502/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..86c839c 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -272,8 +272,8 @@ { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ @@ -319,9 +319,21 @@ memcpy(cbrom, rom, cbrom_length); - /* write _ROM method */ + /* write ACPI methods */ acpigen_write_scope(scope); + + /* Nvidia uses _ROM */ acpigen_write_rom(cbrom, cbrom_length); + + /* AMD uses ATRM. Redirect ATRM to _ROM */ + acpigen_write_method_serialized("ATRM", 2); + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("_ROM"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* pop method */ + acpigen_pop_len(); /* pop scope */ } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2212f29f0de051f6cbd59f8332e86696c1166ab Gerrit-Change-Number: 31502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: Updated and converted to markdown doc from wiki on porting motherboards.
by Calvin (Code Review) 10 Jun '23

10 Jun '23

Calvin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31849 Change subject: Updated and converted to markdown doc from wiki on porting motherboards. ...................................................................... Updated and converted to markdown doc from wiki on porting motherboards. Some of the documentation from the wiki (https://www.coreboot.org/Motherboard_Porting_Guide) has been ported to markdown and updated as I was able to figure things out. Still a work in progress as there is more data from that page that I will need to convert as I work through it. If I get anywhere in my project of porting coreboot to an older Chromebook, I will document more of this process as I go. Signed-off-by: calvinrempel <calvin.rempel(a)gmail.com> Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 --- M Documentation/index.md A Documentation/porting/index.md A Documentation/porting/motherboard_probe.md 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31849/1 diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..32635f9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -164,6 +164,7 @@ * [Rookie Guide](lessons/index.md) * [Coding Style](coding_style.md) * [Project Ideas](contributing/project_ideas.md) +* [Porting](porting/index.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/porting/index.md b/Documentation/porting/index.md new file mode 100644 index 0000000..ed282e8 --- /dev/null +++ b/Documentation/porting/index.md @@ -0,0 +1,3 @@ +# Porting New Boards + +* [Motherboard Probing](motherboard_probe.md) diff --git a/Documentation/porting/motherboard_probe.md b/Documentation/porting/motherboard_probe.md new file mode 100644 index 0000000..7562f7c --- /dev/null +++ b/Documentation/porting/motherboard_probe.md @@ -0,0 +1,131 @@ +Motherboard Porting Guide +========================= + +Please note that this guide is very much a work in progress. + +Finding out What You Have +------------------------- + +### Tools +To begin the process of porting a motherboard to coreboot, you first +need to determine what all is on it: the chipset (ie, North and South +Bridge), Flash Rom, etc. To do this, you will need a suite of +tools provided by the coreboot project, as well as some that can be +found more readily in various repositories. + +For the sake of this page, it will be assumed you are using Debian or +Ubuntu. + +#### Build Environment +If you have not already done so, get your basic build environment +installed: + + $ sudo apt install build-essential git cvs subversion + +#### Probing Utilities - From Repos +Next, a number of utilities will need to be installed which will be used +later for probing the system as well as some dev libraries which will be +used in building some of the tools in the next step.These should be +available in your distro's repo: + + $ sudo apt install pciutils pciutils-dev flashrom acpitool \ + usbutils acpidump + +#### Probing Utilities - From Source +Once the base build system in place and what utilities along with what +libraries you can glean from your distro's repositories, it is time to +build some tools from source. If you have not already done so, checkout +the git repo as described in "[Rookie Guide: Lesson 1]". + +Once you have synced the coreboot repo, cd into the utilities folder: + + $cd coreboot/util + +##### superiotool + + $ cd ./superiotool + $ make + $ sudo make install + $ cd .. + +##### inteltool + + $ cd ./inteltool + $ make + $ sudo make install + $ cd .. + +##### ectool + + $ cd ./ectool + $ make + $ make install + $ cd .. + +##### dmidecode + + $ cvs -z3 -d:pserver:anonymous@cvs.savannah.nongnu.org:/sources/dmidecode \ + co dmidecode + $ cd dmidecode + $ make + $ sudo make install + $ cd .. + +##### msrtool + + $ cd ./msrtool + $ ./configure + $ make + $ sudo make install + $ cd .. + +##### nvramtool + + $ cd ./nvramtool + $ make + $ sudo make install + +##### acpica-unix + + $ wget http://deb.debian.org/debian/pool/main/a/acpica-unix/acpica-unix_20181213.o… + $ tar -xaf acpica-unix_20181213.orig.tar.gz + $ cd ./acpica-unix-2018-12-13/ + $ make + $ sudo make install + +### Probe the Board +Now we will begin to probe the board to see what we can find out about +it. First, become root: + + $ sudo su + +Then load the msr module into the kernel: + + $ sudo modprobe msr + +Finally, we probe the board: + + $ lspci -nnvvvxxxx > lspci.log 2> lspci.err.log + $ lsusb -vvv > lsusb.log 2> lsusb.err.log + $ superiotool -deV > superiotool.log 2> superiotool.err.log + $ inteltool -a > inteltool.log 2> inteltool.err.log + $ ectool -i > ectool.log 2> ectool.err.log + $ msrtool > msrtool.log 2> msrtool.err.log + $ dmidecode > dmidecode.log 2> dmidecode.err.log + $ biosdecode > biosdecode.log 2> biosdecode.err.log + $ nvramtool -x > nvramtool.log 2> nvramtool.err.log + $ dmesg > dmesg.log 2> dmesg.err.log + $ acpidump > acpidump.log 2> acpidump.err.log + $ for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" \ + > pin_"$(basename "$x")"; done + $ for x in /proc/asound/card0/codec#*; do cat "$x" > \ + "$(basename "$x")"; done + $ cat /proc/cpuinfo > cpuinfo.log 2> cpuinfo.err.log + $ cat /proc/ioports > ioports.log 2> ioports.err.log + $ cat /sys/class/input/input*/id/bustype > input_bustypes.log + $flashrom -V -p internal:laptop=force_I_want_a_brick > \ + flashrom_info.log 2> flashrom_info.err.log + $ flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > \ + flashrom_read.log 2> flashrom_read.err.log + +[Rookie Guide: Lesson 1]: https://doc.coreboot.org/lessons/lesson1.html -- To view, visit https://review.coreboot.org/c/coreboot/+/31849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3b8a99c10808c7e7ebc826b4d2f992774cc9a75 Gerrit-Change-Number: 31849 Gerrit-PatchSet: 1 Gerrit-Owner: Calvin <calvin.rempel(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: util/mtkheader: Add a tool to extract bootload header from binary files.
by You-Cheng Syu (Code Review) 10 Jun '23

10 Jun '23

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32333 Change subject: util/mtkheader: Add a tool to extract bootload header from binary files. ...................................................................... util/mtkheader: Add a tool to extract bootload header from binary files. Add a tool, extract-bl-img.py, which can extract MTK bootload header from binary files. This could be useful for boards (e.g., Kukui) which put the bootblock in other places (e.g., Chrome EC). Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- A util/mtkheader/extract-bl-img.py 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32333/1 diff --git a/util/mtkheader/extract-bl-img.py b/util/mtkheader/extract-bl-img.py new file mode 100755 index 0000000..21bf9eb --- /dev/null +++ b/util/mtkheader/extract-bl-img.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python +# This file is part of the coreboot project. +# +# Copyright 2019 Google LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +import argparse +import struct +import sys + + +_DESCRIPTION = 'Extract MTK bootload header from a binary file.' + + +def parse_args(): + parser = argparse.ArgumentParser(description=_DESCRIPTION) + parser.add_argument('input_path', metavar='INPUT_FILE') + parser.add_argument('output_path', metavar='OUTPUT_FILE') + return parser.parse_args() + + +def main(): + args = parse_args() + + with open(args.input_path, 'rb') as f: + data = f.read() + + header = struct.pack('<8sII', 'BRLYT', 1, 2048) + + start = -1 + while True: + start = data.find(header, start + 1) + if start < 0: + raise RuntimeError('Cannot find MTK bootload header') + offset = start + len(header) + buf = struct.unpack('<II', data[offset:offset+8]) + if buf[1] == 0x42424242: + break + size = buf[0] + offset = start - 512 + + with open(args.output_path, 'wb') as f: + f.write(data[offset:offset+size]) + + +if __name__ == '__main__': + main() -- To view, visit https://review.coreboot.org/c/coreboot/+/32333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib744c80bdc2adfe27d4287365e161096e3fe08c7 Gerrit-Change-Number: 32333 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

2 1

Change in ...coreboot[master]: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proo...
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32082 Change subject: Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept ...................................................................... Patch SSDTs into qemu, and add VPD area to the fmap for q35 as a proof of concept Change-Id: I8c31fa79e13be237a752f47e72a6a7025fe9dffd reformatting Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 --- M src/arch/x86/acpi.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-q35/Kconfig 3 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32082/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..7bbbd2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -38,7 +38,6 @@ */ #include <console/console.h> -#include <string.h> #include <arch/acpi.h> #include <arch/acpi_ivrs.h> #include <arch/acpigen.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..af5dddd 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -225,6 +225,8 @@ BiosLinkerLoaderEntry *s; unsigned long *addrs, current; uint8_t *ptr; + acpi_rsdp_t *rsdp = NULL; + acpi_header_t *ssdt; int i, j, src, dst, max; if (fw_cfg_check_file(&f, "etc/table-loader")) @@ -251,6 +253,10 @@ printk(BIOS_DEBUG, "QEMU: loading \"%s\" to 0x%lx (len %d)\n", s[i].alloc.file, current, f.size); + if (!strncmp(s[i].alloc.file, "etc/acpi/rsdp", 13)) { + printk(BIOS_DEBUG, "Found RSDP at 0x%lx\n", current); + rsdp = (acpi_rsdp_t *) current; + } fw_cfg_get(f.select, (void *)current, f.size); addrs[i] = current; current += f.size; @@ -322,6 +328,16 @@ }; } + if (rsdp) { + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(acpi_header_t)) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } + } + printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n"); free(s); free(addrs); diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 815b93b..0672092 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -54,4 +54,8 @@ hex default 0x4000 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_EMULATION_QEMU_X86_Q35 -- To view, visit https://review.coreboot.org/c/coreboot/+/32082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1b161a89d860c350d4735f843f6bee42313378 Gerrit-Change-Number: 32082 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: Add default boards for qemu, that has VPD partitions.
by John Looney (Code Review) 10 Jun '23

10 Jun '23

John Looney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32144 Change subject: Add default boards for qemu, that has VPD partitions. ...................................................................... Add default boards for qemu, that has VPD partitions. Tested with https://review.coreboot.org/c/coreboot/+/31984 and the 'vpd' command to add VPD variables to those partitions, then checked that they were exported to userspace. Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc --- A src/mainboard/emulation/qemu-i440fx/board.fmd A src/mainboard/emulation/qemu-q35/board.fmd 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32144/1 diff --git a/src/mainboard/emulation/qemu-i440fx/board.fmd b/src/mainboard/emulation/qemu-i440fx/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 0000000..a97e218 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,16 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash +FLASH@4278190080 0x1000000 { + BIOS@0 0x1000000 { + FMAP@0 0x200 + RO_VPD@0x200 0x10000 + RW_VPD@0x10200 0x1000 + COREBOOT(CBFS)@0x11200 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aca55543cb3bdbdb77c8b421cbbafad2405d3cc Gerrit-Change-Number: 32144 Gerrit-PatchSet: 1 Gerrit-Owner: John Looney <john.looney(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mb/*/devicetree.cb: Add more smbios_slot_desc
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32684 Change subject: mb/*/devicetree.cb: Add more smbios_slot_desc ...................................................................... mb/*/devicetree.cb: Add more smbios_slot_desc Add smbios_slot_desc for desktop and serverboards. Fill in PCIe, PCI and Mini PCIe slots. Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/asus/h61m-cs/devicetree.cb M src/mainboard/asus/kcma-d8/devicetree.cb M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 22 files changed, 100 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32684/1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 9eba6fc..18c0c12 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -48,6 +48,7 @@ end device pci 01.0 on subsystemid 0x1849 0x0151 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on subsystemid 0x1849 0x0152 @@ -92,6 +93,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x1849 0x1e10 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -114,6 +116,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x1849 0x244e + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1e49 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..1e4d6bc 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -267,6 +267,7 @@ end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 @@ -295,7 +296,9 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 58a319d..a25a57e 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -38,6 +38,7 @@ device pci 01.0 on # PCIe graphics subsystemid 0x1849 0x0c01 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # VGA controller @@ -101,6 +102,7 @@ end device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" end device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index 9a4c6fe..118e435 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -30,7 +30,9 @@ device domain 0x0 on subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index f8a2d83..49bb8b2 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -17,6 +17,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -211,12 +212,15 @@ device pci 14.4 on # Bridge device pci 1.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot 0" "5" end device pci 2.0 on # Slot # Slot # PCI 1 + smbios_slot_desc "6" "3" "PCI slot 1" "5" end device pci 3.0 on # Slot # Slot # PCI 2 + smbios_slot_desc "6" "3" "PCI slot 2" "5" end device pci 5.0 on end # VGA end diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..5710521 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -18,6 +18,7 @@ device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" end device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) @@ -35,12 +36,15 @@ end device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci c.0 on # Bridge (GPP2 Port1) # Slot # PCI E 5 + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xb" end device pci d.0 on # Bridge (GPP3b Port0) # Slot # PCI E 3 + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 @@ -226,6 +230,7 @@ device pci 2.0 on end # FireWire device pci 3.0 on # Slot # Slot # PCI 0 + smbios_slot_desc "6" "3" "PCI slot" "5" end end device pci 14.5 on end # USB OHCI2 0x4399 diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f39..915b67a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071f..80cd2e9 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x1043 0x844d inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index f853452..d3706d5 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -119,7 +119,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe bridge for discrete graphics (PCIEX16_1) device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568a..409314e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -24,7 +24,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end @@ -73,7 +75,9 @@ device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end - device pci 1e.0 on end # PCI bridge + device pci 1e.0 on + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" + end # PCI bridge device pci 1f.0 on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index a00e2ee..faf05a2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -23,7 +23,9 @@ device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index e382cbd..72d064c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -31,7 +31,9 @@ register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics (PCIEX16) device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 95659be..1c97750 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -72,6 +72,7 @@ end device pci 1c.0 on # PCIe Port #1 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb0" "4" "PCI Express x4" "0xa" end device pci 1c.1 off # PCIe Port #2 end @@ -81,6 +82,7 @@ end device pci 1c.4 on # PCIe Port #5 subsystemid 0x103c 0x1495 + smbios_slot_desc "0xac" "4" "PCI Express x1" "0x8" end device pci 1c.5 off # PCIe Port #6 end @@ -95,6 +97,7 @@ end device pci 1e.0 on # PCI bridge subsystemid 0x103c 0x1495 + smbios_slot_desc "0x6" "3" "PCI slot" "0x5" end device pci 1f.0 on # LPC bridge PCI-LPC bridge subsystemid 0x103c 0x1495 @@ -214,6 +217,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x103c 0x1495 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x103c 0x1495 diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fad139a..3feb4e7 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -21,7 +21,8 @@ device domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge x16 + device pci 01.0 on + end # PCIe Bridge x16 device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -56,13 +57,19 @@ # Disabling 1c.0 might break IRQ settings as it enables port coalescing # There are two mini PCIe x1 sockets, so one PCIe port is unrouted - device pci 1c.0 on end # PCIe Port #1 mini PCIe x1? - device pci 1c.1 on end # PCIe Port #2 mini PCIe x1? + device pci 1c.0 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #1 mini PCIe x1? + device pci 1c.1 on + smbios_slot_desc "0x22" "4" "PCI Express Mini" "8" + end # PCIe Port #2 mini PCIe x1? device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY device pci 1c.5 on end # PCIe Port #6 FireWire - device pci 1c.6 on end # PCIe Port #7 PCIe x1 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 PCIe x1 device pci 1c.7 on end # PCIe Port #8 mini PCIe x1? device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 4db2536..58e6942 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -35,13 +35,17 @@ device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 + device pci 1c.6 on + smbios_slot_desc "0xac" "4" "PCI Express x1" "8" + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge @@ -111,7 +115,9 @@ device pci 1f.6 off end # Thermal end device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 01.0 on + smbios_slot_desc "0xb0" "4" "PCI Express x16" "0xd" + end # PCIe Bridge for discrete graphics device pci 02.0 off end # Internal graphics end end diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2e8b8f4..4074e82 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -27,7 +27,9 @@ device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 + device pci 7.0 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # PCIE P2P bridge miniPCIe slot 1 device pci 8.0 on end # NB/SB Link P2P bridge end # agesa northbridge @@ -77,7 +79,9 @@ device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 + device pci 15.0 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # PCIe PortA miniPCIe slot 2 device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 6728228..e37dc20 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 0c0c21e..2c2900c 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c93c04f..95a6920 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -32,7 +32,9 @@ device pci 2.2 on end # LAN2 device pci 2.3 on end # LAN3 device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index b6b22cf..dac8c50 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -28,11 +28,15 @@ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.1 on + smbios_slot_desc "0x22" "4" "mPCIe 2" "8" + end # mPCIe slot 2 (on GFX lane) device pci 2.2 on end # LAN3 device pci 2.3 on end # LAN2 device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 + device pci 2.5 on + smbios_slot_desc "0x22" "4" "mPCIe 1" "8" + end # mPCIe slot 1 device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..05dec1b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -157,6 +157,7 @@ end device pci 01.0 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xd" end device pci 02.0 on # Internal graphics VGA controller subsystemid 0x8086 0x2010 diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 434fb59..5784fe0 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -34,7 +34,9 @@ subsystemid 0x15d9 0x0803 inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG 10 + device pci 01.0 on + smbios_slot_desc "0xb6" "4" "PCI Express x16" "0xb" + end # PEG 10 device pci 01.1 on end # PEG 11 device pci 02.0 off end # IGD device pci 03.0 off end # Mini-HD audio @@ -78,7 +80,9 @@ subsystemid 0x15d9 0x1533 end end - device pci 1c.4 on end # PCIe root port 5 + device pci 1c.4 on + smbios_slot_desc "0xaf" "4" "PCI Express x8" "0xa" + end # PCIe root port 5 device pci 1c.5 off end # PCIe root port 6 device pci 1c.6 off end # PCIe root port 7 device pci 1c.7 off end # PCIe root port 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/32684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I829de30c50212bb90cb51470af91518fd9b9e41c Gerrit-Change-Number: 32684 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020