coreboot-gerrit November 2020

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Change in coreboot[master]: mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code
by Julien Viard de Galbert (Code Review) 10 Jun '23

10 Jun '23

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47479 ) Change subject: mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code ...................................................................... mb/scaleway/tagada: Add bmcinfo field confMRC to configure FSP MRC code The BMC now expose an extra field to give more control over the FSP MRC options. Change-Id: I2cad2ec24ff61d384e040c23a24782d8934b6f0b Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/scaleway/tagada/bmcinfo.h M src/mainboard/scaleway/tagada/romstage.c 3 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47479/1 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 9f30a7e..b2037fc 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -21,6 +21,7 @@ u8 bootOption; u8 hwRev; // Note: Initial implementation ended here u8 disableNic1; + u8 confMRC; u8 endMarker; // Insert new fields before } biosBmcInfo_t; @@ -162,6 +163,15 @@ return 0; } +int bmcinfo_conf_mrc(void) +{ + if (IS_BMC_INFO_FIELD_VALID(confMRC)) { + printk(BIOS_DEBUG, "bmcInfo confMRC=%x\n", BMC_INFO->confMRC); + return BMC_INFO->confMRC; + } + return CONF_MRC_DEFAULT; +} + /* Add override functions below */ /* Override default uart baudrate */ diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h index 016de9b..de014bb 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ b/src/mainboard/scaleway/tagada/bmcinfo.h @@ -13,6 +13,13 @@ // Reset after boot sequence (don't go to EFI shell) #define BOOT_OPTION_NO_EFISHELL 0x80 +// Enable FastBoot +#define CONF_MRC_FAST_BOOT 1 +// Enable MRC RMT reporting +#define CONF_MRC_RMT_ENABLE 2 + +#define CONF_MRC_DEFAULT (CONF_MRC_FAST_BOOT | CONF_MRC_RMT_ENABLE) + char *bmcinfo_serial(void); u8 *bmcinfo_uuid(void); int bmcinfo_slot(void); @@ -23,5 +30,6 @@ int bmcinfo_relax_security(void); int bmcinfo_boot_option(void); int bmcinfo_disable_nic1(void); +int bmcinfo_conf_mrc(void); #endif /* MAINBOARD_BMCINFO_H */ diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index f041b6f..6b3ac47 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -41,6 +41,7 @@ // Enable Rmt and Fast Boot by default, RMT will be run only on first // boot or when dimms change - mupd->FspmConfig.PcdMrcRmtSupport = 1; - mupd->FspmConfig.PcdFastBoot = 1; + int confMRC = bmcinfo_conf_mrc(); + mupd->FspmConfig.PcdMrcRmtSupport = (confMRC & CONF_MRC_RMT_ENABLE)?1:0; + mupd->FspmConfig.PcdFastBoot = (confMRC & CONF_MRC_FAST_BOOT)?1:0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cad2ec24ff61d384e040c23a24782d8934b6f0b Gerrit-Change-Number: 47479 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
by David Jimenez (Code Review) 10 Jun '23

10 Jun '23

David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 ) Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch ...................................................................... mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration Signed-off-by: David Jimenez <dvjimenez(a)chromium.org> Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f7cf3cd..f360c10 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -50,6 +50,8 @@ register "PchUnlockGpioPads" = "1" # SD card WP pin confguration register "ScsSdCardWpPinEnabled" = "0" + # Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support + register "TetonGlacierMode" = "1" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of @@ -163,7 +165,7 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" - # Enable Root port 9(x4) for NVMe. + # Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -171,6 +173,10 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # Enable Root port 11(x2) for NVMe hybrid storage devices. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" @@ -324,9 +330,9 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on end # PCI Express Port 9 (X2 NVME) device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 (x2 NVME) device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..16265d2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + // Enables support for Teton Glacier hybrid storage device + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dc4a2a8..e8ad62f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable; + /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df Gerrit-Change-Number: 38947 Gerrit-PatchSet: 1 Gerrit-Owner: David Jimenez <dvjimenez(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG
by Chen Wisley (Code Review) 10 Jun '23

10 Jun '23

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47733 ) Change subject: xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG ...................................................................... xmb/google/volteer: Add BOOT_*_SUPPORT to FW_CONFIG bit 22 for BOOT_SUPPORT_NVME bit 23 for BOOT_SUPPORT_SATA bit 24 for BOOT_SUPPORT_EMMC: bit24 BUG=none BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I41a6c624c8e32a6115b496f523dbd7a7c3f038c4 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47733/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 50be736..18d1f6b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -38,6 +38,15 @@ option SD_GL9755S 1 option SD_RTS5261 2 end + field BOOT_NVME_MASK 22 + option BOOT_SUPPORT_NVME 1 + end + field BOOT_SATA_MASK 23 + option BOOT_SUPPORT_SATA 1 + end + field BOOT_EMMC_MASK 24 + option BOOT_SUPPORT_EMMC 1 + end end chip soc/intel/tigerlake -- To view, visit https://review.coreboot.org/c/coreboot/+/47733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41a6c624c8e32a6115b496f523dbd7a7c3f038c4 Gerrit-Change-Number: 47733 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/sipi_vector: Properly use uintptr_t
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47711 ) Change subject: cpu/x86/sipi_vector: Properly use uintptr_t ...................................................................... cpu/x86/sipi_vector: Properly use uintptr_t Change-Id: Ifc60e1efa6fe6a3029ef9e5e63ce50afa8c8c51c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/sipi_vector.S M src/include/cpu/x86/mp.h 2 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47711/1 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ad614ae..cb5641a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -15,6 +15,11 @@ * C code. The C handler loads microcode, sets up MSRs, and enables caching * before calling into the MP init provided 'c_handler' */ +#if ENV_X86_64 +#define uintptr_t quad +#else +#define uintptr_t long +#endif .section ".module_parameters", "aw", @progbits ap_start_params: @@ -25,19 +30,19 @@ idt_ptr: .long 0 stack_top: -.long 0 +.uintptr_t 0 stack_size: .long 0 microcode_lock: .long 0 microcode_ptr: -.long 0 +.uintptr_t 0 msr_table_ptr: -.long 0 +.uintptr_t 0 msr_count: .long 0 c_handler: -.long 0 +.uintptr_t 0 ap_count: .long 0 diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index b55e2e7..ed6e91f 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -149,13 +149,13 @@ uint32_t gdt; uint16_t unused; uint32_t idt_ptr; - uint32_t stack_top; + uintptr_t stack_top; uint32_t stack_size; uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ - uint32_t microcode_ptr; - uint32_t msr_table_ptr; + uintptr_t microcode_ptr; + uintptr_t msr_table_ptr; uint32_t msr_count; - uint32_t c_handler; + uintptr_t c_handler; atomic_t ap_count; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/47711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc60e1efa6fe6a3029ef9e5e63ce50afa8c8c51c Gerrit-Change-Number: 47711 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test
by Aamir Bohra (Code Review) 10 Jun '23

10 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47788 ) Change subject: soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test ...................................................................... soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test Change-Id: I4813572a31240b2796cacfa97044f9ed091ec108 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/jasperlake/bootblock/bootblock.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47788/1 diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 96e6268..a1254cf 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <console/console.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <string.h> + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -22,6 +25,31 @@ uart_bootblock_init(); } +static void report_cache_info(void) +{ + struct cpuid_result res; + uintptr_t addr = 0xFF000000; + char buf[1024]; + uint32_t kbcount=0; + res = cpuid_ext(0x04, 0x03); + const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; + const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; + const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; + const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; + printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", + assoc, partitions, cache_line_size, number_of_sets); + printk(BIOS_INFO, "@@ dedede cache_size 0x%lx bytes\n", cache_size); + + while (addr < 0xFFFF0000) { + memcpy(buf, (void *)addr, 1024); + printk(BIOS_ERR, "TEST : %lx %x KBcount : %d \n", addr, buf[0], kbcount); + addr += 1024; + ++kbcount; + } + +} + void bootblock_soc_init(void) { report_platform_info(); @@ -29,4 +57,5 @@ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + report_cache_info(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4813572a31240b2796cacfa97044f9ed091ec108 Gerrit-Change-Number: 47788 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/tigerlake: Get SPI-DMI destination Id
by Srinidhi N Kaushik (Code Review) 10 Jun '23

10 Jun '23

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48067 ) Change subject: src/soc/intel/tigerlake: Get SPI-DMI destination Id ...................................................................... src/soc/intel/tigerlake: Get SPI-DMI destination Id Add support to get SPI_DMI destination id. This change implements SOC function that rteruns SPI-DMI Destination id by calling soc_get_spi_dmi_destination_id(). BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Idf500f1ccf576bbb903bdb5e218263d3f1295ae8 --- M src/soc/intel/tigerlake/spi.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48067/1 diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index 63d9d80..fa63713 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -7,7 +7,9 @@ */ #include <intelblocks/spi.h> +#include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -23,3 +25,8 @@ } return -1; } + +uint32_t soc_get_spi_dmi_destination_id() +{ + return SPI_DMI_DESTINATION_ID; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf500f1ccf576bbb903bdb5e218263d3f1295ae8 Gerrit-Change-Number: 48067 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Add builder Kontron mAL-10 config
by Maxim Polyakov (Code Review) 10 Jun '23

10 Jun '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47886 ) Change subject: configs: Add builder Kontron mAL-10 config ...................................................................... configs: Add builder Kontron mAL-10 config Add config file that can be used to build the coreboot image for the Kontron mAL-10 module. Change-Id: I7144a49410d05783224760ebc1933011b22a108b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A configs/config.kontron_mal10 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47886/1 diff --git a/configs/config.kontron_mal10 b/configs/config.kontron_mal10 new file mode 100644 index 0000000..fa9ecf1 --- /dev/null +++ b/configs/config.kontron_mal10 @@ -0,0 +1,7 @@ +CONFIG_VENDOR_KONTRON=y +CONFIG_FMDFILE="src/mainboard/kontron/mal10/mal10.fmd" +CONFIG_NEED_IFWI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_KONTRON_COME_MAL10=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_PAYLOAD_NONE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/47886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7144a49410d05783224760ebc1933011b22a108b Gerrit-Change-Number: 47886 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46558 ) Change subject: mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation ...................................................................... mb/amd/mandolin: cereme: Use 64K instead of 0x1000 for size notation Use the more readable size notation, which also unifies it with Mandolin’s FMD. Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/mandolin/variants/cereme/board.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46558/1 diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd index b55b8b5..31a0b2a 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/board.fmd +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -1,7 +1,7 @@ FLASH@0xFF000000 16M { BIOS { EC 0x20000 - RW_MRC_CACHE 0x10000 + RW_MRC_CACHE 64K FMAP 0x1000 COREBOOT(CBFS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95c22d8d775104dc046601418bd402317dd8e676 Gerrit-Change-Number: 46558 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel: Add unaligned flag (%) sections that don't need alignment
by Hung-Te Lin (Code Review) 10 Jun '23

10 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37314 ) Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ...................................................................... mb/intel: Add unaligned flag (%) sections that don't need alignment Sections that won't be updated independently and don't need to be aligned. Note: glkrvp/chromeos.fmd had unaligned RW_SECTION_{A,B} and is fixed now. leafhill/leafhill.8192.fmd had unaligned UNIFIED_MRC_CACHE and is fixed. Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/intel/baskingridge/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/icelake_rvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/intel/strago/chromeos.fmd M src/mainboard/intel/wtm2/chromeos.fmd 14 files changed, 88 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37314/1 diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.fmd +++ b/src/mainboard/intel/baskingridge/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..0a7be5f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..d4f9021 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -20,13 +20,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -40,11 +40,11 @@ RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 + RO_UNUSED@0x4000% 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..fbaca9b 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -4,9 +4,9 @@ IFWI@0x1000 0x1ff000 RO_VPD(PRESERVE)@0x200000 0x4000 RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 COREBOOT(CBFS)@0x1000 0x1ab000 GBB@0x1ac000 0x40000 RO_UNUSED@0x1ec000 0x10000 @@ -27,17 +27,17 @@ FPF_STATUS@0x3B000 0x1000 TMP_UNUSED_HOLE@0x3C000 0xE000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x44a000 0x478000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x467fc0 + RW_FWID_A@0x477fc0% 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8c2000 0x478000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x467fc0 + RW_FWID_B@0x477fc0% 0x40 } - RW_NVRAM(PRESERVE)@0xd39000 0x6000 + RW_NVRAM(PRESERVE)@0xd3a000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd index f4db8b4..037de53 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..a7a6b26 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xc1d800 + FMAP@0x300000% 0x800 + COREBOOT(CBFS)@0x300800% 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..3fe71e0 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,9 +1,9 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 - COREBOOT(CBFS)@0x321800 0x300000 - UNIFIED_MRC_CACHE@0x621800 0x21000 { + FMAP@0x321000% 0x800 + COREBOOT(CBFS)@0x321800% 0x300800 + UNIFIED_MRC_CACHE@0x622000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..9733567 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 - COREBOOT(CBFS)@0x301800 0x3dc800 + FMAP@0x301000% 0x800 + COREBOOT(CBFS)@0x301800% 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 923c8ee..5dec9ec 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x6f000 COREBOOT(CBFS)@0x70000 0x180000 } diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/wtm2/chromeos.fmd +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Gerrit-Change-Number: 37314 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43483 ) Change subject: Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ...................................................................... Documentation/vendorcode/eltan/security.md: Fix bugs in the guide ELTAN verified boot seems to be using vboot 2.1 key format not vboot 1.0. Generating vboot 1.0 keys results in public key of incorrect size (according to the verified boot implementation in vendorcode) which results in errors during booting. Fix the cbfstool extraction command to take account for stage file which may have certain sections removed. Add note about endianess of digest generated by openssl. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 --- M Documentation/vendorcode/eltan/security.md 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43483/1 diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md index 9dd47c0..1c05cd5 100644 --- a/Documentation/vendorcode/eltan/security.md +++ b/Documentation/vendorcode/eltan/security.md @@ -42,7 +42,7 @@ Create private key in RSA2048 format: `openssl genrsa -F4 -out <private_key_file> 2048` Create public key using private key: -`futility --vb1 create <private_key_file> <public_key_file_without_extension>` +`futility --vb21 create <private_key_file> <public_key_file_without_extension>` The public key will be included into coreboot and used for verified boot only. @@ -79,9 +79,15 @@ The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`. For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot -image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name>` +image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name> -m x86 -U` +Note the `-m x86 -U` flags are required for correct extraction of stages. Certain stages are +put in CBFS without certain program sections so extraction process must also remove these sections. + followed by: `openssl dgst -sha256 -binary -out <hash_file_name> <item_binary_file_name>` +The SHA256 digest will be in big endian so it must be converted to little endian with: +`< <hash_file_name> xxd -p -c1 | tac | xxd -p -r > <hash_file_name_le>` + Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled. All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as -- To view, visit https://review.coreboot.org/c/coreboot/+/43483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cf8e3f8e22876f671092fe4d3265a98564d996 Gerrit-Change-Number: 43483 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020