coreboot-gerrit November 2020

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Change in coreboot[master]: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/...
by Ryback Hung (Code Review) 10 Jun '23

10 Jun '23

Ryback Hung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40334 ) Change subject: configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. ...................................................................... configs/builder/config.ocp.sonorapass: Config for SonoraPass PO. src/mainboard/ocp/sonorapass/*.*: Preliminiary platform porting for SonoraPass PO. It can boot SonoraPass EVT board w/ ES1 CPX-SP and ES PCH. Due to IRQs issue, it has yet to boot into Linuxboot/u-root payload. Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b --- A configs/builder/config.ocp.sonorapass A src/mainboard/ocp/sonorapass/Kconfig A src/mainboard/ocp/sonorapass/Kconfig.name A src/mainboard/ocp/sonorapass/Makefile.inc A src/mainboard/ocp/sonorapass/acpi/platform.asl A src/mainboard/ocp/sonorapass/board.fmd A src/mainboard/ocp/sonorapass/board_info.txt A src/mainboard/ocp/sonorapass/bootblock.c A src/mainboard/ocp/sonorapass/devicetree.cb A src/mainboard/ocp/sonorapass/dsdt.asl 10 files changed, 320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40334/1 diff --git a/configs/builder/config.ocp.sonorapass b/configs/builder/config.ocp.sonorapass new file mode 100644 index 0000000..c05dce2 --- /dev/null +++ b/configs/builder/config.ocp.sonorapass @@ -0,0 +1,21 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.sonorapass + +CONFIG_VENDOR_OCP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/sonorapass/me.bin" +CONFIG_IFD_BIN_PATH="site-local/sonorapass/descriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/linuxboot_uroot_ttys0" +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x3f8,57600n1 console=uart8250,io,0x3f8,57600n1 loglevel=7" diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig new file mode 100644 index 0000000..34adf5f --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_OCP_SONORAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select IPMI_KCS + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default "ocp/sonorapass" + +config MAINBOARD_PART_NUMBER + string + default "SonoraPass" + +config MAINBOARD_FAMILY + string + default "SonoraPass" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name new file mode 100644 index 0000000..90e7f3d --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_SONORAPASS + bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc new file mode 100644 index 0000000..8501868 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += bootblock.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl new file mode 100644 index 0000000..75c1b92 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd new file mode 100644 index 0000000..e28bcf0 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board.fmd @@ -0,0 +1,10 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x2fd8000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fc5000 + } + FMAP@0x03000000 0x800 + RW_MRC_CACHE@0x3000800 0x10000 + COREBOOT(CBFS)@0x3010800 +} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt new file mode 100644 index 0000000..bbf3ee9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: SonoraPass +Category: server +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c new file mode 100644 index 0000000..06f45c9 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/bootblock.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F + +void bootblock_mainboard_early_init(void) +{ + struct config_data port80[] = { + /* {Type, base, reg, and, or} */ + /* Set command source of GPIOH to LPC */ + {MEM, ASPEED_GPIO_BASE, 0x68, 0xFEFFFFFF, 0x01000000}, + {MEM, ASPEED_GPIO_BASE, 0x6C, 0xFEFFFFFF, 0x00000000}, + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* Program GPIOH multi-function to GPIO */ + {MEM, ASPEED_SCU_BASE, 0x90, 0xFFFFFF3F, 0x00000000}, + /* Program GPIOH as output */ + {MEM, ASPEED_GPIO_BASE, 0x24, 0x00FFFFFF, 0xFF000000}, + /* Set snooping address#0 as 80h */ + {MEM, ASPEED_LPC_BASE, 0x90, 0xFFFF0000, 0x00000080}, + /* Enable snooping address#0 */ + {MEM, ASPEED_LPC_BASE, 0x80, 0xFFFFFFFE, 0x00000001}, + /* Enable GPIO device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_ENTRY_KEY}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, PORT80_GPIO_EN | ACTIVATE_VALUE}, + /* Select GPIOH for port80 GPIO */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, PORT80_GPIO_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, GPIOH_SEL}, + /* Disable GPIO Device */ + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, LDN_SEL}, + {SIO, 0, ASPEED_CONFIG_DATA, 0x00, AST2400_GPIO}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ACT_REG}, + {SIO, 0, ASPEED_CONFIG_DATA, 0xFE, DEACTIVATE_VALUE}, + {SIO, 0, ASPEED_CONFIG_INDEX, 0x00, ASPEED_EXIT_KEY} + }; + struct config_data uart[] = { + /* {Type, base, reg, and, or} */ + /* Unlock SCU Registers */ + {MEM, ASPEED_SCU_BASE, 0x00, 0x00000000, 0x1688A8A8}, + /* SERIAL PORT1 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0xFF00FFFF, 0x00C00000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + /* SERIAL PORT2 */ + {MEM, ASPEED_SCU_BASE, 0x84, 0x00FFFFFF, 0xC0000000}, + {MEM, ASPEED_GPIO_BASE, 0x90, 0xFFFFFFCF, 0x00000000}, + }; + + /* Enable COM1 only */ + pcr_write32(PID_DMI, 0x2770, 0); + pcr_write32(PID_DMI, 0x2774, 1); + + /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + aspeed_early_config(ASPEED_CONFIG_INDEX, port80, ARRAY_SIZE(port80)); + + /* Init UART */ + aspeed_early_config(ASPEED_CONFIG_INDEX, uart, ARRAY_SIZE(uart)); +} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000..fff834a --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,53 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + end + + end +end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl new file mode 100644 index 0000000..3dc45d5 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +#include <soc/iomap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> + #include <soc/intel/common/block/acpi/acpi/lpc.asl> + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60452205d666fd19582780401ccd9d7773e68a5b Gerrit-Change-Number: 40334 Gerrit-PatchSet: 1 Gerrit-Owner: Ryback Hung <ryback.hung%quantatw.com(a)gtempaccount.com> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: soc/intel/tigerlake: move mainboard_silicon_init_params
by Shaunak Saha (Code Review) 10 Jun '23

10 Jun '23

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44262 ) Change subject: soc/intel/tigerlake: move mainboard_silicon_init_params ...................................................................... soc/intel/tigerlake: move mainboard_silicon_init_params This patch arranges mainboard_silicon_init_params before fetching any config variables from devicetree. This would allow the variant specific devicetree overrides to get consumed so that FSP UPD parameters are initialized properly before SiliconInit. BUG=b:158573805 TEST=Test that UPD values are set properly with variant specific overrides of config's . Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Idfce528efa7806e292071e092fb129b53a94a145 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44262/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a61a025..5178d91 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -107,6 +107,8 @@ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + mainboard_silicon_init_params(params); + /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable; cpu_id = cpu_get_cpuid(); @@ -311,7 +313,6 @@ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; - mainboard_silicon_init_params(params); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfce528efa7806e292071e092fb129b53a94a145 Gerrit-Change-Number: 44262 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/emulation/qemu-armv7/memlayout: Move regions
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44395 ) Change subject: mb/emulation/qemu-armv7/memlayout: Move regions ...................................................................... mb/emulation/qemu-armv7/memlayout: Move regions Move pre RAM regions into SRAM. Tested using uImage/FIT, still boots into GNU/Linux 5.5.7. Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-armv7/memlayout.ld 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44395/1 diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index b0408ed..c1e99eb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,19 +28,19 @@ REGION(nor_flash1, 0x40000000, 0x4000000, 4K) REGION(nor_flash2, 0x44000000, 0x4000000, 4K) SRAM_START(0x48000000) + STACK(0x48000000, 64K) + FMAP_CACHE(0x48010000, 4K) + TIMESTAMP(0x48011000, 1K) + TTB_SUBTABLES(0x48012000, 4K) + TTB(0x48014000, 32K) + BOOTBLOCK(0x48020000, 128K) + ROMSTAGE(0x48040000, 128K) SRAM_END(0x4C000000) REGION(videoram, 0x4c000000, 0x1000000, 4K) REGION(ethernet, 0x4e000000, 0x1000000, 4K) REGION(usb, 0x4f000000, 0x1000000, 4K) DRAM_START(0x60000000) - STACK(0x60000000, 64K) - BOOTBLOCK(0x60010000, 128K) - FMAP_CACHE(0x60030000, 4K) - TIMESTAMP(0x60031000, 1K) - TTB_SUBTABLES(0x60032000, 4K) - TTB(0x60034000, 32K) - ROMSTAGE(0x60040000, 128K) - RAMSTAGE(0x60060000, 16M) - POSTRAM_CBFS_CACHE(0x61060000, 8M) + RAMSTAGE(0x60000000, 16M) + POSTRAM_CBFS_CACHE(0x61000000, 8M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/44395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b3664f018eded576262cf7b52a94dcd6d4f346 Gerrit-Change-Number: 44395 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/tigerlake: Clean up report_cpu_info() function
by Alexey Buyanov (Code Review) 10 Jun '23

10 Jun '23

Alexey Buyanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44050 ) Change subject: soc/intel/tigerlake: Clean up report_cpu_info() function ...................................................................... soc/intel/tigerlake: Clean up report_cpu_info() function This patch uses the fill_processor_name function in order to fetch the CPU Name. BUG=none TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov(a)intel.com> Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 --- M src/soc/intel/tigerlake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44050/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6acc0c3..d715725 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -10,6 +10,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/mp_init.h> @@ -99,35 +100,14 @@ static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - const char cpu_not_found[] = "Platform info not available"; - const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax >= 0x80000004) { - int j = 0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12] = 0; - cpu_name = (char *)p; - - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) - cpu_name++; - } + fill_processor_name(cpu_name); microcode_ver.lo = 0; microcode_ver.hi = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97be5d6b0a6fc5785c10ace3b78a1bc9c9f31230 Gerrit-Change-Number: 44050 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Buyanov <alexey.buyanov(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/intel/tglrvp: Enable CSE Firmware Lite SKU
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Jamie Ryu, Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44853 to review the following change. Change subject: mb/intel/tglrvp: Enable CSE Firmware Lite SKU ...................................................................... mb/intel/tglrvp: Enable CSE Firmware Lite SKU BUG=None BRANCH=None TEST=Build and boot tglrvp with CSE Lite and Consumer SKU Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44853/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 3e55f56..2ad6e79 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -18,6 +18,7 @@ select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select SOC_INTEL_CSE_LITE_SKU config CHROMEOS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/44853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78b2000acad24314d239d32ee60b5c6583aae363 Gerrit-Change-Number: 44853 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: prodrive/hermes: Disable USB power on S5
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44526 ) Change subject: prodrive/hermes: Disable USB power on S5 ...................................................................... prodrive/hermes: Disable USB power on S5 Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/dsdt.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44526/1 diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 4d8d170..c1bed5f 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -20,6 +20,16 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } + Method (MPTS,1) { + if (Arg0 == 5) { + /* Disable USB power on S5 */ + \_SB.PCI0.CTXS(GPP_G0) + \_SB.PCI0.CTXS(GPP_G1) + \_SB.PCI0.CTXS(GPP_G2) + \_SB.PCI0.CTXS(GPP_G3) + \_SB.PCI0.CTXS(GPP_G4) + } + } } #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/44526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d78e8966b7ccc06b04045fda6bda36eab464051 Gerrit-Change-Number: 44526 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mtrr.h: refine _POW2_MASK
by ky0ko (Code Review) 10 Jun '23

10 Jun '23

ky0ko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44845 ) Change subject: mtrr.h: refine _POW2_MASK ...................................................................... mtrr.h: refine _POW2_MASK this patch adjusts _POW2_MASK to work with rom sizes between 64KiB and 512MiB, additionally fixing incorrectness for sizes 128MiB and above that previously were present. Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Signed-off-by: ky0ko <ky0ko(a)disroot.org> --- M src/include/cpu/x86/mtrr.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44845/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b0..fd4159d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -176,9 +176,11 @@ #endif /* !defined(__ASSEMBLER__) */ /* Align up/down to next power of 2, suitable for assembler - too. Range of result 256kB to 128MB is good enough here. */ + too. Range works from 64kB to 512MB. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ - (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) + (x>>6)|(x>>7)|(x>>8)|(x>>9)|(x>>10)| \ + (x>>11)|(x>>12)|(x>>13)|((1<<16)-1)) + #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/44845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75 Gerrit-Change-Number: 44845 Gerrit-PatchSet: 1 Gerrit-Owner: ky0ko <ky0ko(a)disroot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 10 Jun '23

10 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44071 ) Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer This brings in Bay Trail support. Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44071/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf2..729fff7 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit 729fff7de5070bbfd2975065549b1f9fbf057976 -- To view, visit https://review.coreboot.org/c/coreboot/+/44071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b265862e2a7cce8e3d272dee9d22aba8358fa5 Gerrit-Change-Number: 44071 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/volteer: Disable Precision Time Measurement for PCIe RP 9
by Shreesh Chhabbi (Code Review) 10 Jun '23

10 Jun '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45302 to review the following change. Change subject: mb/volteer: Disable Precision Time Measurement for PCIe RP 9 ...................................................................... mb/volteer: Disable Precision Time Measurement for PCIe RP 9 Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45302/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1b8b0d6..eb1f1a9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -99,6 +99,9 @@ register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" + # PCIe RP PTM + register "PciePtm[8]" = "0" + # Enable SATA register "SataEnable" = "1" register "SataMode" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/45302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id42d0485a5ff8cb2c1886c460e6ec2f1fb540516 Gerrit-Change-Number: 45302 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Read spds only once if measured boot is enabled
by Bill XIE (Code Review) 10 Jun '23

10 Jun '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39969 ) Change subject: nb/intel/sandybridge: Read spds only once if measured boot is enabled ...................................................................... nb/intel/sandybridge: Read spds only once if measured boot is enabled Without considering s3 resume, spd may be used various times depending on various condition. If spd is stored in CBFS and read various times, PCR value may become inconsistent. As mentioned in CB:39906, in order to avoid this, we could read spd exactly once, and use the data read out various times, when measured boot is enabled. Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39969/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11..f3c81a6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -98,6 +98,17 @@ } } +static bool spd_is_available(const spd_raw_data spds[], size_t num_spd) +{ + /* An available spd should at least have an non-zero id */ + size_t i, j, sum = 0; + for (i = 0; i < num_spd; i++) { + for (j = 117; j < 128; j++) + sum += spds[i][j]; + } + return (sum > 0); +} + static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; @@ -222,6 +233,8 @@ struct region_device rdev; ramctr_timing *ctrl_cached = NULL; + if (CONFIG(TPM_MEASURED_BOOT)) + memset(spds, 0, sizeof(spds)); MCHBAR32(SAPMCTL) |= 1; /* Wait for ME to be ready */ @@ -271,8 +284,14 @@ /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { /* Load SPD unique information data. */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 1); + if (CONFIG(TPM_MEASURED_BOOT)) { + /* if CONFIG(TPM_MEASURED_BOOT), + we manage to get spds only ONCE */ + mainboard_get_spd(spds, 0); + } else { + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 1); + } /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); @@ -307,8 +326,12 @@ ctrl.cpu = cpuid; /* Get DDR3 SPD data */ - memset(spds, 0, sizeof(spds)); - mainboard_get_spd(spds, 0); + if (!CONFIG(TPM_MEASURED_BOOT) || !spd_is_available(spds, 4)) { + /* without CONFIG(TPM_MEASURED_BOOT), the previous read may + only contains id, so read it again */ + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds, 0); + } dram_find_spds_ddr3(spds, &ctrl); err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/39969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02cad7e85d5e66fd9efb674e4dc9868233f6c233 Gerrit-Change-Number: 39969 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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