coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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3243 discussions

Change in coreboot[master]: mb/ocp/deltalake: Configure GPIO
by Jingle Hsu (Code Review) 26 Nov '20

26 Nov '20

Hello Marc Jones, Maxim Polyakov, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Bryant Ou, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47229 to look at the new patch set (#5). Change subject: mb/ocp/deltalake: Configure GPIO ...................................................................... mb/ocp/deltalake: Configure GPIO On Delta Lake DVT with original UEFI firmware, dump GPIO settings by util/inteltool and generate header file by util/intelp2m. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h A src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio_dvt.h 2 files changed, 565 insertions(+), 244 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47229/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 5 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: Configure GPIO
by Jingle Hsu (Code Review) 26 Nov '20

26 Nov '20

Hello Marc Jones, Maxim Polyakov, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Bryant Ou, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47229 to look at the new patch set (#4). Change subject: mb/ocp/deltalake: Configure GPIO ...................................................................... mb/ocp/deltalake: Configure GPIO On Delta Lake DVT with original UEFI firmware, dump GPIO settings by util/inteltool and generate header file by util/intelp2m. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/bootblock.c A src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio_dvt.h M src/mainboard/ocp/deltalake/ramstage.c 4 files changed, 332 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47229/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 4 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by Aamir Bohra (Code Review) 26 Nov '20

26 Nov '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Nov 2020 05:38:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlp: Add support for LPDDR5
by V Sowmya (Code Review) 26 Nov '20

26 Nov '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlp: Add support for LPDDR5 ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 26 Nov 2020 05:38:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlp: Add support for LPDDR5
by Aamir Bohra (Code Review) 26 Nov '20

26 Nov '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlp: Add support for LPDDR5 ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 26 Nov 2020 05:38:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by V Sowmya (Code Review) 26 Nov '20

26 Nov '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Nov 2020 05:37:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl: correct OC pin skip value for disabled usb ports
by Michael Niewöhner (Code Review) 25 Nov '20

25 Nov '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48003 to look at the new patch set (#3). Change subject: soc/intel/skl: correct OC pin skip value for disabled usb ports ...................................................................... soc/intel/skl: correct OC pin skip value for disabled usb ports Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48003/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Gerrit-Change-Number: 48003 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Paul Menzel (Code Review) 25 Nov '20

25 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47892/3/Documentation/mainboard/sy… File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/3/Documentation/mainboard/sy… PS3, Line 72: Please remove blank lines at the end of the file. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Nov 2020 21:39:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create galtic variant
by Paul Fagerburg (Code Review) 25 Nov '20

25 Nov '20

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47900 ) Change subject: mb/google/dedede: Create galtic variant ...................................................................... mb/google/dedede: Create galtic variant Create the galtic variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:170913840 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_GALTIC Signed-off-by: FrankChu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900 Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/galtic/include/variant/ec.h A src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h A src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc A src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/galtic/overridetree.cb 8 files changed, 77 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Fagerburg: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6c4f456..9f662a4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -96,6 +96,7 @@ default "Magolor" if BOARD_GOOGLE_MAGOLOR default "Metaknight" if BOARD_GOOGLE_METAKNIGHT default "Lantis" if BOARD_GOOGLE_LANTIS + default "Galtic" if BOARD_GOOGLE_GALTIC config MAX_CPUS int @@ -127,5 +128,6 @@ default "magolor" if BOARD_GOOGLE_MAGOLOR default "metaknight" if BOARD_GOOGLE_METAKNIGHT default "lantis" if BOARD_GOOGLE_LANTIS + default "galtic" if BOARD_GOOGLE_GALTIC endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 2a8950c..c8ce003 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -78,3 +78,8 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + +config BOARD_GOOGLE_GALTIC + bool "-> Galtic" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt new file mode 100644 index 0000000..59381dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Gerrit-Change-Number: 47900 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create galtic variant
by Martin Roth (Code Review) 25 Nov '20

25 Nov '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47900 ) Change subject: mb/google/dedede: Create galtic variant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Gerrit-Change-Number: 47900 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Nov 2020 21:28:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020