coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by Subrata Banik (Code Review) 26 Nov '20

26 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/in… File src/soc/intel/alderlake/include/soc/meminit.h: https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/in… PS4, Line 95: Bit Mark:Bits [7:0] > What is a *bit mark*? Ack https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/in… PS4, Line 96: Ascending > lowercase? Ack https://review.coreboot.org/c/coreboot/+/47436/4/src/soc/intel/alderlake/in… PS4, Line 96: CCC > What does CCC stand for? CA, CTL, CLK? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Nov 2020 19:22:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for LPDDR5
by Subrata Banik (Code Review) 26 Nov '20

26 Nov '20

Subrata Banik has uploaded a new patch set (#13) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlrvp: Add support for LPDDR5 ...................................................................... mb/intel/adlrvp: Add support for LPDDR5 This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex 5 files changed, 71 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46899/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add lp5_ccc_config to the board memory configura...
by Subrata Banik (Code Review) 26 Nov '20

26 Nov '20

Subrata Banik has uploaded a new patch set (#5) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/47436 ) Change subject: soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration ...................................................................... soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a --- M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47436/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Gerrit-Change-Number: 47436 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1481_11
by Subrata Banik (Code Review) 26 Nov '20

26 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47901 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1481_11 ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1481_11 List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 88 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47901/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index da746ba..0e9ca02 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -524,18 +524,18 @@ /** Offset 0x0241 - Reserved **/ - UINT8 Reserved14[143]; + UINT8 Reserved14[141]; -/** Offset 0x02D0 - DMI Gen3 Root port preset values per lane +/** Offset 0x02CE - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 DmiGen3RootPortPreset[8]; -/** Offset 0x02D8 - Reserved +/** Offset 0x02D6 - Reserved **/ UINT8 Reserved15[150]; -/** Offset 0x036E - C6DRAM power gating feature +/** Offset 0x036C - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. @@ -543,314 +543,314 @@ **/ UINT8 EnableC6Dram; -/** Offset 0x036F - Reserved +/** Offset 0x036D - Reserved **/ UINT8 Reserved16[5]; -/** Offset 0x0374 - Hyper Threading Enable/Disable +/** Offset 0x0372 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_DIS **/ UINT8 HyperThreading; -/** Offset 0x0375 - Reserved +/** Offset 0x0373 - Reserved **/ UINT8 Reserved17; -/** Offset 0x0376 - CPU ratio value +/** Offset 0x0374 - CPU ratio value CPU ratio value. Valid Range 0 to 63 **/ UINT8 CpuRatio; -/** Offset 0x0377 - Reserved +/** Offset 0x0375 - Reserved **/ UINT8 Reserved18[2]; -/** Offset 0x0379 - Processor Early Power On Configuration FCLK setting +/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x037A - Reserved +/** Offset 0x0378 - Reserved **/ UINT8 Reserved19; -/** Offset 0x037B - Enable or Disable VMX +/** Offset 0x0379 - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x037C - Reserved +/** Offset 0x037A - Reserved **/ UINT8 Reserved20[20]; -/** Offset 0x0390 - Enable or Disable TME +/** Offset 0x038E - Enable or Disable TME Enable or Disable TME; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TmeEnable; -/** Offset 0x0391 - Reserved +/** Offset 0x038F - Reserved **/ - UINT8 Reserved21[13]; + UINT8 Reserved21[11]; -/** Offset 0x039E - BiosGuard +/** Offset 0x039A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x039F +/** Offset 0x039B **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x03A0 - Reserved +/** Offset 0x039C - Reserved **/ UINT8 Reserved22[4]; -/** Offset 0x03A4 - PrmrrSize +/** Offset 0x03A0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x03A8 - SinitMemorySize +/** Offset 0x03A4 - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x03AC - Reserved +/** Offset 0x03A8 - Reserved **/ - UINT8 Reserved23[12]; + UINT8 Reserved23[8]; -/** Offset 0x03B8 - TxtHeapMemorySize +/** Offset 0x03B0 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x03BC - TxtDprMemorySize +/** Offset 0x03B4 - TxtDprMemorySize Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x03C0 - Reserved +/** Offset 0x03B8 - Reserved **/ UINT8 Reserved24[614]; -/** Offset 0x0626 - Number of RsvdSmbusAddressTable. +/** Offset 0x061E - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0627 - Reserved +/** Offset 0x061F - Reserved **/ UINT8 Reserved25[4]; -/** Offset 0x062B - Usage type for ClkSrc +/** Offset 0x0623 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x063D - Reserved +/** Offset 0x0635 - Reserved **/ UINT8 Reserved26[14]; -/** Offset 0x064B - ClkReq-to-ClkSrc mapping +/** Offset 0x0643 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x065D - Reserved +/** Offset 0x0655 - Reserved **/ UINT8 Reserved27[91]; -/** Offset 0x06B8 - Enable PCIE RP Mask +/** Offset 0x06B0 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x06BC - Reserved +/** Offset 0x06B4 - Reserved **/ UINT8 Reserved28[2]; -/** Offset 0x06BE - Enable HD Audio Link +/** Offset 0x06B6 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x06BF - Reserved +/** Offset 0x06B7 - Reserved **/ UINT8 Reserved29[3]; -/** Offset 0x06C2 - Enable HD Audio DMIC_N Link +/** Offset 0x06BA - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x06C4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x06BC - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x06CC - DMIC<N> ClkB Pin Muxing +/** Offset 0x06C4 - DMIC<N> ClkB Pin Muxing Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x06D4 - Enable HD Audio DSP +/** Offset 0x06CC - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x06D5 - Reserved +/** Offset 0x06CD - Reserved **/ UINT8 Reserved30[3]; -/** Offset 0x06D8 - DMIC<N> Data Pin Muxing +/** Offset 0x06D0 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x06E0 - Enable HD Audio SSP0 Link +/** Offset 0x06D8 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x06E6 - Enable HD Audio SoundWire#N Link +/** Offset 0x06DE - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x06EA - iDisp-Link Frequency +/** Offset 0x06E2 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x06EB - iDisp-Link T-mode +/** Offset 0x06E3 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x06EC - iDisplay Audio Codec disconnection +/** Offset 0x06E4 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x06ED - Debug Interfaces +/** Offset 0x06E5 - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x06EE - Serial Io Uart Debug Controller Number +/** Offset 0x06E6 - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x06EF - Reserved +/** Offset 0x06E7 - Reserved **/ UINT8 Reserved31[13]; -/** Offset 0x06FC - ISA Serial Base selection +/** Offset 0x06F4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x06FD - Reserved +/** Offset 0x06F5 - Reserved **/ UINT8 Reserved32[4]; -/** Offset 0x0701 - MRC Safe Config +/** Offset 0x06F9 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x0702 - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x06FA - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x0703 - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x06FB - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x0704 - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x06FC - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x0705 - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x06FD - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x0706 - TCSS USB HOST (xHCI) Enable +/** Offset 0x06FE - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x0707 - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x06FF - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x0708 - TCSS DMA0 Enable +/** Offset 0x0700 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x0709 - TCSS DMA1 Enable +/** Offset 0x0701 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x070A - Reserved +/** Offset 0x0702 - Reserved **/ UINT8 Reserved33[2]; -/** Offset 0x070C - Early Command Training +/** Offset 0x0704 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x070D - Reserved +/** Offset 0x0705 - Reserved **/ UINT8 Reserved34[65]; -/** Offset 0x074E - Ch Hash Mask +/** Offset 0x0746 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0750 - Reserved +/** Offset 0x0748 - Reserved **/ UINT8 Reserved35[64]; -/** Offset 0x0790 - PcdSerialDebugLevel +/** Offset 0x0788 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -859,89 +859,89 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0791 - Reserved +/** Offset 0x0789 - Reserved **/ UINT8 Reserved36[2]; -/** Offset 0x0793 - Safe Mode Support +/** Offset 0x078B - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x0794 - Reserved +/** Offset 0x078C - Reserved **/ UINT8 Reserved37[2]; -/** Offset 0x0796 - TCSS USB Port Enable +/** Offset 0x078E - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x0797 - Reserved +/** Offset 0x078F - Reserved **/ UINT8 Reserved38[35]; -/** Offset 0x07BA - Command Pins Mapping +/** Offset 0x07B2 - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x07BB - Reserved +/** Offset 0x07B3 - Reserved **/ UINT8 Reserved39[14]; -/** Offset 0x07C9 - Skip external display device scanning +/** Offset 0x07C1 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x07CA - Reserved +/** Offset 0x07C2 - Reserved **/ UINT8 Reserved40; -/** Offset 0x07CB - Lock PCU Thermal Management registers +/** Offset 0x07C3 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x07CC - Reserved +/** Offset 0x07C4 - Reserved **/ UINT8 Reserved41[129]; -/** Offset 0x084D - Skip CPU replacement check +/** Offset 0x0845 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x084E - Reserved +/** Offset 0x0846 - Reserved **/ UINT8 Reserved42[292]; -/** Offset 0x0972 - Serial Io Uart Debug Mode +/** Offset 0x096A - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0973 - Reserved +/** Offset 0x096B - Reserved **/ UINT8 Reserved43[183]; -/** Offset 0x0A2A - GPIO Override +/** Offset 0x0A22 - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use **/ UINT8 GpioOverride; -/** Offset 0x0A2B - Reserved +/** Offset 0x0A23 - Reserved **/ UINT8 Reserved44[349]; } FSP_M_CONFIG; @@ -962,12 +962,11 @@ **/ FSP_M_CONFIG FspmConfig; - -/** Offset 0x0B88 +/** Offset 0x0B80 **/ - UINT8 UnusedUpdSpace32[6]; + UINT8 UnusedUpdSpace29[6]; -/** Offset 0x0B8E +/** Offset 0x0B86 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 38945d0..14d29db 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -865,7 +865,7 @@ /** Offset 0x1200 **/ - UINT8 UnusedUpdSpace46[6]; + UINT8 UnusedUpdSpace44[6]; /** Offset 0x1206 **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/47901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Gerrit-Change-Number: 47901 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: lenovo/g505s: add the PIRQ tables [WIP]
by Mike Banon (Code Review) 26 Nov '20

26 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48076 ) Change subject: lenovo/g505s: add the PIRQ tables [WIP] ...................................................................... lenovo/g505s: add the PIRQ tables [WIP] [WIP] - ideally, not to merge separately without CB:47852's main part. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0874d1f7d78b93ad308212d15a1a9eb2d76acb11 --- M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/irq_tables.c 2 files changed, 58 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48076/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 322d3a7..75ae32c 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -11,6 +11,7 @@ select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER @@ -47,4 +48,8 @@ string default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS +config IRQ_SLOT_COUNT + int + default 14 + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 0baf079..3898a72 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,88 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x4, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x780b, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x87, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* IOMMU: 0:02.00 - IRQ 3 */ + {0x00, (0x00 << 3) | 0x2, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {0x00, (0x02 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 3 */ + {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* USB XHCI: 0:10.00 - IRQ 5 */ + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* SATA: 0:11.00 - IRQ 7 */ + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + /* USB EHCI1: 0:12.02 - IRQ 4 */ + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + /* USB EHCI2: 0:13.02 - IRQ 4 */ + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + /* USB EHCI3: 0:16.02 - IRQ 4 */ + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + /* USB OHCI4: 0:14.05 - IRQ 5 */ + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0}, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + {0x01, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x1, 0x0}, + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + {0x02, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x2, 0x0}, + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + {0x03, (0x00 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90} }, 0x3, 0x0} + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0874d1f7d78b93ad308212d15a1a9eb2d76acb11 Gerrit-Change-Number: 48076 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/google/dedede: Create sasuke variant
by Raymond Chung (Code Review) 26 Nov '20

26 Nov '20

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48075 ) Change subject: mb/google/dedede: Create sasuke variant ...................................................................... mb/google/dedede: Create sasuke variant Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Change-Id: Idca86c713c7ff3860b13d2efb0e53df516ecd236 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h A src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h A src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc A src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/sasuke/overridetree.cb 8 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48075/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9f662a4..86921a2 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -97,6 +97,7 @@ default "Metaknight" if BOARD_GOOGLE_METAKNIGHT default "Lantis" if BOARD_GOOGLE_LANTIS default "Galtic" if BOARD_GOOGLE_GALTIC + default "Sasuke" if BOARD_GOOGLE_SASUKE config MAX_CPUS int @@ -129,5 +130,6 @@ default "metaknight" if BOARD_GOOGLE_METAKNIGHT default "lantis" if BOARD_GOOGLE_LANTIS default "galtic" if BOARD_GOOGLE_GALTIC + default "sasuke" if BOARD_GOOGLE_SASUKE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index c8ce003..cba8c9f 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -83,3 +83,10 @@ bool "-> Galtic" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_SASUKE + bool "-> Sasuke" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt new file mode 100644 index 0000000..59381dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb new file mode 100644 index 0000000..69ea1e1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + device domain 0 on + device pci 14.0 on end + device pci 15.0 on end + device pci 15.2 on end + device pci 1c.7 on end + device pci 19.0 on end + device pci 1f.3 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/48075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca86c713c7ff3860b13d2efb0e53df516ecd236 Gerrit-Change-Number: 48075 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/adlp: Add support for LPDDR5
by Subrata Banik (Code Review) 26 Nov '20

26 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlp: Add support for LPDDR5 ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/46899/12/src/mainboard/intel/adlrv… File src/mainboard/intel/adlrvp/memory.c: https://review.coreboot.org/c/coreboot/+/46899/12/src/mainboard/intel/adlrv… PS12, Line 62: 15, 14, 12, 13, 8, 9, 10, 11 }, /* Byte 1 */ > I’d also remove the comments. > > For the record (for myself), it’s an array: > > uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; yes, Paul its an array. we could put 0 and 1 in same line, its more about readability in code -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Nov 2020 13:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlp: Add support for LPDDR5
by Paul Menzel (Code Review) 26 Nov '20

26 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46899 ) Change subject: mb/intel/adlp: Add support for LPDDR5 ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/46899/12/src/mainboard/intel/adlrv… File src/mainboard/intel/adlrvp/memory.c: https://review.coreboot.org/c/coreboot/+/46899/12/src/mainboard/intel/adlrv… PS12, Line 62: 15, 14, 12, 13, 8, 9, 10, 11 }, /* Byte 1 */ > Should bytes 0 and 1 be put on one line? I’d also remove the comments. For the record (for myself), it’s an array: uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; -- To view, visit https://review.coreboot.org/c/coreboot/+/46899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Gerrit-Change-Number: 46899 Gerrit-PatchSet: 12 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Nov 2020 13:31:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86: Top align the bootblock
by Arthur Heymans (Code Review) 26 Nov '20

26 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47194 ) Change subject: arch/x86: Top align the bootblock ...................................................................... arch/x86: Top align the bootblock This removes the fixed C_ENV_BOOTBLOCK requirement for X86 systems. Change-Id: Ibd22ab394a38e73ba365b0796419b69e4bc0b45f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld M src/arch/x86/memlayout.ld M src/cpu/x86/16bit/reset16.ld 3 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/47194/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index eabe873..cbd5ceb 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -94,7 +94,7 @@ _car_mtrr_mask = ~(MAX(4096, _car_mtrr_sz_log2) - 1); #if !CONFIG(NO_XIP_EARLY_STAGES) -_xip_program_sz_log2 = 1 << LOG2CEIL(_ebootblock - _bootblock); +_xip_program_sz_log2 = 1 << LOG2CEIL(0x100000000 - _program); _xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1); #endif diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 3659cc9..c592a82 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,9 +28,6 @@ #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, - CONFIG_C_ENV_BOOTBLOCK_SIZE) - #include "car.ld" #elif ENV_POSTCAR diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index 97e70b9..755234a 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -12,6 +12,18 @@ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + .bogus PROGRAM_START : { + . = ALIGN(4); + } + + INCLUDE "bootblock/lib/program.ld" + + /* + * Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + .bogus ROMLOC_MIN : { . = ALIGN(4); } @@ -32,8 +44,13 @@ } EARLYASM_SIZE = (_erealmode - _realmode); +PROGRAM_SIZE = (_eprogram - _program); /* Assume that 0xf0 below the reset vector (size 0x10), so 0x100 in total is * not available for code. */ ROMLOC_MIN = ALIGN_DOWN(CONFIG_X86_RESET_VECTOR - RESERVED_BELOW_RESET - EARLYASM_SIZE, \ REALMODE_ALIGNMENT); +/* With Intel CbNT or Bootguard the IBB alignment needs to be 64 bytes. + * Not much is lost to do this for all systems. + */ +PROGRAM_START = ALIGN_DOWN(ROMLOC_MIN - PROGRAM_SIZE, 64); -- To view, visit https://review.coreboot.org/c/coreboot/+/47194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd22ab394a38e73ba365b0796419b69e4bc0b45f Gerrit-Change-Number: 47194 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Remove 64KiB bootblock limit
by Arthur Heymans (Code Review) 26 Nov '20

26 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47193 ) Change subject: arch/x86: Remove 64KiB bootblock limit ...................................................................... arch/x86: Remove 64KiB bootblock limit X86 CPU start by executing the reset vector in 16bit real mode. The first instruction, called the reset vector is a jump instruction. Since this is 16bit the jump needs to remain in the 64KiB section. This adds a section to the linker script for code that needs to remain close enough to the reset vector. As soon as we are in 32bit protected mode we can jump anywhere else in the bootblock. This removes the 64KiB limit on the C_ENV_BOOTBLOCK_SIZE. For systems where the SIPI vector is in ROM the alignment of the _start16bit symbol is handled in the linker script instead of the assembly code. Change-Id: I192fd08311fccf2e73a70799de2b028a9c8c4a40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/bootblock_crt0.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld 3 files changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47193/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3f41464..389dd55 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,16 +10,18 @@ #include <cpu/x86/cr.h> -.section .text - /* * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ +.section ".bootblock.top", "ax", @progbits #include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> + jmp continue_text +.section .text +continue_text: #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12be..86c14a0 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -31,7 +31,6 @@ /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index b90dd04..97e70b9 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -2,11 +2,27 @@ /* _RESET_VECTOR: typically the top of the ROM */ +#define ALIGN_DOWN(loc, size) ((loc) / (size) * (size)) + +#define REALMODE_ALIGNMENT (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16) +#define RESERVED_BELOW_RESET 0xf0 + SECTIONS { /* Trigger an error if I have an unuseable start address */ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + .bogus ROMLOC_MIN : { + . = ALIGN(4); + } + + .bootblock_top . : { + . = ALIGN(REALMODE_ALIGNMENT); + _realmode = .; + *(.bootblock.top); + _erealmode = .; + } + . = CONFIG_X86_RESET_VECTOR; .reset . : { *(.reset); @@ -14,3 +30,10 @@ BYTE(0x00); } } + +EARLYASM_SIZE = (_erealmode - _realmode); +/* Assume that 0xf0 below the reset vector (size 0x10), so 0x100 in total is + * not available for code. + */ +ROMLOC_MIN = ALIGN_DOWN(CONFIG_X86_RESET_VECTOR - RESERVED_BELOW_RESET - EARLYASM_SIZE, \ + REALMODE_ALIGNMENT); -- To view, visit https://review.coreboot.org/c/coreboot/+/47193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I192fd08311fccf2e73a70799de2b028a9c8c4a40 Gerrit-Change-Number: 47193 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020