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Change in coreboot[master]: Documentation/soc/amd: Add family 15h
by Richard Spiegel (Code Review) 01 Oct '19

01 Oct '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34561 ) Change subject: Documentation/soc/amd: Add family 15h ...................................................................... Documentation/soc/amd: Add family 15h Create documentation for AMD family 15h, and in particular to models for which there's coreboot code: Models 60h-6Fh and 70h-7Fh. BUG=none. TEST=none. Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/soc/amd/family15h.md M Documentation/soc/amd/index.md 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34561/1 diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md new file mode 100644 index 0000000..2e583e8 --- /dev/null +++ b/Documentation/soc/amd/family15h.md @@ -0,0 +1,44 @@ +# AMD Family 15h in coreboot + +## Abstract + +Family 15h uses the AMD CPU micro architecture _Excavator_, and is available +in several models with different number of cores and some other small +variations, to attend a broad spectrum of users. Of particular interest for +coreboot are models **60h-6Fh** (_Merlin Falcon_) and **70h-7Fh** (_Stoney Ridge_), +for which there are coreboot implementations. + +## Introduction + +Family 15h products are x86-based designs. This documentation assumes +familiarity with x86, its reset state and its early initialization requirements. + +AMD has historically required an NDA for access to the PSP specification. +coreboot relies on util/amdfwtool to build the structures and add various +other firmware to the final image. + +Support in coreboot for modern AMD products is based on AMD’s +reference code: AMD Generic Encapsulated Software Architecture +(AGESA _**TM**_). AGESA contains the technology for enabling DRAM, +configuring proprietary core logic, assistance with generating ACPI +tables, and other features. + +Some functionality, such as GPIO setting and D0/D3 of some devices such as +I2C and UART were removed from AGESA (though still available on most AGESA +images) and converted to coreboot code for granularity, speed and easy of +use reasons. +>In particular, GPIO achieved a greater control over what is being +>programmed through the use of a table that is easily created using +>macros. + +## Additional Definitions + +* PSP, Platform Security Processor: Onboard ARM processor that runs +alongside the main x86 processor; may be viewed as analogous to the +Intel<sup>R</sup> Management Engine +* FCH, Fusion Control Hub, the logical southbridge within the SOC + +## References + +1. [Merlin Falcon BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BK… +2. [Stoney Ridge BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models… diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index 7945b48..d6f31c8 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -4,5 +4,6 @@ ## Technology +- [Family 15h](family15h.md) - [Family 17h](family17h.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/34561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Gerrit-Change-Number: 34561 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

5 43

Change in ...coreboot[master]: mediatek/mt8183: allow modifying vcore voltage
by hsin-hsiung wang (Code Review) 01 Oct '19

01 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33391 Change subject: mediatek/mt8183: allow modifying vcore voltage ...................................................................... mediatek/mt8183: allow modifying vcore voltage Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33391/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index c90e6e4..f213c35 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -25,6 +25,9 @@ PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, + PMIC_VCORE_OP_EN = 0x1490, + PMIC_VCORE_DBG0 = 0x149e, + PMIC_VCORE_VOSEL = 0x14aa, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, PMIC_VDRAM1_OP_EN = 0x1610, PMIC_VDRAM1_DBG0 = 0x161e, @@ -43,5 +46,7 @@ void pmic_set_power_hold(bool enable); unsigned int pmic_get_vdram1_vol(void); void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vcore_vol(void); +void pmic_set_vcore_vol(unsigned int vcore_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 409369f..eff0543 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -756,6 +756,29 @@ pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); } +unsigned int pmic_get_vcore_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +void pmic_set_vcore_vol(unsigned int vcore_uv) +{ + unsigned int vol_reg; + + if (vcore_uv < 500000) + vol_reg = 0; + else if (vcore_uv > 1100000) + vol_reg = 0x60; + else + vol_reg = (vcore_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Gerrit-Change-Number: 33391 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

5 16

Change in ...coreboot[master]: sb/intel/bd82x6x: Use common final SPI OPs setup
by Arthur Heymans (Code Review) 30 Sep '19

30 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33040 Change subject: sb/intel/bd82x6x: Use common final SPI OPs setup ...................................................................... sb/intel/bd82x6x: Use common final SPI OPs setup This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/lpc.c 3 files changed, 24 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33040/1 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59df..1ad58b8 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -56,7 +56,14 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" - register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }" + register "spi.ops" = "{ {0x01, WRITE_NO_ADDR }, + {0x02, WRITE_WITH_ADDR }, + {0x03, READ_WITH_ADDR }, + {0x05, READ_NO_ADDR }, + {0x20, WRITE_WITH_ADDR }, + {0x9f, READ_NO_ADDR }, + {0xad, WRITE_NO_ADDR }, + {0x04, WRITE_NO_ADDR } }" device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 29f6881..d04cbec 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <southbridge/intel/common/spi.h> #include <stdint.h> struct southbridge_intel_bd82x6x_config { @@ -97,14 +98,7 @@ uint32_t spi_uvscc; uint32_t spi_lvscc; - struct { - uint8_t opprefixes[2]; - struct { - uint8_t needs_address; - uint8_t is_write; - uint8_t op; - } ops[8]; - } spi; + struct intel_spi_config spi; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7737501..9615698 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -38,6 +38,7 @@ #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -875,34 +876,6 @@ static void lpc_final(struct device *dev) { - u16 spi_opprefix = SPI_OPPREFIX; - u16 spi_optype = SPI_OPTYPE; - u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }; - - /* Configure SPI opcode menu; devicetree may override defaults. */ - const config_t *const config = dev->chip_info; - if (config && config->spi.ops[0].op) { - unsigned int i; - - spi_opprefix = 0; - spi_optype = 0; - spi_opmenu[0] = 0; - spi_opmenu[1] = 0; - for (i = 0; i < sizeof(spi_opprefix); ++i) - spi_opprefix |= config->spi.opprefixes[i] << i * 8; - for (i = 0; i < sizeof(spi_opmenu); ++i) { - spi_optype |= - config->spi.ops[i].is_write << 2 * i | - config->spi.ops[i].needs_address << (2 * i + 1); - spi_opmenu[i / 4] |= - config->spi.ops[i].op << (i % 4) * 8; - } - } - RCBA16(0x3894) = spi_opprefix; - RCBA16(0x3896) = spi_optype; - RCBA32(0x3898) = spi_opmenu[0]; - RCBA32(0x389c) = spi_opmenu[1]; - /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || @@ -918,6 +891,19 @@ } } +void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + /* Devicetree may override defaults. */ + const config_t *const config = dev->chip_info; + + if (config) + return; + + if (config->spi.ops[0].op != 0) + memcpy(spi_config, &config->spi, sizeof(config->spi)); +} + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/33040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Gerrit-Change-Number: 33040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: SPM: mt8183: support spm suspend in coreboot
by DAWEI CHIEN (Code Review) 30 Sep '19

30 Sep '19

DAWEI CHIEN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34545 ) Change subject: SPM: mt8183: support spm suspend in coreboot ...................................................................... SPM: mt8183: support spm suspend in coreboot Load SPM firmware and init SPM in core boot Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/spm.h A src/soc/mediatek/mt8183/include/soc/spm_init.h M src/soc/mediatek/mt8183/soc.c A src/soc/mediatek/mt8183/spm.c 5 files changed, 2,499 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/34545/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 0a79ed7..bc8085b 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -50,11 +50,22 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += sspm.c +ramstage-y += spm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +cbfs-files-y += pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-type := raw +pcm_allinone_lp4_3200.bin-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-type := raw +pcm_allinone_lp4_3733.bin-compression := $(CBFS_COMPRESS_FLAG) + CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 5e7770e..290f99c 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -473,24 +473,66 @@ u32 spm_ack_chk_latch4; }; +check_member(mtk_spm_regs, poweron_config_set, 0x0000); +check_member(mtk_spm_regs, spm_power_on_val0, 0x0004); +check_member(mtk_spm_regs, spm_power_on_val1, 0x0008); +check_member(mtk_spm_regs, spm_clk_con, 0x000c); +check_member(mtk_spm_regs, pcm_con0, 0x0018); +check_member(mtk_spm_regs, pcm_con1, 0x001c); +check_member(mtk_spm_regs, pcm_im_ptr, 0x0020); +check_member(mtk_spm_regs, pcm_im_len, 0x0024); +check_member(mtk_spm_regs, pcm_reg_data_ini, 0x0028); +check_member(mtk_spm_regs, pcm_pwr_io_en, 0x002c); +check_member(mtk_spm_regs, pcm_im_host_rw_ptr, 0x0038); +check_member(mtk_spm_regs, pcm_im_host_rw_dat, 0x003c); +check_member(mtk_spm_regs, pcm_event_vector0, 0x0040); +check_member(mtk_spm_regs, pcm_event_vector1, 0x0044); +check_member(mtk_spm_regs, pcm_event_vector2, 0x0048); +check_member(mtk_spm_regs, pcm_event_vector3, 0x004c); +check_member(mtk_spm_regs, pcm_event_vector4, 0x0050); +check_member(mtk_spm_regs, pcm_event_vector5, 0x0054); +check_member(mtk_spm_regs, pcm_event_vector6, 0x0058); +check_member(mtk_spm_regs, pcm_event_vector7, 0x005c); +check_member(mtk_spm_regs, pcm_event_vector8, 0x0060); +check_member(mtk_spm_regs, pcm_event_vector9, 0x0064); +check_member(mtk_spm_regs, pcm_event_vector10, 0x0068); +check_member(mtk_spm_regs, pcm_event_vector11, 0x006c); +check_member(mtk_spm_regs, pcm_event_vector12, 0x0070); +check_member(mtk_spm_regs, pcm_event_vector13, 0x0074); +check_member(mtk_spm_regs, pcm_event_vector14, 0x0078); +check_member(mtk_spm_regs, pcm_event_vector15, 0x007c); +check_member(mtk_spm_regs, spm_swint_clr, 0x0094); +check_member(mtk_spm_regs, spm_cpu_wakeup_event, 0x00b0); +check_member(mtk_spm_regs, spm_irq_mask, 0x00b4); +check_member(mtk_spm_regs, spm_wakeup_event_mask, 0x00c4); +check_member(mtk_spm_regs, ddr_en_dbc_len, 0x00d8); check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); +check_member(mtk_spm_regs, pcm_reg1_data, 0x0104); +check_member(mtk_spm_regs, pcm_reg15_data, 0x013c); +check_member(mtk_spm_regs, spm_irq_sta, 0x0158); +check_member(mtk_spm_regs, pcm_fsm_sta, 0x0178); check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); check_member(mtk_spm_regs, vde_pwr_con, 0x0300); +check_member(mtk_spm_regs, sysrom_con, 0x0354); check_member(mtk_spm_regs, ufs_sram_con, 0x036c); check_member(mtk_spm_regs, dummy_sram_con, 0x0380); check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); +check_member(mtk_spm_regs, spm_mas_pause_mask_b, 0x0408); +check_member(mtk_spm_regs, spm_mas_pause2_mask_b, 0x040c); check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); check_member(mtk_spm_regs, root_cputop_addr, 0x0570); check_member(mtk_spm_regs, cpu_spare_con, 0x0580); check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); +check_member(mtk_spm_regs, spare_ack_mask, 0x06f4); check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); +check_member(mtk_spm_regs, spare_src_req_mask, 0x06c0); check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); diff --git a/src/soc/mediatek/mt8183/include/soc/spm_init.h b/src/soc/mediatek/mt8183/include/soc/spm_init.h new file mode 100644 index 0000000..7cc4f9f --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/spm_init.h @@ -0,0 +1,2123 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SPM_INIT__ +#define __SPM_INIT__ + +#include <arch/barrier.h> +#include <arch/mmio.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <stdint.h> +#include <types.h> + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ +#define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ +#define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define WFI_OP_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define MM_MASK_B_LSB (1U << 16) /* 2b */ +#define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ +#define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ +#define MD_MASK_B_LSB (1U << 20) /* 2b */ +#define SSPM_MASK_B_LSB (1U << 22) /* 1b */ +#define SCP_MASK_B_LSB (1U << 23) /* 1b */ +#define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ +#define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ +#define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ +#define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ +#define CONN_MASK_B_LSB (1U << 28) /* 1b */ +#define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_IM_PTR (0x10006000+0x020) */ +#define PCM_IM_PTR_LSB (1U << 0) /* 32b */ +/* PCM_IM_LEN (0x10006000+0x024) */ +#define PCM_IM_LEN_LSB (1U << 0) /* 13b */ +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ +/* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ +#define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ +/* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ +#define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ +#define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ +#define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ +#define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ +#define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ +#define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ +#define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ +#define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ +#define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ +#define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ +#define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ +#define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ +#define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ +#define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ +#define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ +#define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ +#define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ +#define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ +#define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ +#define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ +/* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ +#define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ +/* SPM_SRAM_RSV_CON (0x10006000+0x088) */ +#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ +/* SCP_SPM_MAILBOX (0x10006000+0x09C) */ +#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ +#define TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ +#define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ +#define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ +#define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ +#define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ +#define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ +#define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ +#define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ +/* SPM_SCP_IRQ (0x10006000+0x0AC) */ +#define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ +#define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ +#define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ +#define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ +#define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ +#define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ +#define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ +#define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ +#define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ +#define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ +#define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ +#define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ +#define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ +#define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ +#define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ +#define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ +#define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ +#define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ +#define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ +#define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ +#define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ +#define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ +#define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ +#define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ +#define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ +#define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ +#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ +/* SCP_CLK_CON (0x10006000+0x0D0) */ +#define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ +#define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ +#define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ +/* PCM_DEBUG_CON (0x10006000+0x0D4) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ +/* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ +#define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ +#define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ +/* AHB_BUS_CON (0x10006000+0x0DC) */ +#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ +#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ +/* SPM_SRC3_MASK (0x10006000+0x0E0) */ +#define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ +#define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ +#define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ +#define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ +#define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ +#define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ +#define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ +#define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ +/* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ +#define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ +#define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ +#define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ +#define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ +/* SSPM_CLK_CON (0x10006000+0x0E8) */ +#define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG1_DATA (0x10006000+0x104) */ +#define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG2_DATA (0x10006000+0x108) */ +#define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG3_DATA (0x10006000+0x10C) */ +#define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG4_DATA (0x10006000+0x110) */ +#define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG5_DATA (0x10006000+0x114) */ +#define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG6_DATA (0x10006000+0x118) */ +#define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG7_DATA (0x10006000+0x11C) */ +#define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG8_DATA (0x10006000+0x120) */ +#define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG9_DATA (0x10006000+0x124) */ +#define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG10_DATA (0x10006000+0x128) */ +#define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG11_DATA (0x10006000+0x12C) */ +#define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_DATA (0x10006000+0x130) */ +#define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG13_DATA (0x10006000+0x134) */ +#define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG14_DATA (0x10006000+0x138) */ +#define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG15_DATA (0x10006000+0x13C) */ +#define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ +#define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_DATA (0x10006000+0x144) */ +#define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ +/* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ +#define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ +/* PCM_EVENT_REG_STA (0x10006000+0x14C) */ +#define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ +/* PCM_TIMER_OUT (0x10006000+0x150) */ +#define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* PCM_WDT_OUT (0x10006000+0x154) */ +#define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ +/* SPM_IRQ_STA (0x10006000+0x158) */ +#define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +/* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ +/* SPM_WAKEUP_STA (0x10006000+0x15C) */ +#define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ +#define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_MISC (0x10006000+0x164) */ +#define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ +#define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ +/* BUS_PROTECT_RDY (0x10006000+0x168) */ +#define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT2_RDY (0x10006000+0x16C) */ +#define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ +/* SUBSYS_IDLE_STA (0x10006000+0x170) */ +#define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ +/* CPU_IDLE_STA (0x10006000+0x174) */ +#define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ +#define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ +#define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ +#define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ +#define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ +#define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ +#define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ +#define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ +#define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ +#define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ +#define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ +#define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ +/* PCM_FSM_STA (0x10006000+0x178) */ +#define EXEC_INST_OP_LSB (1U << 0) /* 4b */ +#define PC_STATE_LSB (1U << 4) /* 3b */ +#define IM_STATE_LSB (1U << 7) /* 3b */ +#define MASTER_STATE_LSB (1U << 10) /* 5b */ +#define EVENT_FSM_LSB (1U << 15) /* 3b */ +#define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ +#define PCM_KICK_LSB (1U << 21) /* 1b */ +#define IM_KICK_LSB (1U << 22) /* 1b */ +#define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ +#define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ +/* SRC_REQ_STA (0x10006000+0x17C) */ +#define SRC_REQ_STA_LSB (1U << 0) /* 32b */ +/* PWR_STATUS (0x10006000+0x180) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_2ND (0x10006000+0x184) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS (0x10006000+0x188) */ +#define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ +#define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* MISC_STA (0x10006000+0x190) */ +#define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ +/* SPM_SRC_RDY_STA (0x10006000+0x194) */ +#define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ +/* DRAMC_DBG_LATCH (0x10006000+0x19C) */ +#define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ +#define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ +#define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ +#define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ +#define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ +#define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ +#define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ +#define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ +#define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ +#define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_STA (0x10006000+0x1C8) */ +#define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ +/* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ +#define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ +#define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ +/* SRC_DDREN_STA (0x10006000+0x1E0) */ +#define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ +/* MCU_PWR_CON (0x10006000+0x200) */ +#define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCU_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ +#define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ +#define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU1_PWR_CON (0x10006000+0x220) */ +#define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU2_PWR_CON (0x10006000+0x224) */ +#define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP1_CPU3_PWR_CON (0x10006000+0x228) */ +#define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ +#define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ +#define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ +#define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ +/* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ +#define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_L1_PDN (0x10006000+0x248) */ +#define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ +#define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU2_L1_PDN (0x10006000+0x250) */ +#define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP0_CPU3_L1_PDN (0x10006000+0x254) */ +#define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ +#define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ +#define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU0_L1_PDN (0x10006000+0x260) */ +#define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU1_L1_PDN (0x10006000+0x264) */ +#define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU2_L1_PDN (0x10006000+0x268) */ +#define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ +#define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ +/* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ +#define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +#define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ +/* DUMMY1_PWR_CON (0x10006000+0x2B0) */ +#define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ +#define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +/* BYPASS_SPMC (0x10006000+0x2B4) */ +#define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ +/* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ +#define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ +#define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ +/* ARMPLL_CLK_CON (0x10006000+0x2BC) */ +#define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ +#define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ +#define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ +#define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ +#define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ +/* SPMC_IN_RET (0x10006000+0x2C0) */ +#define SPMC_STATUS_LSB (1U << 0) /* 8b */ +/* VDE_PWR_CON (0x10006000+0x300) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VEN_PWR_CON (0x10006000+0x304) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* ISP_PWR_CON (0x10006000+0x308) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DIS_PWR_CON (0x10006000+0x30C) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE1_PWR_CON (0x10006000+0x310) */ +#define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* AUDIO_PWR_CON (0x10006000+0x314) */ +#define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUD_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* IFR_PWR_CON (0x10006000+0x318) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* DPY_PWR_CON (0x10006000+0x31C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MD1_PWR_CON (0x10006000+0x320) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ +/* VPU_TOP_PWR_CON (0x10006000+0x324) */ +#define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CONN_PWR_CON (0x10006000+0x32C) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VPU_CORE2_PWR_CON (0x10006000+0x330) */ +#define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ +#define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_PWR_CON (0x10006000+0x338) */ +#define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ +#define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* VPU_CORE1_PWR_CON (0x10006000+0x340) */ +#define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ +#define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ +#define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ +/* CAM_PWR_CON (0x10006000+0x344) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_2D_PWR_CON (0x10006000+0x348) */ +#define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ +#define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ +#define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ +/* SYSRAM_CON (0x10006000+0x350) */ +#define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* SYSROM_CON (0x10006000+0x354) */ +#define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ +/* SSPM_SRAM_CON (0x10006000+0x358) */ +#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* SCP_SRAM_CON (0x10006000+0x35C) */ +#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* UFS_SRAM_CON (0x10006000+0x36C) */ +#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ +#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ +/* DUMMY_SRAM_CON (0x10006000+0x380) */ +#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ +#define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ +#define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ +/* MD_SRAM_ISO_CON (0x10006000+0x394) */ +#define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ +/* MD_EXTRA_PWR_CON (0x10006000+0x398) */ +#define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ +#define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ +/* EXT_BUCK_CON (0x10006000+0x3A0) */ +#define RG_VA09_ON_LSB (1U << 0) /* 1b */ +/* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ +#define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON (0x10006000+0x400) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ +#define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ +/* SPM_MDBSI_CON (0x10006000+0x404) */ +#define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ +/* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ +#define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ +#define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BSI_GEN (0x10006000+0x410) */ +#define SPM_BSI_START_LSB (1U << 0) /* 1b */ +/* SPM_BSI_EN_SR (0x10006000+0x414) */ +#define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_CLK_SR (0x10006000+0x418) */ +#define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D0_SR (0x10006000+0x41C) */ +#define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D1_SR (0x10006000+0x420) */ +#define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ +/* SPM_BSI_D2_SR (0x10006000+0x424) */ +#define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ +/* SPM_AP_SEMA (0x10006000+0x428) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_SPM_SEMA (0x10006000+0x42C) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ +/* AP_MDSRC_REQ (0x10006000+0x430) */ +#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ +#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ +#define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ +#define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ +#define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ +#define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ +#define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ +#define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ +#define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ +/* DPY_LP_CON (0x10006000+0x444) */ +#define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ +/* CPU_DVFS_REQ (0x10006000+0x448) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ +/* SPM_EMI_BW_MODE (0x10006000+0x450) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ +#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ +#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ +/* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ +/* ULPOSC_CON (0x10006000+0x458) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ +#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ +/* SPM2MM_CON (0x10006000+0x45C) */ +#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ +#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ +#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ +#define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ +#define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ +#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ +/* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ +#define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ +#define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ +#define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ +#define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ +#define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ +#define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ +/* SPM_S1_MODE_CH (0x10006000+0x468) */ +#define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ +#define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ +/* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ +#define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ +#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ +#define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ +#define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ +#define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ +#define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ +#define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ +#define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ +/* DRAMC_DMYRD_CON (0x10006000+0x478) */ +#define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ +#define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ +#define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ +#define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ +/* SPM_DRS_CON (0x10006000+0x47C) */ +#define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ +#define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ +#define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ +#define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ +/* SPM_SEMA_M0 (0x10006000+0x480) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M1 (0x10006000+0x484) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M2 (0x10006000+0x488) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M3 (0x10006000+0x48C) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M4 (0x10006000+0x490) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M5 (0x10006000+0x494) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M6 (0x10006000+0x498) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M7 (0x10006000+0x49C) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ +/* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ +#define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ +#define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_ACK (0x10006000+0x4AC) */ +#define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON (0x10006000+0x4B0) */ +#define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ +#define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ +/* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ +#define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ +/* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ +#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ +/* SPM_SSPM_IRQ (0x10006000+0x4C0) */ +#define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ +#define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ +/* SPM2PMCU_INT (0x10006000+0x4C4) */ +#define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ +#define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ +#define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ +/* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ +#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ +#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ +#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ +#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_INT (0x10006000+0x4E0) */ +#define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ +#define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ +#define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ +#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ +#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ +#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ +#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_CFG (0x10006000+0x4FC) */ +#define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU0_WFI_EN (0x10006000+0x530) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU1_WFI_EN (0x10006000+0x534) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU2_WFI_EN (0x10006000+0x538) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU0_WFI_EN (0x10006000+0x540) */ +#define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU1_WFI_EN (0x10006000+0x544) */ +#define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU2_WFI_EN (0x10006000+0x548) */ +#define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ +#define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_L2CFLUSH (0x10006000+0x554) */ +#define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* MP1_L2CFLUSH (0x10006000+0x558) */ +#define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ +#define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ +/* CPU_PTPOD2_CON (0x10006000+0x560) */ +#define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ +#define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ +#define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ +#define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ +#define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ +#define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ +/* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ +/* ROOT_CORE_ADDR (0x10006000+0x574) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON (0x10006000+0x580) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_SET (0x10006000+0x584) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_CLR (0x10006000+0x588) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ +#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ +#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ +#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ +#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_INT (0x10006000+0x5E0) */ +#define SW2SPM_INT_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_SET (0x10006000+0x5E4) */ +#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_CLR (0x10006000+0x5E8) */ +#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ +#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ +#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ +#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ +#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_CFG (0x10006000+0x5FC) */ +#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +#define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ +/* SPM_SW_FLAG (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG (0x10006000+0x604) */ +#define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_0 (0x10006000+0x608) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_1 (0x10006000+0x60C) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_2 (0x10006000+0x610) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_3 (0x10006000+0x614) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_4 (0x10006000+0x618) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_5 (0x10006000+0x61C) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON (0x10006000+0x620) */ +#define SPM_RSV_CON_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA (0x10006000+0x624) */ +#define SPM_RSV_STA_LSB (1U << 0) /* 16b */ +/* SPM_RSV_CON1 (0x10006000+0x628) */ +#define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ +/* SPM_RSV_STA1 (0x10006000+0x62C) */ +#define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ +/* SPM_PASR_DPD_0 (0x10006000+0x630) */ +#define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_1 (0x10006000+0x634) */ +#define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_2 (0x10006000+0x638) */ +#define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ +/* SPM_PASR_DPD_3 (0x10006000+0x63C) */ +#define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON (0x10006000+0x640) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_SET (0x10006000+0x644) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_CLR (0x10006000+0x648) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_6 (0x10006000+0x64C) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_7 (0x10006000+0x650) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_8 (0x10006000+0x654) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_9 (0x10006000+0x658) */ +#define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_10 (0x10006000+0x65C) */ +#define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_18 (0x10006000+0x67C) */ +#define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_19 (0x10006000+0x680) */ +#define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ +/* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ +#define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ +#define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ +#define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ +/* DVFSRC_EVENT_SEL (0x10006000+0x698) */ +#define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ +/* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ +#define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ +#define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ +#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ +/* DVFS_ABORT_STA (0x10006000+0x6A8) */ +#define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ +#define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ +/* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ +#define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ +/* SPM_DFS_LEVEL (0x10006000+0x6B0) */ +#define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ +/* SPM_DVS_LEVEL (0x10006000+0x6B4) */ +#define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +#define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ +#define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ +/* SPM_DVFS_MISC (0x10006000+0x6B8) */ +#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ +#define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ +#define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ +#define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ +#define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ +#define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ +#define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ +#define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ +#define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ +#define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ +#define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ +#define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ +/* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ +#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ +/* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ +#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ +#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ +/* SPARE_ACK_STA (0x10006000+0x6F0) */ +#define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1 (0x10006000+0x700) */ +#define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON1_STA (0x10006000+0x704) */ +#define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD0 (0x10006000+0x710) */ +#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD1 (0x10006000+0x714) */ +#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD2 (0x10006000+0x718) */ +#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD3 (0x10006000+0x71C) */ +#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD4 (0x10006000+0x720) */ +#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD5 (0x10006000+0x724) */ +#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD6 (0x10006000+0x728) */ +#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD7 (0x10006000+0x72C) */ +#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD8 (0x10006000+0x730) */ +#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD9 (0x10006000+0x734) */ +#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD10 (0x10006000+0x738) */ +#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD11 (0x10006000+0x73C) */ +#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD12 (0x10006000+0x740) */ +#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD13 (0x10006000+0x744) */ +#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD14 (0x10006000+0x748) */ +#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD15 (0x10006000+0x74C) */ +#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ +#define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ +#define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ +#define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ +#define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ +/* SPARE_ACK_IN_FIX (0x10006000+0x790) */ +#define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ +#define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ +#define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_0 (0x10006000+0x800) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_1 (0x10006000+0x804) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_2 (0x10006000+0x808) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_4 (0x10006000+0x810) */ +#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_5 (0x10006000+0x814) */ +#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_6 (0x10006000+0x818) */ +#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ +#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_8 (0x10006000+0x820) */ +#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_9 (0x10006000+0x824) */ +#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE0 (0x10006000+0x828) */ +#define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ +#define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE2 (0x10006000+0x830) */ +#define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ +/* WDT_LATCH_SPARE3 (0x10006000+0x834) */ +#define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_10 (0x10006000+0x838) */ +#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ +#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ +#define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ +#define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ +#define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ +#define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ +#define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ +#define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ +#define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ +#define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ +#define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ +#define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ +#define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ +#define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ +#define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ +#define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ +#define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ +/* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ +#define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ +/* DCHA_LATCH_RSV0 (0x10006000+0x880) */ +#define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* DCHB_LATCH_RSV0 (0x10006000+0x884) */ +#define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_12 (0x10006000+0x888) */ +#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ +#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ +#define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ +/* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ +#define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ +#define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ +#define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ +#define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ +#define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ +#define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ +#define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ +/* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ +#define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ +/* SPM_ACK_CHK_CON (0x10006000+0x900) */ +#define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC (0x10006000+0x904) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL (0x10006000+0x908) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ +#define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA (0x10006000+0x910) */ +#define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ +#define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ +#define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ +#define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ +#define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ +#define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ +#define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ +#define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ +#define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ +#define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ +#define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ +#define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ +#define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ +#define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ +#define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DIS_CPU_PDN (1U << 0) +#define SPM_FLAG_DIS_INFRA_PDN (1U << 1) +#define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) +#define SPM_FLAG_DIS_VCORE_DVS (1U << 3) +#define SPM_FLAG_DIS_VCORE_DFS (1U << 4) +#define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) +#define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) +#define SPM_FLAG_DIS_ATF_ABORT (1U << 7) +#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) +#define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) +#define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) +#define SPM_FLAG_SODI_CG_MODE (1U << 12) +#define SPM_FLAG_SODI_NO_EVENT (1U << 13) +#define SPM_FLAG_ENABLE_SODI3 (1U << 14) +#define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) +#define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) +#define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) +#define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) +#define SPM_FLAG_SUSPEND_OPTION (1U << 19) +#define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) +#define SPM_FLAG_SODI_OPTION (1U << 21) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) +#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) + +/* --- SPM Flag1 Define --- */ +#define SPM_FLAG1_RESERVED_BIT0 (1U << 0) +#define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) +#define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) +#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) +#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) +#define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) +#define SPM_FLAG1_DISABLE_MCDSR (1U << 6) +#define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) +#define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) +#define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) +#define SPM_FLAG1_RESERVED_BIT10 (1U << 10) +#define SPM_FLAG1_RESERVED_BIT11 (1U << 11) +#define SPM_FLAG1_RESERVED_BIT12 (1U << 12) +#define SPM_FLAG1_RESERVED_BIT13 (1U << 13) +#define SPM_FLAG1_RESERVED_BIT14 (1U << 14) +#define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) +#define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) +#define SPM_FLAG1_DIS_IMP_DIS (1U << 17) +#define SPM_FLAG1_DIS_IMP_COPY (1U << 18) +#define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) +#define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) +#define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) +#define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) +#define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) +#define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) +#define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) +#define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) +#define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) +#define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) +#define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) +#define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) +#define SPM_FLAG1_DIS_SW_MR4 (1U << 31) + +/* --- SPM DEBUG Define --- */ +#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) +#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) +#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) +#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) +#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) +#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) +#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) +#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) +#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) +#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) +#define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) +#define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) +#define SPM_DBG_DEBUG_IDX_DPD (1U << 13) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) +#define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) +#define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) +#define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) +#define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) +#define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) +#define SPM_DBG_RESERVED_BIT21 (1U << 21) +#define SPM_DBG_RESERVED_BIT22 (1U << 22) +#define SPM_DBG_RESERVED_BIT23 (1U << 23) +#define SPM_DBG_RESERVED_BIT24 (1U << 24) +#define SPM_DBG_RESERVED_BIT25 (1U << 25) +#define SPM_DBG_RESERVED_BIT26 (1U << 26) +#define SPM_DBG_SODI1_FLAG (1U << 27) +#define SPM_DBG_SODI3_FLAG (1U << 28) +#define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) +#define SPM_DBG_DEEPIDLE_FLAG (1U << 30) +#define SPM_DBG_SUSPEND_FLAG (1U << 31) + +/* --- SPM DEBUG1 Define --- */ +#define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) +#define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) +#define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) +#define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) +#define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) +#define SPM_DBG1_RESERVED_BIT5 (1U << 5) +#define SPM_DBG1_RESERVED_BIT6 (1U << 6) +#define SPM_DBG1_RESERVED_BIT7 (1U << 7) +#define SPM_DBG1_RESERVED_BIT8 (1U << 8) +#define SPM_DBG1_RESERVED_BIT9 (1U << 9) +#define SPM_DBG1_RESERVED_BIT10 (1U << 10) +#define SPM_DBG1_RESERVED_BIT11 (1U << 11) +#define SPM_DBG1_RESERVED_BIT12 (1U << 12) +#define SPM_DBG1_RESERVED_BIT13 (1U << 13) +#define SPM_DBG1_RESERVED_BIT14 (1U << 14) +#define SPM_DBG1_RESERVED_BIT15 (1U << 15) +#define SPM_DBG1_RESERVED_BIT16 (1U << 16) +#define SPM_DBG1_RESERVED_BIT17 (1U << 17) +#define SPM_DBG1_RESERVED_BIT18 (1U << 18) +#define SPM_DBG1_RESERVED_BIT19 (1U << 19) +#define SPM_DBG1_RESERVED_BIT20 (1U << 20) +#define SPM_DBG1_RESERVED_BIT21 (1U << 21) +#define SPM_DBG1_RESERVED_BIT22 (1U << 22) +#define SPM_DBG1_RESERVED_BIT23 (1U << 23) +#define SPM_DBG1_RESERVED_BIT24 (1U << 24) +#define SPM_DBG1_RESERVED_BIT25 (1U << 25) +#define SPM_DBG1_RESERVED_BIT26 (1U << 26) +#define SPM_DBG1_RESERVED_BIT27 (1U << 27) +#define SPM_DBG1_RESERVED_BIT28 (1U << 28) +#define SPM_DBG1_RESERVED_BIT29 (1U << 29) +#define SPM_DBG1_RESERVED_BIT30 (1U << 30) +#define SPM_DBG1_RESERVED_BIT31 (1U << 31) + +/* --- R0 Define --- */ +#define R0_SC_26M_CK_OFF (1U << 0) +#define R0_BIT1 (1U << 1) +#define R0_SC_MEM_CK_OFF (1U << 2) +#define R0_SC_AXI_CK_OFF (1U << 3) +#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) +#define R0_SC_MD26M_CK_OFF (1U << 5) +#define R0_SC_DPY_MODE_SW_PCM (1U << 6) +#define R0_SC_DMSUS_OFF_PCM (1U << 7) +#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) +#define R0_BIT9 (1U << 9) +#define R0_SC_MPLLOUT_OFF (1U << 10) +#define R0_SC_TX_TRACKING_DIS (1U << 11) +#define R0_SC_DPY_DLL_EN_PCM (1U << 12) +#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) +#define R0_SC_DPY_VREF_EN_PCM (1U << 14) +#define R0_SC_PHYPLL_EN_PCM (1U << 15) +#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) +#define R0_SC_DPY_BCLK_ENABLE (1U << 17) +#define R0_SC_MPLL_OFF (1U << 18) +#define R0_SC_SHU_RESTORE (1U << 19) +#define R0_SC_CKSQ0_OFF (1U << 20) +#define R0_SC_CKSQ1_OFF (1U << 21) +#define R0_SC_DR_SHU_EN_PCM (1U << 22) +#define R0_SC_DPHY_PRECAL_UP (1U << 23) +#define R0_SC_MPLL_S_OFF (1U << 24) +#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) +#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) +#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) +#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) +#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) +#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) +#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) + +/* --- R7 Define --- */ +#define R7_PWRAP_SLEEP_REQ (1U << 0) +#define R7_EMI_CLK_OFF_REQ (1U << 1) +#define R7_TOP_MAS_PAU_REQ (1U << 2) +#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) +#define R7_PCM_CK_SEL0 (1U << 4) +#define R7_PCM_CK_SEL1 (1U << 5) +#define R7_SPM2RC_DVS_DONE (1U << 6) +#define R7_FREQH_PAUSE_MPLL (1U << 7) +#define R7_SC_26M_CK_SEL (1U << 8) +#define R7_PCM_TIMER_SET (1U << 9) +#define R7_PCM_TIMER_CLR (1U << 10) +#define R7_SRCVOLTEN (1U << 11) +#define R7_CSYSPWRUPACK (1U << 12) +#define R7_IM_SLEEP_ENABLE (1U << 13) +#define R7_SRCCLKENO_0 (1U << 14) +#define R7_SYSRST (1U << 15) +#define R7_MD_APSRC_ACK (1U << 16) +#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) +#define R7_SC_AXI_DCM_DIS (1U << 18) +#define R7_FREQH_PAUSE_MAIN (1U << 19) +#define R7_FREQH_PAUSE_MEM (1U << 20) +#define R7_SRCCLKENO_1 (1U << 21) +#define R7_WDT_KICK_P (1U << 22) +#define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) +#define R7_WAKEUP_EXT_W_SEL (1U << 24) +#define R7_WAKEUP_EXT_R_SEL (1U << 25) +#define R7_PMIC_IRQ_REQ_EN (1U << 26) +#define R7_FORCE_26M_WAKE (1U << 27) +#define R7_FORCE_APSRC_WAKE (1U << 28) +#define R7_FORCE_INFRA_WAKE (1U << 29) +#define R7_FORCE_VRF18_WAKE (1U << 30) +#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) + +/* --- R12 Define --- */ +#define R12_PCM_TIMER (1U << 0) +#define R12_SSPM_WDT_EVENT_B (1U << 1) +#define R12_KP_IRQ_B (1U << 2) +#define R12_APWDT_EVENT_B (1U << 3) +#define R12_APXGPT1_EVENT_B (1U << 4) +#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) +#define R12_EINT_EVENT_B (1U << 6) +#define R12_CONN_WDT_IRQ_B (1U << 7) +#define R12_CCIF0_EVENT_B (1U << 8) +#define R12_LOWBATTERY_IRQ_B (1U << 9) +#define R12_SSPM_SPM_IRQ_B (1U << 10) +#define R12_SCP_SPM_IRQ_B (1U << 11) +#define R12_SCP_WDT_EVENT_B (1U << 12) +#define R12_PCM_WDT_WAKEUP_B (1U << 13) +#define R12_USB_CDSC_B (1U << 14) +#define R12_USB_POWERDWN_B (1U << 15) +#define R12_SYS_TIMER_EVENT_B (1U << 16) +#define R12_EINT_EVENT_SECURE_B (1U << 17) +#define R12_CCIF1_EVENT_B (1U << 18) +#define R12_UART0_IRQ_B (1U << 19) +#define R12_AFE_IRQ_MCU_B (1U << 20) +#define R12_THERM_CTRL_EVENT_B (1U << 21) +#define R12_SYS_CIRQ_IRQ_B (1U << 22) +#define R12_MD2AP_PEER_EVENT_B (1U << 23) +#define R12_CSYSPWREQ_B (1U << 24) +#define R12_MD1_WDT_B (1U << 25) +#define R12_CLDMA_EVENT_B (1U << 26) +#define R12_SEJ_WDT_GPT_B (1U << 27) +#define R12_ALL_SSPM_WAKEUP_B (1U << 28) +#define R12_CPU_IRQ_B (1U << 29) +#define R12_CPU_WFI_AND_B (1U << 30) +#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) + +/* --- R12ext Define --- */ +#define R12EXT_26M_WAKE (1U << 0) +#define R12EXT_26M_SLEEP (1U << 1) +#define R12EXT_INFRA_WAKE (1U << 2) +#define R12EXT_INFRA_SLEEP (1U << 3) +#define R12EXT_APSRC_WAKE (1U << 4) +#define R12EXT_APSRC_SLEEP (1U << 5) +#define R12EXT_VRF18_WAKE (1U << 6) +#define R12EXT_VRF18_SLEEP (1U << 7) +#define R12EXT_DVFS_ALL_STATE (1U << 8) +#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) +#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) +#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) +#define R12EXT_DDREN_WAKE (1U << 12) +#define R12EXT_DDREN_SLEEP (1U << 13) +#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) +#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) +#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) +#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) +#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) +#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) +#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) +#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) +#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) +#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) +#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) +#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) +#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) +#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) +#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) +#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) +#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) +#define R12EXT_HYBRID_DDREN_WAKE (1U << 31) + +/* --- R13 Define --- */ +#define R13_EXT_SRCCLKENI_0 (1U << 0) +#define R13_EXT_SRCCLKENI_1 (1U << 1) +#define R13_MD1_SRCCLKENA (1U << 2) +#define R13_MD1_APSRC_REQ (1U << 3) +#define R13_CONN_DDR_EN (1U << 4) +#define R13_MD2_SRCCLKENA (1U << 5) +#define R13_SSPM_SRCCLKENA (1U << 6) +#define R13_SSPM_APSRC_REQ (1U << 7) +#define R13_MD_STATE (1U << 8) +#define R13_EMI_CLK_OFF_2_ACK (1U << 9) +#define R13_MM_STATE (1U << 10) +#define R13_SSPM_STATE (1U << 11) +#define R13_MD_DDR_EN (1U << 12) +#define R13_CONN_STATE (1U << 13) +#define R13_CONN_SRCCLKENA (1U << 14) +#define R13_CONN_APSRC_REQ (1U << 15) +#define R13_SLEEP_EVENT_STA (1U << 16) +#define R13_WAKE_EVENT_STA (1U << 17) +#define R13_EMI_IDLE (1U << 18) +#define R13_CSYSPWRUPREQ (1U << 19) +#define R13_PWRAP_SLEEP_ACK (1U << 20) +#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) +#define R13_TOP_MAS_PAU_ACK (1U << 22) +#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) +#define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) +#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) +#define R13_INFRA_AUX_IDLE (1U << 26) +#define R13_DVFS_ALL_STATE (1U << 27) +#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) +#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) +#define R13_MD1_VRF18_REQ (1U << 30) +#define R13_C2K_VRF18_REQ (1U << 31) + +#define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) +#define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) + +#define MP0_SPMC_SRAM_DORMANT_EN (1<<0) +#define MP1_SPMC_SRAM_DORMANT_EN (1<<1) +#define MP2_SPMC_SRAM_DORMANT_EN (1<<2) + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 7) | \ + (!!(resume) << 6) | \ + ((event) & 0x3f)) + +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF 0x00015800 +#define PCM_FSM_STA_DEF 0x00108490 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 (1U << 0) +#define PCM_SW_INT1 (1U << 1) +#define PCM_SW_INT2 (1U << 2) +#define PCM_SW_INT3 (1U << 3) +#define PCM_SW_INT4 (1U << 4) +#define PCM_SW_INT5 (1U << 5) +#define PCM_SW_INT6 (1U << 6) +#define PCM_SW_INT7 (1U << 7) +#define PCM_SW_INT8 (1U << 8) +#define PCM_SW_INT9 (1U << 9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ0 (1U << 8) +#define ISRM_RET_IRQ1 (1U << 9) +#define ISRM_RET_IRQ2 (1U << 10) +#define ISRM_RET_IRQ3 (1U << 11) +#define ISRM_RET_IRQ4 (1U << 12) +#define ISRM_RET_IRQ5 (1U << 13) +#define ISRM_RET_IRQ6 (1U << 14) +#define ISRM_RET_IRQ7 (1U << 15) +#define ISRM_RET_IRQ8 (1U << 16) +#define ISRM_RET_IRQ9 (1U << 17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ + ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ + ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ + ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_WAKEUP_MISC */ +#define WAKE_MISC_TWAM (1U << 18) +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +enum SPM_WAKE_SRC_LIST { + WAKE_SRC_R12_PCM_TIMER = (1U << 0), + WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), + WAKE_SRC_R12_KP_IRQ_B = (1U << 2), + WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), + WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), + WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), + WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), + WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), + WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), + WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), + WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), + WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), + WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), + WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), + WAKE_SRC_R12_USB_CDSC_B = (1U << 14), + WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), + WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), + WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), + WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), + WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), + WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), + WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), + WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), + WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), + WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), + WAKE_SRC_R12_MD1_WDT_B = (1U << 25), + WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), + WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), + WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), + WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), + WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), +}; + +struct pcm_desc { + const char *version; /* PCM code version */ + u32 *base; /* binary array base */ + const u16 size; /* binary array size */ + const u8 sess; /* session number */ + const u8 replace; /* replace mode */ + const u16 addr_2nd; /* 2nd binary array size */ + const u16 reserved; /* for 32bit alignment */ + u32 vec0; /* event vector 0 config */ + u32 vec1; /* event vector 1 config */ + u32 vec2; /* event vector 2 config */ + u32 vec3; /* event vector 3 config */ + u32 vec4; /* event vector 4 config */ + u32 vec5; /* event vector 5 config */ + u32 vec6; /* event vector 6 config */ + u32 vec7; /* event vector 7 config */ + u32 vec8; /* event vector 8 config */ + u32 vec9; /* event vector 9 config */ + u32 vec10; /* event vector 10 config */ + u32 vec11; /* event vector 11 config */ + u32 vec12; /* event vector 12 config */ + u32 vec13; /* event vector 13 config */ + u32 vec14; /* event vector 14 config */ + u32 vec15; /* event vector 15 config */ +}; + +struct pwr_ctrl { + unsigned int pcm_flags; + unsigned int pcm_flags1; + unsigned int timer_val; + unsigned int wake_src; + + /* SPM_AP_STANDBY_CON */ + unsigned int wfi_op; + unsigned int mp0_cputop_idle_mask; + unsigned int mp1_cputop_idle_mask; + unsigned int mcusys_idle_mask; + unsigned int mm_mask_b; + unsigned int md_ddr_en_0_dbc_en; + unsigned int md_ddr_en_1_dbc_en; + unsigned int md_mask_b; + unsigned int sspm_mask_b; + unsigned int scp_mask_b; + unsigned int srcclkeni_mask_b; + unsigned int md_apsrc_1_sel; + unsigned int md_apsrc_0_sel; + unsigned int conn_ddr_en_dbc_en; + unsigned int conn_mask_b; + unsigned int conn_apsrc_sel; + + /* SPM_SRC_REQ */ + unsigned int spm_apsrc_req; + unsigned int spm_f26m_req; + unsigned int spm_infra_req; + unsigned int spm_vrf18_req; + unsigned int spm_ddren_req; + unsigned int spm_rsv_src_req; + unsigned int spm_ddren_2_req; + unsigned int cpu_md_dvfs_sop_force_on; + + /* SPM_SRC_MASK */ + unsigned int csyspwreq_mask; + unsigned int ccif0_md_event_mask_b; + unsigned int ccif0_ap_event_mask_b; + unsigned int ccif1_md_event_mask_b; + unsigned int ccif1_ap_event_mask_b; + unsigned int ccif2_md_event_mask_b; + unsigned int ccif2_ap_event_mask_b; + unsigned int ccif3_md_event_mask_b; + unsigned int ccif3_ap_event_mask_b; + unsigned int md_srcclkena_0_infra_mask_b; + unsigned int md_srcclkena_1_infra_mask_b; + unsigned int conn_srcclkena_infra_mask_b; + unsigned int ufs_infra_req_mask_b; + unsigned int srcclkeni_infra_mask_b; + unsigned int md_apsrc_req_0_infra_mask_b; + unsigned int md_apsrc_req_1_infra_mask_b; + unsigned int conn_apsrcreq_infra_mask_b; + unsigned int ufs_srcclkena_mask_b; + unsigned int md_vrf18_req_0_mask_b; + unsigned int md_vrf18_req_1_mask_b; + unsigned int ufs_vrf18_req_mask_b; + unsigned int gce_vrf18_req_mask_b; + unsigned int conn_infra_req_mask_b; + unsigned int gce_apsrc_req_mask_b; + unsigned int disp0_apsrc_req_mask_b; + unsigned int disp1_apsrc_req_mask_b; + unsigned int mfg_req_mask_b; + unsigned int vdec_req_mask_b; + + /* SPM_SRC2_MASK */ + unsigned int md_ddr_en_0_mask_b; + unsigned int md_ddr_en_1_mask_b; + unsigned int conn_ddr_en_mask_b; + unsigned int ddren_sspm_apsrc_req_mask_b; + unsigned int ddren_scp_apsrc_req_mask_b; + unsigned int disp0_ddren_mask_b; + unsigned int disp1_ddren_mask_b; + unsigned int gce_ddren_mask_b; + unsigned int ddren_emi_self_refresh_ch0_mask_b; + unsigned int ddren_emi_self_refresh_ch1_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + unsigned int spm_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + unsigned int spm_wakeup_event_ext_mask; + + /* SPM_SRC3_MASK */ + unsigned int md_ddr_en_2_0_mask_b; + unsigned int md_ddr_en_2_1_mask_b; + unsigned int conn_ddr_en_2_mask_b; + unsigned int ddren2_sspm_apsrc_req_mask_b; + unsigned int ddren2_scp_apsrc_req_mask_b; + unsigned int disp0_ddren2_mask_b; + unsigned int disp1_ddren2_mask_b; + unsigned int gce_ddren2_mask_b; + unsigned int ddren2_emi_self_refresh_ch0_mask_b; + unsigned int ddren2_emi_self_refresh_ch1_mask_b; + + unsigned int mp0_cpu0_wfi_en; + unsigned int mp0_cpu1_wfi_en; + unsigned int mp0_cpu2_wfi_en; + unsigned int mp0_cpu3_wfi_en; + + unsigned int mp1_cpu0_wfi_en; + unsigned int mp1_cpu1_wfi_en; + unsigned int mp1_cpu2_wfi_en; + unsigned int mp1_cpu3_wfi_en; +}; + +struct wake_status { + unsigned int assert_pc; + unsigned int r12; + unsigned int r12_ext; + unsigned int raw_sta; + unsigned int raw_ext_sta; + unsigned int wake_misc; + unsigned int timer_out; + unsigned int r13; + unsigned int r15; + unsigned int idle_sta; + unsigned int req_sta; + unsigned int debug_flag; + unsigned int debug_flag1; + unsigned int event_reg; + unsigned int isr; + unsigned int sw_flag; + unsigned int sw_flag1; + unsigned int log_index; +}; + +enum dyna_load_pcm_index { + DYNA_LOAD_PCM_SUSPEND_LP4_3733 = 0, + DYNA_LOAD_PCM_SUSPEND_LP4_3200, + DYNA_LOAD_PCM_MAX, +}; + +struct dyna_load_pcm_t { + char path[128]; + char version[128]; + u8 *buf; + struct pcm_desc desc; + int ready; +}; + +void spm_init(void); + +#endif /* __SPM_INIT__ */ diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4..5e8c2e4 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/spm_init.h> #include <symbols.h> @@ -27,6 +28,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + spm_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c new file mode 100644 index 0000000..dcac95f --- /dev/null +++ b/src/soc/mediatek/mt8183/spm.c @@ -0,0 +1,321 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <soc/emi.h> +#include <soc/spm.h> +#include <soc/spm_init.h> + +#define BUF_SIZE (16 * KiB) +static uint8_t spm_bin[BUF_SIZE] __aligned(8); + +struct dyna_load_pcm_t dyna_load_pcm[DYNA_LOAD_PCM_MAX]; + +static void spm_register_init(void) +{ + write32(&mtk_spm->poweron_config_set, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB | + MD_BCLK_CG_EN_LSB); + + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + if ((read32(&mtk_spm->pcm_fsm_sta) & 0x7fffff) != PCM_FSM_STA_DEF) + printk(BIOS_ERR, "PCM reset failed\n"); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | EVENT_LOCK_EN_LSB | + SPM_SRAM_ISOINT_B_LSB | MIF_APBEN_LSB | + SCP_APB_INTERNAL_EN_LSB); + write32(&mtk_spm->pcm_im_ptr, 0); + write32(&mtk_spm->pcm_im_len, 0); + + write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) | (0x3 << 2) | + SPM_LOCK_INFRA_DCM_LSB | (1 << 6) | + CXO32K_REMOVE_EN_MD1_LSB | + CLKSQ1_SEL_CTRL_LSB | SRCLKEN0_EN_LSB | + (0x10 << 23)); + + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->ddr_en_dbc_len, 0x154 | (0x154 << 10) | (0x154 << 20)); + write32(&mtk_spm->spare_ack_mask, + (read32(&mtk_spm->spare_ack_mask) & ~(0x1 << 1)) | 0x1); + write32(&mtk_spm->sysrom_con, 0x3f); + write32(&mtk_spm->spm_pc_trace_con, 0x8 | SPM_PC_TRACE_HW_EN_LSB); + + write32(&mtk_spm->spare_src_req_mask, read32(&mtk_spm->spare_src_req_mask) | + SPARE1_DDREN_MASK_B_LSB); +} + +static void spm_code_swapping(void) +{ + unsigned int con1, retry = 0, timeout = 5000; + + con1 = read32(&mtk_spm->spm_wakeup_event_mask); + + write32(&mtk_spm->spm_wakeup_event_mask, (con1 & ~(0x1))); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + + while ((read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB) == 0) { + if (retry > timeout) { + printk(BIOS_ERR, "r15: 0x%x, pcmsta: 0x%x, irqsta: 0x%x [%d]\n", + read32(&mtk_spm->pcm_reg15_data), + read32(&mtk_spm->pcm_fsm_sta), + read32(&mtk_spm->spm_irq_sta), timeout); + } + retry++; + } + + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, con1); +} + +static void spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) +{ + unsigned int con1; + + if ((read32(&mtk_spm->pcm_reg1_data) == 0x1) && + !(read32(&mtk_spm->pcm_reg15_data) == 0x0)) { + spm_code_swapping(); + write32(&mtk_spm->spm_power_on_val0, read32(&mtk_spm->pcm_reg0_data)); + } + + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~PCM_TIMER_EN_LSB)); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + if ((read32(&mtk_spm->pcm_fsm_sta) & 0x7fffff) != PCM_FSM_STA_DEF) + printk(BIOS_ERR, "reset pcm(PCM_FSM_STA=0x%x)\n", + read32(&mtk_spm->pcm_fsm_sta)); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + + con1 = read32(&mtk_spm->pcm_con1) & (PCM_WDT_WAKE_MODE_LSB); + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + EVENT_LOCK_EN_LSB | SPM_SRAM_ISOINT_B_LSB | + (pcmdesc->replace ? 0 : IM_NONRP_EN_LSB) | + MIF_APBEN_LSB | SCP_APB_INTERNAL_EN_LSB); +} + +static void spm_load_pcm_code(const struct pcm_desc *pcmdesc) +{ + int i; + + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | IM_SLAVE_LSB); + + for (i = 0; i < pcmdesc->size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, BIT(31) | BIT(30) | i); + write32(&mtk_spm->pcm_im_host_rw_dat, + (unsigned int) *(pcmdesc->base + i)); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_check_pcm_code(const struct pcm_desc *pcmdesc) +{ + int i; + + for (i = 0; i < pcmdesc->size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, BIT(31) | i); + if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != + (unsigned int) *(pcmdesc->base + i)) + spm_load_pcm_code(pcmdesc); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) +{ + unsigned int ptr, len, con0; + + ptr = (unsigned int)(unsigned long)(pcmdesc->base); + len = pcmdesc->size - 1; + + spm_load_pcm_code(pcmdesc); + spm_check_pcm_code(pcmdesc); + + printk(BIOS_INFO, "spm_kick_im_to_fetch: ptr = 0x%x\n", ptr); + printk(BIOS_INFO, "spm_kick_im_to_fetch: len = %d\n", len); + + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | + PCM_CK_EN_LSB | IM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + write32(&mtk_spm->pcm_event_vector0, pcmdesc->vec0); + write32(&mtk_spm->pcm_event_vector1, pcmdesc->vec1); + write32(&mtk_spm->pcm_event_vector2, pcmdesc->vec2); + write32(&mtk_spm->pcm_event_vector3, pcmdesc->vec3); + write32(&mtk_spm->pcm_event_vector4, pcmdesc->vec4); + write32(&mtk_spm->pcm_event_vector5, pcmdesc->vec5); + write32(&mtk_spm->pcm_event_vector6, pcmdesc->vec6); + write32(&mtk_spm->pcm_event_vector7, pcmdesc->vec7); + write32(&mtk_spm->pcm_event_vector8, pcmdesc->vec8); + write32(&mtk_spm->pcm_event_vector9, pcmdesc->vec9); + write32(&mtk_spm->pcm_event_vector10, pcmdesc->vec10); + write32(&mtk_spm->pcm_event_vector11, pcmdesc->vec11); + write32(&mtk_spm->pcm_event_vector12, pcmdesc->vec12); + write32(&mtk_spm->pcm_event_vector13, pcmdesc->vec13); + write32(&mtk_spm->pcm_event_vector14, pcmdesc->vec14); + write32(&mtk_spm->pcm_event_vector15, pcmdesc->vec15); +} + +static const char *dyna_load_pcm_path[] = { + [DYNA_LOAD_PCM_SUSPEND_LP4_3733] = "pcm_allinone_lp4_3733.bin", + [DYNA_LOAD_PCM_SUSPEND_LP4_3200] = "pcm_allinone_lp4_3200.bin", + [DYNA_LOAD_PCM_MAX] = "pcm_path_max", +}; + +static void spm_load_firmware(enum dyna_load_pcm_index index) +{ + int offset = 0; + u16 firmware_size = 0; + int copy_size = 0; + const char *file_name = dyna_load_pcm_path[index]; + struct pcm_desc *pdesc = &(dyna_load_pcm[index].desc); + + size_t fw_size = cbfs_boot_load_file(file_name, + spm_bin, + sizeof(spm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) + printk(BIOS_ERR, "SPM file: %s not found!!!\n", + dyna_load_pcm_path[index]); + + /* start of binary size */ + offset = 0; + copy_size = 2; + memcpy(&firmware_size, spm_bin + offset, copy_size); + + printk(BIOS_INFO, "spm: firmware_size = %d\n", firmware_size); + + /* start of binary */ + offset += copy_size; + copy_size = firmware_size * 4; + dyna_load_pcm[index].buf = spm_bin + offset; + + printk(BIOS_INFO, "start of binary: (spm_bin + offset) = 0x%x\n", + (unsigned int)(unsigned long) dyna_load_pcm[index].buf); + + /* start of pcm_desc */ + offset += copy_size; + copy_size = sizeof(struct pcm_desc) - offsetof(struct pcm_desc, size); + memcpy((void *)&(dyna_load_pcm[index].desc.size), + spm_bin + offset, copy_size); + + offset += copy_size; + snprintf(dyna_load_pcm[index].version, 128 - 1, "%s", spm_bin + offset); + pdesc->version = dyna_load_pcm[index].version; + pdesc->base = (u32 *) dyna_load_pcm[index].buf; + + printk(BIOS_INFO, "start of pcm_desc: pdesc->version %s\n", + pdesc->version); + + printk(BIOS_INFO, "#@# %s(%d) use spmfw partition for %s\n", __func__, + __LINE__, dyna_load_pcm_path[index]); + + dyna_load_pcm[index].ready = 1; +} + +static void spm_kick_pcm_to_run(void) +{ + uint32_t con0; + + write32(&mtk_spm->spm_mas_pause_mask_b, 0xffffffff); + write32(&mtk_spm->spm_mas_pause2_mask_b, 0xffffffff); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + write32(&mtk_spm->pcm_pwr_io_en, PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7); + + printk(BIOS_INFO, "SPM spm_kick_pcm_to_run\n"); + + /* check IM ready */ + while ((read32(&mtk_spm->pcm_fsm_sta) & (0x7 << 7)) != (0x4 << 7)) + ; + + /* kick PCM to run, and toggle PCM_KICK */ + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + printk(BIOS_INFO, "SPM spm_kick_pcm_to_run done\n"); +} + +void spm_init(void) +{ + struct pcm_desc *pcmdesc = NULL; + unsigned int dram_type = get_dram_type(); + enum dyna_load_pcm_index index; + + if (dram_type == DRAM_TYPE_EMCP) + index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; + else + index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; + + printk(BIOS_INFO, "SPM: dram type = %d, pcm index = %d\n", + dram_type, index); + + if (dyna_load_pcm[index].ready) + pcmdesc = &(dyna_load_pcm[index].desc); + else { + printk(BIOS_ERR, "SPM: firmware is not ready!!!\n"); + return; + } + + spm_load_firmware(index); + spm_register_init(); + spm_reset_and_init_pcm(pcmdesc); + spm_kick_im_to_fetch(pcmdesc); + spm_init_pcm_register(); + spm_init_event_vector(pcmdesc); + spm_kick_pcm_to_run(); + + printk(BIOS_INFO, "SPM spm_init done\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Gerrit-Change-Number: 34545 Gerrit-PatchSet: 1 Gerrit-Owner: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-MessageType: newchange

7 91

Change in ...coreboot[master]: mb/asrock/h110m: rewrite gpio config using macros
by Maxim Polyakov (Code Review) 28 Sep '19

28 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33565 Change subject: mb/asrock/h110m: rewrite gpio config using macros ...................................................................... mb/asrock/h110m: rewrite gpio config using macros Use macros from the intel/common/block/include/intelblocks/gpio_defs.h instead of the raw values of the DW0/1 registers to determine the GPIO ports configuration for this board. The pch-pads-parser(1) utility was used to create this configuration from inteltool logs. [1] https://github.com/maxpoliak/pch-pads-parser Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/include/gpio.h 1 file changed, 228 insertions(+), 240 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33565/1 diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae9911..4063087 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -19,254 +19,242 @@ #include <soc/gpe.h> #include <soc/gpio.h> -#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ - _PAD_CFG_STRUCT(val, config0, config1) - /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC1 */ + PAD_CFG_GPI(GPP_A11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A12, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */ + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* SUS_ACK# */ + PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_A23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPI(GPP_B0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B1, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), /* CPU_GP3 */ + PAD_CFG_GPI(GPP_B5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B6, NONE, PLTRST), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_B8, 5K_PU, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B10, NONE, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, 0x04000000, 0x00000000), /* GPIO */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), /* SPKR */ + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO */ + PAD_CFG_GPI(GPP_B18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_B22, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), /* PCHHOT# */ + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPI(GPP_C5, NONE, PLTRST), /* GPIO */ /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), /* UART0_TXD */ + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), /* UART0_RTS# */ + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), /* UART0_CTS# */ + PAD_CFG_GPI(GPP_C12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_C19, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), /* UART2_TXD */ + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* UART2_RTS# */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), /* GPIO */ + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI(GPP_D0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D1, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D4, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), /* I2S_SFRM */ + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), /* I2S_TXD */ + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* I2S_RXD */ + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* I2S_SCLK */ + PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D18, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), /* DMIC_DATA0 */ + PAD_CFG_GPI(GPP_D21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_D23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), /* SATAXPCIE0 */ + PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), /* SATAXPCIE1 */ + PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), /* SATAXPCIE2 */ + PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* CPU_GP0 */ + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* SATA_DEVSLP2 */ + PAD_CFG_GPI(GPP_E7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* SATA_LED# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_OC3# */ + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI(GPP_F0, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */ + PAD_NC(GPP_F2, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F4, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F7, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC4# */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* USB_OC5# */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* USB_OC6# */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_F23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI(GPP_G0, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G1, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G2, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G3, NONE, PWROK), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* GPIO */ + PAD_CFG_GPI(GPP_G5, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G6, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G7, NONE, PWROK), /* GPIO */ + PAD_CFG_GPI(GPP_G8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G13, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G15, 0, PLTRST), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G17, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* SMI# */ + PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_G23, NONE, PLTRST), /* GPIO */ + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, PLTRST), /* GPIO */ + PAD_NC(GPP_H1, NONE), /* GPIO */ + PAD_CFG_GPI(GPP_H2, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H3, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H4, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H8, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H9, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H10, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H11, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H12, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H18, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H20, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H21, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPP_H23, NONE, PWROK), /* GPIO */ + /* -------- GPIO Group GPD -------- */ + PAD_CFG_GPI(GPD0, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPD1, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_GPI(GPD6, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPI(GPD7, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPC_HPD1 */ + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPD_HPD2 */ + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DDPE_HPD3 */ + PAD_CFG_GPI(GPP_I4, NONE, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ + PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), /* DDPD_CTRLDATA */ }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */ + + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* CLKOUT_LPC1 */ + + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */ + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* SUS_ACK# */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529 Gerrit-Change-Number: 33565 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 18

Change in ...coreboot[master]: mb/lenovo/x131e: enable mSATA slot
by James (Code Review) 28 Sep '19

28 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31364 Change subject: mb/lenovo/x131e: enable mSATA slot ...................................................................... mb/lenovo/x131e: enable mSATA slot Per google/stout. Functionality untested. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 --- M src/mainboard/lenovo/x131e/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31364/1 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 628c4eb..d20abdf 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -49,8 +49,8 @@ register "gpi6_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports - register "sata_port_map" = "0x1" + # Enable SATA ports 0 (2.5 inch) and 1 (mSATA) + register "sata_port_map" = "0x3" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" -- To view, visit https://review.coreboot.org/c/coreboot/+/31364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Gerrit-Change-Number: 31364 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/lenovo/x131e: correct USB port config
by James (Code Review) 27 Sep '19

27 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31365 Change subject: mb/lenovo/x131e: correct USB port config ...................................................................... mb/lenovo/x131e: correct USB port config Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc --- M src/mainboard/lenovo/x131e/romstage.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31365/1 diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..7e326e7 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -38,20 +38,20 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, - {1, 1, 0}, - {0, 1, 1}, - {1, 1, 1}, - {1, 0, 2}, - {1, 0, 2}, - {0, 0, 3}, - {0, 0, 3}, - {0, 1, 4}, - {1, 1, 4}, - {0, 0, 5}, - {0, 0, 5}, - {0, 0, 6}, - {1, 0, 6}, + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 0, -1}, /* P13: Bluetooth (no OC) */ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/c/coreboot/+/31365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Gerrit-Change-Number: 31365 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX
by Frans Hendriks (Code Review) 27 Sep '19

27 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33442 Change subject: vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX ...................................................................... vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXX To avoid confusion use VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT config values. Inlcude verfied_boot and mboot subdirectories as CPPFLAGS when measured boot or verified boot is enabled. This allows to generate binary with measured boot enabled only. BUG=N/A TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/Makefile.inc 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33442/1 diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index 26b324b..16f17fd 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,6 +1,6 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Eltan B.V. +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -16,12 +16,9 @@ subdirs-y += verified_boot subdirs-y += mboot -ifeq ($(CONFIG_MBOOT), y) +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/mboot CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/include -endif - -ifeq ($(CONFIG_VERIFIED_BOOT), y) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/verified_boot endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a Gerrit-Change-Number: 33442 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel: Fix regression on pcidev_
by Kyösti Mälkki (Code Review) 26 Sep '19

26 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34285 ) Change subject: soc/intel: Fix regression on pcidev_ ...................................................................... soc/intel: Fix regression on pcidev_ Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c M src/include/device/device.h M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pci_devs.h 8 files changed, 27 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34285/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index c1b0b06..05dfb30 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -234,6 +234,16 @@ return pcidev_path_on_root(PCI_DEVFN(dev, fn)); } +DEVTREE_CONST struct device *pcidev_debug_path_on_root(pci_devfn_t devfn, const char *func) +{ + DEVTREE_CONST struct device *dev = pcidev_path_on_root(devfn); + if (dev) + return dev; + + printk(BIOS_ERR, "BUG: %s requests hidden 00:%02x.%d\n", func, devfn >> 3, devfn & 7); + return dev_find_slot(0, devfn); +} + /** * Given an SMBus bus and a device number, find the device structure. * diff --git a/src/include/device/device.h b/src/include/device/device.h index 007c51f..12c258e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -275,8 +275,6 @@ void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, - unsigned int devfn); DEVTREE_CONST struct device *dev_find_next_pci_device( DEVTREE_CONST struct device *previous_dev); DEVTREE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, @@ -292,6 +290,10 @@ DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); +/* To be deprecated, avoid using. */ +DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); +DEVTREE_CONST struct device *pcidev_debug_path_on_root(pci_devfn_t devfn, const char *func); + void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index a334f63..c5eaf4c 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -22,8 +22,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 522e3eb..ae3e08f 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -25,8 +25,8 @@ #else #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #endif /* System Agent Devices */ diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 1bc028f..33814b0 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 303ba67..27f9e35 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -27,8 +27,8 @@ #if ENV_RAMSTAGE #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 1348f23b..0eddee2 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -23,8 +23,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 5acaaeb..d25942f 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_debug_path_on_root(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_debug_path_on_root(_PCH_DEVFN(slot, func), __func__) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) @@ -39,7 +39,7 @@ #define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func)) +#define SA_DEV_PEG(func) pcidev_debug_path_on_root(SA_DEVFN_PEG(func), __func__) #define SA_DEV_PEG0 SA_DEV_PEG(0) #define SA_DEV_PEG1 SA_DEV_PEG(1) #define SA_DEV_PEG2 SA_DEV_PEG(2) -- To view, visit https://review.coreboot.org/c/coreboot/+/34285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Gerrit-Change-Number: 34285 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

9 34

Change in ...coreboot[master]: src/mainboard: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 26 Sep '19

26 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33684 Change subject: src/mainboard: Use 'include <stdlib.h>' when appropriate ...................................................................... src/mainboard: Use 'include <stdlib.h>' when appropriate Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/gardenia/gpio.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/esd/atom15/gpio.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/intel/bayleybay_fsp/gpio.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/minnowmax/gpio.c M src/mainboard/intel/strago/gpio.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c M src/mainboard/roda/rk886ex/m3885.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/siemens/mc_tcu3/gpio.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/mainboard/ti/beaglebone/leds.c 20 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33684/1 diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 7c5f47b..2013fa5 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -14,8 +14,8 @@ */ #include <soc/southbridge.h> -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> #include "gpio.h" diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..66c49ad 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <commonlib/endian.h> +#include <stdlib.h> #include "fw_cfg.h" #include "fw_cfg_if.h" diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c index b9c7829..248e6d8 100644 --- a/src/mainboard/esd/atom15/gpio.c +++ b/src/mainboard/esd/atom15/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 9db26c7..9916df4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -16,7 +16,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <stdlib.h> +#include <stddef.h> #include <boardid.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..feb8c02 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853..6d180fd 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b357..4049b2d 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 9a6b64e..14298d4 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -14,9 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> +#include <stddef.h> #include <string.h> - #include <boardid.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c index 27b22c5..0ac1f9b 100644 --- a/src/mainboard/intel/bayleybay_fsp/gpio.c +++ b/src/mainboard/intel/bayleybay_fsp/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4c93051..801dbc8 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -19,9 +19,9 @@ #include <console/console.h> #include <device/device.h> #include <gpio.h> -#include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> + #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index b0f78c8..08b89d1 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ed9ae4b..0fe55d2 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -16,8 +16,8 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <stdlib.h> #include <boardid.h> + #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index 757d8da..9924ec0 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -11,16 +11,15 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <delay.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ - #include <Porting.h> #include <AGESA.h> #include <northbridge/amd/agesa/dimmSpd.h> + #include "sema.h" /* Write data block to slave on SMBUS0. */ diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c index 78d1ad6..32edaf5 100644 --- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c index c9d5426..e280e7c 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" #define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K) diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 60a4f48..4b97dfc 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -15,12 +15,11 @@ */ #include <types.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <delay.h> - #include <ec/acpi/ec.h> + #include "m3885.h" #define TH0LOW 80 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 237d551..3530ff4 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -14,8 +14,8 @@ * */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <arch/early_variables.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 23c6f96..d6d7106 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 8ac6ff1..3d43181 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include <string.h> #include <console/console.h> #include <soc/otp.h> diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index a4889b9..97b544a 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -13,8 +13,8 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <cpu/ti/am335x/gpio.h> -#include <stdlib.h> #include "leds.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Gerrit-Change-Number: 33684 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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2016

2015

2014

2013

coreboot-gerrit July 2019